)]}'
[{"id":"openocd~master~I1fc343c7f4f40ab0b9902b72fa8f010e1a15d2e3","project":"openocd","branch":"master","attention_set":{"1002530":{"account":{"_account_id":1002530},"last_update":"2026-06-22 16:10:52.000000000","reason":"\u003cGERRIT_ACCOUNT_1000021\u003e replied on the change","reason_account":{"_account_id":1000021}},"1001803":{"account":{"_account_id":1001803},"last_update":"2026-06-25 16:48:17.000000000","reason":"\u003cGERRIT_ACCOUNT_1000021\u003e replied on the change","reason_account":{"_account_id":1000021}}},"removed_from_attention_set":{},"hashtags":[],"change_id":"I1fc343c7f4f40ab0b9902b72fa8f010e1a15d2e3","subject":"target/oocd_capstone: fix RISC-V mode and ARM64 rename for capstone v6","status":"NEW","created":"2026-06-22 02:39:19.000000000","updated":"2026-06-25 16:48:17.000000000","submit_type":"CHERRY_PICK","insertions":12,"deletions":3,"total_comment_count":8,"unresolved_comment_count":0,"has_review_started":true,"meta_rev_id":"25f144519c4796c7bb9de07e91b0291debdaba4e","_number":9750,"owner":{"_account_id":1002530},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"NOT_READY","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014}},{"label":"Code-Review","status":"NEED"}]}]}]
