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{"id":"openocd~master~I5904fe66866de571d97f05fe986929ac93a7f834","project":"openocd","branch":"master","hashtags":[],"change_id":"I5904fe66866de571d97f05fe986929ac93a7f834","subject":"Flash driver for QUADSPI interface in various STM32 variants.","status":"ABANDONED","created":"2015-12-09 17:49:04.000000000","updated":"2017-03-15 04:50:07.000000000","total_comment_count":22,"unresolved_comment_count":0,"has_review_started":true,"meta_rev_id":"63a217e19cdce9e8c769ae912cbfbc965b3d72e8","_number":3162,"owner":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"actions":{},"labels":{"Verified":{"rejected":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"value":0,"permitted_voting_range":{"min":-1,"max":1},"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},{"_account_id":1001120,"name":"Claudio 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\n\nhttp://build.openocd.org/job/openocd-gerrit/6708/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6127/ : FAILURE","accounts_in_message":[],"_revision_number":1},{"id":"3eff417e41cf146d9962d1a7c00691023f801f16","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2015-12-11 19:37:33.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"8f424cc6de9e5efa9d4e5dc8b0b7f23f710608d6","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2015-12-11 19:40:01.000000000","message":"Patch Set 2: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/6715/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6134/ : FAILURE","accounts_in_message":[],"_revision_number":2},{"id":"77e83b88ab84d7c20f2f8de6d9a046099de3a032","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2015-12-16 14:15:58.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"12093594b297c77f53643bbb906e5414ab235353","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2015-12-16 14:39:07.000000000","message":"Patch Set 3: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/6731/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6150/ : FAILURE","accounts_in_message":[],"_revision_number":3},{"id":"405788811d7ef4c65766269bd51ef4c3e9d0d2c6","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2015-12-16 15:18:37.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"2731a8f7f50dd4bb6f2032b0685b5106131a9e55","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2015-12-16 15:55:58.000000000","message":"Patch Set 4: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/6732/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6151/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"28f0b5239707f9086c40f83e776063d2d8685ee6","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2015-12-16 16:16:52.000000000","message":"Patch Set 4:\n\nWhat about introducing tcl/board/stm32(f7|l4)discovery_qspi.cfg that source xxxdiscovery.cfg and init the qspi. Otherwise more board files like for nucleo-l476 are needed. At the moment xxxdiscovery.cfg is good for any board using STLink-V2.1.","accounts_in_message":[],"_revision_number":4},{"id":"85b0126e34b40acccdb936abb1464be5479126fe","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2015-12-16 16:18:44.000000000","message":"Patch Set 4:\n\nThat last 4 lines in yoy new cfg files are constant. Why not move them to the loader? QSPI on F446 would probably need then too.","accounts_in_message":[],"_revision_number":4},{"id":"7ad1474934c1be347d6d5c3b3a4b85e90b814d22","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2015-12-16 17:29:52.000000000","message":"Patch Set 4:\n\nThe qspi-configuration is rather not re-usable, e. g. the pin mapping is highly configurable, and the speed of the external spi flash is not fixed. So no chance to use the same for two different boards even if same mpu chip is used, sigh ...\nActually, the path \u0027.../board/stm...discovery.cfg\u0027 suggests that it is intended just for that specific board, and not for the chip in general or e. g. nucleo boards. There\u0027s already \u0027.../target/stm32f7.cfg\u0027 for the general stuff (in particular, the flash *driver* initialization is tied to the chip, hence in stm32f7.cfg). If to keep things separated, there could be an intermediate \u0027stm32f7_with_stlink.cfg\u0027 but that style had been marked as deprecated?!\nThat\u0027s one point why the last 4 lines in the board cfg are *NOT* hardwired in the loader (and the rather ugly passing of the CCR values to the loader).\nSecond point is that this way spi flash is accessible in memory mapped mode even if the internal flash is blank.\nAfter all, this memory mapped mode is the only reason to have the flash driver integrated into openocd. For an ordinary spi flash with  a separate address space this wouldn\u0027t make much sense.","accounts_in_message":[],"_revision_number":4},{"id":"14317f5534dd4f469a6259683ebbdc802aad4393","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2015-12-17 10:14:31.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/6733/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6152/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"a45cd95d733d036cb200b941661a31551779d171","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2016-02-29 21:36:33.000000000","message":"Patch Set 4:\n\n(5 comments)\n\nWorking as you said on F7 discovery board.","accounts_in_message":[],"_revision_number":4},{"id":"3237d2964eb82a1fe91d32902bb53d70547351e7","author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"real_author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"date":"2016-03-02 21:17:21.000000000","message":"Patch Set 4:\n\n(1 comment)\n\njust a reply to show the comment.","accounts_in_message":[],"_revision_number":4},{"id":"04ed2e6ebee4f4b0072415fd60bd6306ad67e004","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-03-08 18:30:06.000000000","message":"Patch Set 4:\n\n(5 comments)","accounts_in_message":[],"_revision_number":4},{"id":"e63ce519f3d79a1073b1d298cb28d032cea24a80","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-06-19 11:13:47.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"c8752af3bf6a24e1150cbe70c26e771074f506ab","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-06-19 11:18:24.000000000","message":"Patch Set 5: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/7550/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6957/ : FAILURE","accounts_in_message":[],"_revision_number":5},{"id":"1b3bb117738c82d13aeb1b6e1c185b5ace0180d1","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-06-19 12:11:32.000000000","message":"Patch Set 5:\n\nLine 824 / 870: Checking return value doesnt\u0027t help. id1 and id2 would not be initialized at all e. g. in case of error. But even if there is no error, id2 will be uninitialized in single flash mode. So the compiler is quite right.","accounts_in_message":[],"_revision_number":5},{"id":"7c3d3964e75c6c1ad9a55695906d22529ac64f67","author":{"_account_id":1001120,"name":"Claudio Lanconelli","email":"claudiolanconelli@gmail.com","username":"lancos"},"real_author":{"_account_id":1001120,"name":"Claudio Lanconelli","email":"claudiolanconelli@gmail.com","username":"lancos"},"date":"2016-06-23 10:25:56.000000000","message":"Patch Set 5:\n\n(1 comment)\n\nCan you rebase on top of #3526 so I can test it? thanks","accounts_in_message":[],"_revision_number":5},{"id":"d767ebf63d91ec7d75725062a3dd7fca2cdc8876","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-06-26 12:11:54.000000000","message":"Patch Set 5:\n\nNot really sure. The QSPI is part of the chip. Registering the driver doesn\u0027t activate the QSPI system or interfere with system operation in any way even if there is no flash chip connected?! Only \"probe\" or \"write_image\" (in the QSPI range) might cause trouble. But even then, as long as the alternate function mapping for the corresponding pins is not done, nothing will really happen. \nBut I\u0027ll think about that.","accounts_in_message":[],"_revision_number":5},{"id":"fb63f33389859854542d3368a11707f77f72a734","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-06-26 18:01:18.000000000","message":"Uploaded patch set 6.","accounts_in_message":[],"_revision_number":6},{"id":"b67da6d8ac469deb2d8f13362fa65d957bb4b291","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-06-26 18:14:16.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/7570/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6977/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"7fa97a8213946d2b3f759e727b441ce9a167159e","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2016-08-14 00:15:36.000000000","message":"Patch Set 6: Code-Review-1\n\n(1 comment)\n\nLooking good except for the flow-control changing macros which are an absolute blocker for me.","accounts_in_message":[],"_revision_number":6},{"id":"16fb4c28242c8d318172be475b59935728802220","author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"real_author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"date":"2016-12-10 11:05:03.000000000","message":"Patch Set 6: Code-Review-1\n\n(9 comments)\n\nUseful patch but in this current form it\u0027s confusing both to the users (need to unprotect before any write operation) and to the developers, afaict.","accounts_in_message":[],"_revision_number":6},{"id":"bfdef3de81d1691478d305de1b0bcb567a8f49c9","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-12-24 13:25:16.000000000","message":"Uploaded patch set 7.","accounts_in_message":[],"_revision_number":7},{"id":"776a1e87b68dbbcd63810174b15cd3e5a9250672","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2016-12-24 13:27:35.000000000","message":"Abandoned\n\nSubstantial rewrite done.","accounts_in_message":[],"_revision_number":7},{"id":"6b70aaad9e56745a97b430047055336315fd4371","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-12-24 13:30:00.000000000","message":"Patch Set 7:\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/8443/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/7822/ : FAILURE","accounts_in_message":[],"_revision_number":7},{"id":"0f8662f48319c8ddac506e936c58b74808e10682","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2017-02-17 18:01:45.000000000","message":"Restored","accounts_in_message":[],"_revision_number":7},{"id":"4ff2c3dc5140cd5b98bef22cb58b31f756b96e2c","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2017-02-17 18:02:01.000000000","message":"Uploaded patch set 8: Patch Set 7 was rebased.","accounts_in_message":[],"_revision_number":8},{"id":"21fad09de126f1a1bf0ce5fc56964233ac52aba4","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2017-02-17 18:12:53.000000000","message":"Patch Set 8: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/8663/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/8040/ : FAILURE","accounts_in_message":[],"_revision_number":8},{"id":"1960a6f882af18a46750beb9601d3efe8392b445","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2017-02-18 10:38:42.000000000","message":"Abandoned","accounts_in_message":[],"_revision_number":8},{"id":"0651faa80bd23852003f2a30e47fcdbfd891fc51","author":{"_account_id":1001322,"name":"Keir Mierle","email":"mierle@gmail.com"},"real_author":{"_account_id":1001322,"name":"Keir Mierle","email":"mierle@gmail.com"},"date":"2017-03-14 23:15:20.000000000","message":"Patch Set 8:\n\nWhy was this abandoned? It\u0027d be really nice to get this functionality merged.","accounts_in_message":[],"_revision_number":8},{"id":"63a217e19cdce9e8c769ae912cbfbc965b3d72e8","author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"real_author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"date":"2017-03-15 04:50:07.000000000","message":"Patch Set 8:\n\nPlease see http://openocd.zylin.com/#/c/3918/","accounts_in_message":[],"_revision_number":8}],"current_revision":"f0f25e1046ef58f0c86a2ba6366f409dbc5ca689","revisions":{"4bf4ffabcfdf18e28b9887bf435e41ab14d2a477":{"kind":"REWORK","_number":6,"created":"2016-06-26 18:01:18.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/6 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"406f4d1c68330e3bf8d9db4e402fd8802a5c79e2","subject":"stm32f7x.cfg: Fix expected JTAG id."}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-06-26 16:37:32.000000000","tz":120},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-06-26 18:00:19.000000000","tz":120},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7, F4 and L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F4/F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nIds for F446, F469/479 and F767/777 added.\n\nSome provisions for 4 byte addresses added, but that\u0027s still untested.\n\nSupport for internal flash of F7 variants and Cortex-M7 FPU moved from\nthis patch into #3526 and #3131, resp.\nFor testing with e.g. F7-discovery these are not absolutely required but\nrather useful.\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"cd45f3e13bb3d8047f28dcaaf321bf3e98dd0c33":{"kind":"REWORK","_number":7,"created":"2016-12-24 13:25:16.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/7 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"0c2de8b3d0bcc79cac026945d7f29989bbe4084f","subject":"board: add configuration for freescale twr-vf65gs10 system module"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-06-26 16:37:32.000000000","tz":120},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:31:28.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7, F4 and L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F4/F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nIds for F446, F469/479 and F767/777 added.\n\nSome provisions for 4 byte addresses added, but that\u0027s still untested.\n\nSupport for internal flash of F7 variants and Cortex-M7 FPU moved from\nthis patch into #3526 and #3131, resp.\nFor testing with e.g. F7-discovery these are not absolutely required but\nrather useful.\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"02110e1c7a79139e3ab528931669ab424014aa82":{"kind":"REWORK","_number":4,"created":"2015-12-16 15:18:37.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/4 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e0bad0553ff469fe8621280bf92cbf5f46ad4254","subject":"stm32f2x options_read, options_write and FPU support for STM32F7"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-02 20:14:54.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-16 15:18:16.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7 and STM32L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"afdad4756461f0814b8b8a4cf977ad143c273ee5":{"kind":"REWORK","_number":5,"created":"2016-06-19 11:13:47.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/5 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e503696e2dd5ea55a357a7e39d02b80b534bff62","subject":"stm32f2x options_read, options_write and FPU support for STM32F7"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-02 20:14:54.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-06-19 08:13:33.000000000","tz":120},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7 and STM32L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"348989dea68a46cfe30d25a51807370bdf5eefb4":{"kind":"REWORK","_number":2,"created":"2015-12-11 19:37:33.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/2 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e0bad0553ff469fe8621280bf92cbf5f46ad4254","subject":"stm32f2x options_read, options_write and FPU support for STM32F7"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-02 20:14:54.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-10 20:44:20.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7 and STM32L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"024c9ddd5aa391a2dcd86445bba1c294e119babc":{"kind":"REWORK","_number":3,"created":"2015-12-16 14:15:58.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/3 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e0bad0553ff469fe8621280bf92cbf5f46ad4254","subject":"stm32f2x options_read, options_write and FPU support for STM32F7"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-02 20:14:54.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-16 14:04:24.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7 and STM32L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"4f025a42e02b2a0821a7d37fbfaeb1f172e41315":{"kind":"REWORK","_number":1,"created":"2015-12-09 17:49:04.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/1 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e0bad0553ff469fe8621280bf92cbf5f46ad4254","subject":"stm32f2x options_read, options_write and FPU support for STM32F7"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-02 20:14:54.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2015-12-09 17:42:38.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7 and STM32L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"f0f25e1046ef58f0c86a2ba6366f409dbc5ca689":{"kind":"TRIVIAL_REBASE","_number":8,"created":"2017-02-17 18:02:01.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/62/3162/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/62/3162/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/8 \u0026\u0026 git checkout -b change-3162 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/62/3162/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/62/3162/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"7c85165bc1a606883faa9bec51ebefbc652301f4","subject":"aarch64: Fix #include guards"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-06-26 16:37:32.000000000","tz":120},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2017-02-17 17:26:55.000000000","tz":60},"subject":"Flash driver for QUADSPI interface in various STM32 variants.","message":"Flash driver for QUADSPI interface in various STM32 variants.\n\nDriver for the QUADSPI interface implemented in STM32F7, F4 and L4.\nThe QUADSPI interface has to be initialized by a board specific script\nin advance. The flash driver uses flash configuration based on the\ncurrent register values, so speed, single/dual (F4/F7 only) configuration\netc. must be initialized properly. Watchdogs and interrupts must be\ndisabled, i. e. flash programming has to start from reset state!\nTested on STM32F746 and STM32L476 Discovery boards. Both use a single\nSPI flash, so dual mode is untested!\nAdress and data are transferred on single line only, that\u0027s supported\nby any SPI flash. Flash permanently (via non-volatile regs) set to\ndual or quad line mode is NOT supported.\n\nAddress of RCC_CR corrected in stm32l4.cfg, and clock increased to 48 MHz\n\nIds for F446, F469/479 and F767/777 added.\n\nSome provisions for 4 byte addresses added, but that\u0027s still untested.\n\nSupport for internal flash of F7 variants and Cortex-M7 FPU moved from\nthis patch into #3526 and #3131, resp.\nFor testing with e.g. F7-discovery these are not absolutely required but\nrather useful.\n\nChange-Id: I5904fe66866de571d97f05fe986929ac93a7f834\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}