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{"id":"openocd~master~I200286c0b980369f74e8f1e497bc5e565ddb616d","project":"openocd","branch":"master","hashtags":[],"change_id":"I200286c0b980369f74e8f1e497bc5e565ddb616d","subject":"tcl/target/stm32l4x.cfg: Reduce adapter speed before reset.","status":"MERGED","created":"2016-02-28 18:35:54.000000000","updated":"2016-08-13 08:26:42.000000000","submitted":"2016-08-13 08:26:42.000000000","submitter":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"total_comment_count":2,"unresolved_comment_count":0,"has_review_started":true,"meta_rev_id":"a18c187c6de4a3abfcada418cd6f6424a54e51b9","_number":3366,"owner":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"actions":{},"labels":{"Verified":{"approved":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"value":0,"_account_id":1000725,"name":"Andreas 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16:54:00.000000000","updated_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"reviewer":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"state":"REVIEWER"},{"updated":"2016-05-31 17:44:40.000000000","updated_by":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"reviewer":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"state":"REVIEWER"},{"updated":"2016-08-13 08:26:41.000000000","updated_by":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"reviewer":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"state":"REVIEWER"}],"messages":[{"id":"688e0d4027b8dba897b68a5106caca5398332cea","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-02-28 18:35:54.000000000","message":"Uploaded patch set 1.","accounts_in_message":[],"_revision_number":1},{"id":"0ad7ce729bd8cc07ec396a3695543c70c8acd6de","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-02-28 18:54:23.000000000","message":"Patch Set 1: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/7150/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/6559/ : SUCCESS","accounts_in_message":[],"_revision_number":1},{"id":"6218af7f0125a21a029b7c1349ff951bec19d0a7","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-05-06 11:17:15.000000000","message":"Patch Set 2: Patch Set 1 was rebased","accounts_in_message":[],"_revision_number":1},{"id":"681041875a20c07e585cb6883b26ea954691c4e2","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-05-06 11:30:38.000000000","message":"Patch Set 2: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit-build/6739/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit/7330/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"951442e44443e4b914704b65fe64e15be386aea3","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-18 07:28:30.000000000","message":"Patch Set 2:\n\n(1 comment)\n\nI tested your change with STM32L476 disco kit.\nOn-board ST-Link V2.1 works with adapter_khz \u003d 18 * MCU clock\n(tested lowest MSIRANGE ~ 100kHz, adapter_khz 1800 works,\nadapter_khz 4000 does not) so actually no need for clock switching\nwith ST-Link. I have not tested with ftdi, there might be a problem...\n\nAt least a misaddressed write should be corrected:","accounts_in_message":[],"_revision_number":2},{"id":"767a673831ff5445d65fdc7eea124f9c203b5655","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-05-18 08:58:34.000000000","message":"Patch Set 2:\n\nI asked for hard facts about the relation between MCU and SWD/JTAG clock some time ago on the list, but no hard facts turned up. However the suspicion about Tga Clock \u003c 8 * MCU clock was held up.\n\nI will correct RCC_CR in a seperate patch.\n\nShould I abandon thi patch?","accounts_in_message":[],"_revision_number":2},{"id":"bafa780cc42fc24c2f191fbc500d608f53434ff1","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-18 20:58:42.000000000","message":"Patch Set 2:\n\nDo not abandon. cfg needs a fix in any case: either this one or remove clock fiddling at all.\n\nI\u0027m afraid there is no universal answer to SWCLK / HCLK ratio.\nI\u0027m sure that modern ARM implementations can make faster than used to be SWCLK \u003d SYSCLK/6. See\nhttp://infocenter.arm.com/help/index.jsp?topic\u003d/com.arm.doc.faqs/ka16824.html\nbut do not take it too seriously. Cypress states SWDCLK ≤ 1/3 CPU clock freq for PSoC4 (the only documented case I\u0027m aware of). I tested Atmel\u0027s SAM4L and SAMD and both worked at SWDCLK \u003d SYSCLK/2 (tested before WAIT was implemented in ftdi driver).\n\nI\u0027ve seen a recommendation to set SWDCLK \u003c SYSCLK * 10 probably somewhere in IAR Embedded Workbench UI (installed as demo, now expired) when used with STM32L4 disco. It roughly corresponds with my test. Can you test a STM32L4 with a ftdi based adapter? I\u0027m not sure if it is possible to use external swd with STM32L4 disco.","accounts_in_message":[],"_revision_number":2},{"id":"b453d6ff7d2802ac3121e97d415619b14829b556","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-21 08:04:49.000000000","message":"Patch Set 2:\n\nI tried to connect a SWD adapter to L4disco kit externally.\nST-Link v2 worked, but ftdi and vsllink did not even with adapter_khz 5.\nftdi:\nDebug: 274 59 ftdi.c:1150 ftdi_swd_switch_seq(): JTAG-to-SWD\nDebug: 275 59 ftdi.c:1004 ftdi_swd_run_queue(): Executing 2 queued transactions\nDebug: 276 104 ftdi.c:1036 ftdi_swd_run_queue(): JUNK DP read reg 0 \u003d ff3f019f\n\nDon\u0027t have time to investigate it deeper now.","accounts_in_message":[],"_revision_number":2},{"id":"8f9656ed44e3aee0548c1d2bc559da9ff94aeae8","author":{"_account_id":1000725,"name":"Andreas Färber","email":"afaerber@suse.de","username":"afaerber"},"real_author":{"_account_id":1000725,"name":"Andreas Färber","email":"afaerber@suse.de","username":"afaerber"},"date":"2016-05-21 10:52:55.000000000","message":"Patch Set 2:\n\n\u003e Debug: 276 104 ftdi.c:1036 ftdi_swd_run_queue(): JUNK DP read reg 0\n \u003e \u003d ff3f019f\n\nSounds like a collision when connecting two SWD adapters - maybe the on-board ST-Link was not jumpered off properly?","accounts_in_message":[],"_revision_number":2},{"id":"84db53c8bdfc51efa49b1474870a71a7c439f345","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-21 14:04:29.000000000","message":"Patch Set 2:\n\n\u003e Sounds like a collision when connecting two SWD adapters - maybe\n \u003e the on-board ST-Link was not jumpered off properly?\n\nDon\u0027t think so. All 3 jumpers (SWDCLK, SWDIO and NRST) were removed. Signals from ext adapter were connected to two pins for jumpers and\nexternal ST-Link worked well in same config.","accounts_in_message":[],"_revision_number":2},{"id":"f468ac40609fe3d548878590b0746a0797fa13f2","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-24 02:31:42.000000000","message":"Patch Set 2:\n\nFinally solved ftdi adapter issue: STM32L4 is more sensitive to SWCLK signal edge slopes than other MCUs. Therefore is does not work with unbuffered ft2232c (really old), even if ever MCU I worked with does work. Inserting a HC125 buffer to SWCLK path solves the problem.\n\nftdi works up to adapter_khz 0.8 * HCLK, so this change is necessary. Alternatively you can reduce adapter_khz to 1800 as one universal speed.\n\nBTW If you keep speed switching, I propose to change base khz to 480 - stlink native speed. It saves message \"Info : Unable to match requested speed 500 kHz, using 480 kHz\".","accounts_in_message":[],"_revision_number":2},{"id":"7de70577aa3cfe0d64923b63e39741cbb14ade0a","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-05-24 11:39:39.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"8b9bdb7c36ae8690582542002230f36cf4084c9a","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-05-24 11:42:08.000000000","message":"Patch Set 3:\n\nCorrected the number of waitstates to the values the comment indicated.\nChange in comments about SWD/JTAG and HCLK relation.","accounts_in_message":[],"_revision_number":3},{"id":"cd85803af626a8ca91cf107a25596c2512454c9c","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-05-24 11:52:21.000000000","message":"Patch Set 3: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit-build/6923/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit/7516/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"7c204c698eab82bf730b5bda4b4164e432f959ab","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-24 19:48:16.000000000","message":"Patch Set 3:\n\n(1 comment)\n\nLooks good","accounts_in_message":[],"_revision_number":3},{"id":"29a34614af0e440df4a52fe23690ef64f1463fae","author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"real_author":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"date":"2016-05-31 16:35:41.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"737594b9ad54c28a1a5449bde410a67bde0bbdd5","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2016-05-31 16:54:00.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit-build/6944/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit/7537/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"63d3c241519853e040c9fd9c1ee4d92838d3498e","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2016-05-31 17:44:40.000000000","message":"Patch Set 4: Code-Review+2","accounts_in_message":[],"_revision_number":4},{"id":"e3a12fd22410d8dc2538468809cc7e5eaee7b98b","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2016-07-04 23:14:33.000000000","message":"Patch Set 4:\n\nPlease note that there may be different kinds of \"not working\".\n\nThe most basic kind is when clocking the SWCLK faster than the debug logic can handle. For ARM JTAG this really was about 1/6 of the CPU clock, since the JTAG signals, including TCK, was synchronized through several flip-flops clocked by the CPU clock. For SWD, I have not seen such requirement and from testing I strongly suspect that the debug logic is fully clocked by SWCLK and synchronized at the AP. That would mean the maximum frequency depends not on CPU frequency but more on signal integrity.\n\nThe other kind of \"not working\" is when you try to access debug resources in the CPU clock domain but you don\u0027t allow time for the access to complete before you perform the next. This will result in a WAIT response and the idea is that the debugger should retry the transaction until it completes. The ftdi driver does *not* handle WAIT responses yet but relies on the user to insert enough idle clock cycles between each access to allow the access to complete. This is the memaccess_tck command.\n\nSo before settling on a \"0.8 * CPU clock\" rule of thumb for ftdi adapters, make sure you\u0027re talking about frequency failure and not latency failure. Otherwise, once ftdi gains WAIT support, that rule will become just as obsolete as the 1/6*CPU clock for JTAG. Latency errors will give WAIT faults, frequency errors will most likely give JUNK responses (protocol error).","accounts_in_message":[],"_revision_number":4},{"id":"a18c187c6de4a3abfcada418cd6f6424a54e51b9","date":"2016-08-13 08:26:42.000000000","message":"Change has been successfully cherry-picked as 20466e5374e563a61b3c4c859265623451be463c by Andreas Fritiofson","accounts_in_message":[],"_revision_number":4}],"current_revision":"20466e5374e563a61b3c4c859265623451be463c","revisions":{"0b1e2a478dfcfbb458255ef016d7d96756ea51ca":{"kind":"REWORK","_number":3,"created":"2016-05-24 11:39:39.000000000","uploader":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"ref":"refs/changes/66/3366/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/66/3366/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/66/3366/3 \u0026\u0026 git checkout -b change-3366 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11:39:08.000000000","tz":120},"subject":"tcl/target/stm32l4x.cfg: Reduce adapter speed before reset.","message":"tcl/target/stm32l4x.cfg: Reduce adapter speed before reset.\n\nChange-Id: I200286c0b980369f74e8f1e497bc5e565ddb616d\nSigned-off-by: Uwe Bonnes \u003cbon@elektron.ikp.physik.tu-darmstadt.de\u003e\n"}},"b0c25aa71a7a06132025bbb8e5377d01c989fdef":{"kind":"TRIVIAL_REBASE","_number":2,"created":"2016-05-06 11:17:15.000000000","uploader":{"_account_id":1000715,"name":"Uwe Bonnes","email":"bon@elektron.ikp.physik.tu-darmstadt.de","username":"UBonnes"},"ref":"refs/changes/66/3366/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/66/3366/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/66/3366/2 \u0026\u0026 git checkout -b change-3366 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/66/3366/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch 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