)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":29,"context_line":"  W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI with two W25Q128FV,"},{"line_number":30,"context_line":"  sample cfg files included"},{"line_number":31,"context_line":"- read/verify/erase_check uses indirect read mode to work around silicon bug in"},{"line_number":32,"context_line":"  H7, L4+ and MP1 memory mapped mode (last byte not readable, accessing last byte"},{"line_number":33,"context_line":"  causes debug interface to hang"},{"line_number":34,"context_line":"- octospi supported only in single/dual 1-line, 2-line, 4-line"},{"line_number":35,"context_line":"  and single 8-line modes, (not in hyper flash mode)"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"8e7fc396_9c2fcd85","line":32,"updated":"2019-06-26 05:41:10.000000000","message":"s/H7/F7/, right? As per my previous comment? You mentioned this in one of the files too.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":29,"context_line":"  W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI with two W25Q128FV,"},{"line_number":30,"context_line":"  sample cfg files included"},{"line_number":31,"context_line":"- read/verify/erase_check uses indirect read mode to work around silicon bug in"},{"line_number":32,"context_line":"  H7, L4+ and MP1 memory mapped mode (last byte not readable, accessing last byte"},{"line_number":33,"context_line":"  causes debug interface to hang"},{"line_number":34,"context_line":"- octospi supported only in single/dual 1-line, 2-line, 4-line"},{"line_number":35,"context_line":"  and single 8-line modes, (not in hyper flash mode)"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"8e7fc396_5f9127fa","line":32,"in_reply_to":"8e7fc396_5c8b751b","updated":"2019-07-29 19:35:48.000000000","message":"Oh, that must be something undocumented then? I see four errata for the QUADSPI in the STM32F745 (errata rev 7: extra data in FIFO at end of read transfer, first nibble not written after dummy phase, wrong data from memory-mapped read after an indirect mode operation, and memory-mapped read may fail with timeout counter), and only three for the STM32H743 (errata rev 6: first nibble not written after dummy phase, CCR hangs when CR cleared, and cannot be used in indirect mode when only data phase activated).","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":29,"context_line":"  W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI with two W25Q128FV,"},{"line_number":30,"context_line":"  sample cfg files included"},{"line_number":31,"context_line":"- read/verify/erase_check uses indirect read mode to work around silicon bug in"},{"line_number":32,"context_line":"  H7, L4+ and MP1 memory mapped mode (last byte not readable, accessing last byte"},{"line_number":33,"context_line":"  causes debug interface to hang"},{"line_number":34,"context_line":"- octospi supported only in single/dual 1-line, 2-line, 4-line"},{"line_number":35,"context_line":"  and single 8-line modes, (not in hyper flash mode)"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"8e7fc396_5c8b751b","line":32,"in_reply_to":"8e7fc396_9c2fcd85","updated":"2019-07-23 20:46:58.000000000","message":"No, definitely H7. Didn\u0027t encounter any problem with F7 (F746, F767, F723) at all, only H743 and L4+. Can\u0027t say anything re. MP1 except that\u0027s in teh errata sheet.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"contrib/loaders/flash/stmqspi/Makefile":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9db8a79b52b38c5e6ca4ae4f4bfdaba913803bb3","unresolved":false,"context_lines":[{"line_number":23,"context_line":"\t$(OBJCOPY) -S -O binary $\u003c $@"},{"line_number":24,"context_line":""},{"line_number":25,"context_line":"%.c: %.bin"},{"line_number":26,"context_line":"\t@echo -e \"\\tstatic const uint8_t $(@:.c\u003d)_code[] \u003d {\" \u003e $@"},{"line_number":27,"context_line":"\t@cat \"$\u003c\" | xxd -i | sed -r \u0027s/^\\s*/\\t\\t/\u0027 \u003e\u003e $@"},{"line_number":28,"context_line":"\t@echo -e \"\\t};\" \u003e\u003e $@"},{"line_number":29,"context_line":"\tsed -i -e \"/$(patsubst %.c,%,$@).*code\\\\[\\\\]/,/};/d\" \"$(CODE)\" \\"},{"line_number":30,"context_line":"\t\t-e \"/see\\\\s\\+contrib.*$(patsubst %.c,%,$@)/r$@\""},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"clean:"},{"line_number":33,"context_line":"\trm -f *.c *.lst *.pdf"}],"source_content_type":"application/octet-stream","patch_set":3,"id":"2e489777_97be94f9","line":30,"range":{"start_line":26,"start_character":0,"end_line":30,"end_character":49},"updated":"2018-01-16 15:35:11.000000000","message":"Please use much simpler way by #include in driver code. See e.g. contrib/loaders/flash/xmc1xxx/","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6e4bd383acec2d38cc13643adf2f8fcac817911e","unresolved":false,"context_lines":[{"line_number":23,"context_line":"\t$(OBJCOPY) -S -O binary $\u003c $@"},{"line_number":24,"context_line":""},{"line_number":25,"context_line":"%.c: %.bin"},{"line_number":26,"context_line":"\t@echo -e \"\\tstatic const uint8_t $(@:.c\u003d)_code[] \u003d {\" \u003e $@"},{"line_number":27,"context_line":"\t@cat \"$\u003c\" | xxd -i | sed -r \u0027s/^\\s*/\\t\\t/\u0027 \u003e\u003e $@"},{"line_number":28,"context_line":"\t@echo -e \"\\t};\" \u003e\u003e $@"},{"line_number":29,"context_line":"\tsed -i -e \"/$(patsubst %.c,%,$@).*code\\\\[\\\\]/,/};/d\" \"$(CODE)\" \\"},{"line_number":30,"context_line":"\t\t-e \"/see\\\\s\\+contrib.*$(patsubst %.c,%,$@)/r$@\""},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"clean:"},{"line_number":33,"context_line":"\trm -f *.c *.lst *.pdf"}],"source_content_type":"application/octet-stream","patch_set":3,"id":"0e83d3c5_02190a27","line":30,"range":{"start_line":26,"start_character":0,"end_line":30,"end_character":49},"in_reply_to":"2e489777_97be94f9","updated":"2018-01-20 18:36:26.000000000","message":"I\u0027ll see to that.","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"}],"contrib/loaders/flash/stmqspi/stmqspi_crc32.S":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":64,"context_line":"\twait_busy"},{"line_number":65,"context_line":"\tmov\t\tr7, r2\t\t\t\t\t\t/* get current start address */"},{"line_number":66,"context_line":"\torrs\tr7, r7, r1\t\t\t\t\t/* end of current page */"},{"line_number":67,"context_line":"\tsubs\tr7, r7, r2\t\t\t\t\t/* count to end of page */"},{"line_number":68,"context_line":"\tcmp\t\tr7, r0\t\t\t\t\t\t/* if this count \u003c\u003d remaining */"},{"line_number":69,"context_line":"\tbls\t\twrite_dlr\t\t\t\t\t/* then read to end of page */"},{"line_number":70,"context_line":"\tmov\t\tr7, r0\t\t\t\t\t\t/* else read all remaining */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_1c53bd1b","line":67,"range":{"start_line":67,"start_character":24,"end_line":67,"end_character":29},"updated":"2019-06-26 05:41:10.000000000","message":"This is actually count−1. The algorithm uses it correctly, but could the comment be updated to reflect this? (note, this applies to the read and write files as well)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":64,"context_line":"\twait_busy"},{"line_number":65,"context_line":"\tmov\t\tr7, r2\t\t\t\t\t\t/* get current start address */"},{"line_number":66,"context_line":"\torrs\tr7, r7, r1\t\t\t\t\t/* end of current page */"},{"line_number":67,"context_line":"\tsubs\tr7, r7, r2\t\t\t\t\t/* count to end of page */"},{"line_number":68,"context_line":"\tcmp\t\tr7, r0\t\t\t\t\t\t/* if this count \u003c\u003d remaining */"},{"line_number":69,"context_line":"\tbls\t\twrite_dlr\t\t\t\t\t/* then read to end of page */"},{"line_number":70,"context_line":"\tmov\t\tr7, r0\t\t\t\t\t\t/* else read all remaining */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_7c90b146","line":67,"range":{"start_line":67,"start_character":24,"end_line":67,"end_character":29},"in_reply_to":"8e7fc396_1c53bd1b","updated":"2019-07-23 20:46:58.000000000","message":"Well, the -1 is already mentioned above for the DLR, but ok.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":73,"context_line":"\tldr\t\tr7, ccr_page_read\t\t\t/* CCR for page read */"},{"line_number":74,"context_line":"\tstr\t\tr7, [r3, #QSPI_CCR]\t\t\t/* initiate transfer */"},{"line_number":75,"context_line":"\tstr\t\tr2, [r3, #QSPI_AR]\t\t\t/* store SPI start address */"},{"line_number":76,"context_line":"\tldr\t\tr7, [r3, #QSPI_SR]\t\t\t/* wait for command startup */"},{"line_number":77,"context_line":"\tldr\t\tr6, \u003d0x04C11DB7\t\t\t\t/* CRC32 polynomial */"},{"line_number":78,"context_line":"read_loop:"},{"line_number":79,"context_line":"\tldrb\tr7, [r5]\t\t\t\t\t/* read next byte from DR */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_7c4e7174","line":76,"updated":"2019-06-26 05:41:10.000000000","message":"What does this line do? It seems that r7 is thrown away two lines down in the ldrb. (note, this applies to the blank check, read, and write files as well)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":73,"context_line":"\tldr\t\tr7, ccr_page_read\t\t\t/* CCR for page read */"},{"line_number":74,"context_line":"\tstr\t\tr7, [r3, #QSPI_CCR]\t\t\t/* initiate transfer */"},{"line_number":75,"context_line":"\tstr\t\tr2, [r3, #QSPI_AR]\t\t\t/* store SPI start address */"},{"line_number":76,"context_line":"\tldr\t\tr7, [r3, #QSPI_SR]\t\t\t/* wait for command startup */"},{"line_number":77,"context_line":"\tldr\t\tr6, \u003d0x04C11DB7\t\t\t\t/* CRC32 polynomial */"},{"line_number":78,"context_line":"read_loop:"},{"line_number":79,"context_line":"\tldrb\tr7, [r5]\t\t\t\t\t/* read next byte from DR */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_1c95fd35","line":76,"in_reply_to":"8e7fc396_7c4e7174","updated":"2019-07-23 20:46:58.000000000","message":"Without that (or maybe a DSB could be enough) the operation sometimes failed: First access to the FIFO follows right away. Apparently (depending on various clock settings) this access could happen before command processing inside the QSPI has started properly. So simply a small delay, and the length is mildly related to the clock settings. On could explicitly check for the BUSY bit to become set, but it turned out not to be really necessary.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":91,"context_line":"\ttst\t\tr2, r1\t\t\t\t\t\t/* page end ? */"},{"line_number":92,"context_line":"\tbne\t\tread_loop\t\t\t\t\t/* if not, then next byte */"},{"line_number":93,"context_line":"page_end:"},{"line_number":94,"context_line":"\twait_busy\t\t\t\t\t\t\t/* wait for transfer completed */"},{"line_number":95,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":96,"context_line":"\t.pool"},{"line_number":97,"context_line":""}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_7c751192","line":94,"range":{"start_line":94,"start_character":1,"end_line":94,"end_character":10},"updated":"2019-06-26 05:41:10.000000000","message":"Will this hang forever if you hit STM32F7 erratum 2.4.1 (extra data written in the FIFO at the end of a read transfer in indirect mode when clock is AHB/2 and quad DDR is used)?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":91,"context_line":"\ttst\t\tr2, r1\t\t\t\t\t\t/* page end ? */"},{"line_number":92,"context_line":"\tbne\t\tread_loop\t\t\t\t\t/* if not, then next byte */"},{"line_number":93,"context_line":"page_end:"},{"line_number":94,"context_line":"\twait_busy\t\t\t\t\t\t\t/* wait for transfer completed */"},{"line_number":95,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":96,"context_line":"\t.pool"},{"line_number":97,"context_line":""}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_3c9a3967","line":94,"range":{"start_line":94,"start_character":1,"end_line":94,"end_character":10},"in_reply_to":"8e7fc396_7c751192","updated":"2019-07-23 20:46:58.000000000","message":"That\u0027s only in the F74/F75 errata sheet? Indeed, that could happen. Actually, the wait_busy here can be dropped altogether, as an abort is done for the next block anyway.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"contrib/loaders/flash/stmqspi/stmqspi_erase_check.S":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":55,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* start in clean state */"},{"line_number":56,"context_line":"\twait_busy"},{"line_number":57,"context_line":"\tldmia\tr2!, {r4, r5, r6}\t\t\t/* load address offset, length, initial value */"},{"line_number":58,"context_line":"\tsubs\tr2, r2, #8\t\t\t\t\t/* point to length */"},{"line_number":59,"context_line":"\tsubs\tr5, r5, #1\t\t\t\t\t/* decrement sector length for DLR */"},{"line_number":60,"context_line":"\tstr\t\tr5, [r1, #QSPI_DLR]\t\t\t/* size-1 in DLR register */"},{"line_number":61,"context_line":"\tldr\t\tr7, ccr_page_read\t\t\t/* CCR for page read */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_3c58f934","line":58,"updated":"2019-06-26 05:41:10.000000000","message":"Not necessarily a problem, just wondering: would be it less confusing to write this as an ldmia without writeback followed by an add of 4?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":55,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* start in clean state */"},{"line_number":56,"context_line":"\twait_busy"},{"line_number":57,"context_line":"\tldmia\tr2!, {r4, r5, r6}\t\t\t/* load address offset, length, initial value */"},{"line_number":58,"context_line":"\tsubs\tr2, r2, #8\t\t\t\t\t/* point to length */"},{"line_number":59,"context_line":"\tsubs\tr5, r5, #1\t\t\t\t\t/* decrement sector length for DLR */"},{"line_number":60,"context_line":"\tstr\t\tr5, [r1, #QSPI_DLR]\t\t\t/* size-1 in DLR register */"},{"line_number":61,"context_line":"\tldr\t\tr7, ccr_page_read\t\t\t/* CCR for page read */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_dc9ea559","line":58,"in_reply_to":"8e7fc396_3c58f934","updated":"2019-07-23 20:46:58.000000000","message":"Hm, I don\u0027t see any significant (dis-) advantages of either variant. Mainly for symmetry (r5 and r6 later written back with stmia), but that\u0027s a matter of taste ...","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":69,"context_line":"\torrs\tr4, r4, r7\t\t\t\t\t/* copy ones to left of read byte */"},{"line_number":70,"context_line":"\tands\tr6, r6, r4\t\t\t\t\t/* and read byte to result */"},{"line_number":71,"context_line":"\tlsls\tr4, r4, #8\t\t\t\t\t/* shift result into higher byte */"},{"line_number":72,"context_line":"\torrs\tr6, r6, r4\t\t\t\t\t/* or read byte to result */"},{"line_number":73,"context_line":"\tsubs\tr5, r5, #1\t\t\t\t\t/* decrement byte count */"},{"line_number":74,"context_line":"\tbpl\t\tread_loop\t\t\t\t\t/* again if sector not completed */"},{"line_number":75,"context_line":"\tadds\tr5, r5, #1\t\t\t\t\t/* correct count */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_1c22dd50","line":72,"updated":"2019-06-26 05:41:10.000000000","message":"The code that calls this algorithm (stmqspi_blank_check) completely ignores the upper byte of the halfword (other than a debug log). Why bother calculating it?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":69,"context_line":"\torrs\tr4, r4, r7\t\t\t\t\t/* copy ones to left of read byte */"},{"line_number":70,"context_line":"\tands\tr6, r6, r4\t\t\t\t\t/* and read byte to result */"},{"line_number":71,"context_line":"\tlsls\tr4, r4, #8\t\t\t\t\t/* shift result into higher byte */"},{"line_number":72,"context_line":"\torrs\tr6, r6, r4\t\t\t\t\t/* or read byte to result */"},{"line_number":73,"context_line":"\tsubs\tr5, r5, #1\t\t\t\t\t/* decrement byte count */"},{"line_number":74,"context_line":"\tbpl\t\tread_loop\t\t\t\t\t/* again if sector not completed */"},{"line_number":75,"context_line":"\tadds\tr5, r5, #1\t\t\t\t\t/* correct count */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_fc9b6166","line":72,"in_reply_to":"8e7fc396_1c22dd50","updated":"2019-07-23 20:46:58.000000000","message":"All SPI flash chips I know of have \u00271\u0027 as the erased state, but AFAIK there is no technical reason for that. It could be the other way round, too. Just preparation for the unexpected, no need to touch the assembly part then. \nThe speed penalty is negligible.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"contrib/loaders/flash/stmqspi/stmqspi_read.S":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":31,"context_line":" * r9 - fifo end + 1"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":" * Clobbered:"},{"line_number":34,"context_line":" * r4 - rp"},{"line_number":35,"context_line":" * r5 - address of QSPI_DR"},{"line_number":36,"context_line":" * r7 - tmp"},{"line_number":37,"context_line":" */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_dc3c65bf","line":34,"range":{"start_line":34,"start_character":8,"end_line":34,"end_character":10},"updated":"2019-06-26 05:41:10.000000000","message":"r4 is wp, not rp, isn’t it?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":31,"context_line":" * r9 - fifo end + 1"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":" * Clobbered:"},{"line_number":34,"context_line":" * r4 - rp"},{"line_number":35,"context_line":" * r5 - address of QSPI_DR"},{"line_number":36,"context_line":" * r7 - tmp"},{"line_number":37,"context_line":" */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_7c05117c","line":34,"range":{"start_line":34,"start_character":8,"end_line":34,"end_character":10},"in_reply_to":"8e7fc396_dc3c65bf","updated":"2019-07-23 20:46:58.000000000","message":"Right.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":96,"context_line":"\ttst\t\tr2, r1\t\t\t\t\t\t/* page end ? */"},{"line_number":97,"context_line":"\tbne\t\tread_loop\t\t\t\t\t/* if not, then next byte */"},{"line_number":98,"context_line":"page_end:"},{"line_number":99,"context_line":"\twait_busy\t\t\t\t\t\t\t/* wait for transfer completed */"},{"line_number":100,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"exit:"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_5c7055a3","line":99,"range":{"start_line":99,"start_character":1,"end_line":99,"end_character":10},"updated":"2019-06-26 05:41:10.000000000","message":"Will this hang forever if you hit STM32F7 erratum 2.4.1 (extra data written in the FIFO at the end of a read transfer in indirect mode when clock is AHB/2 and quad DDR is used)?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":96,"context_line":"\ttst\t\tr2, r1\t\t\t\t\t\t/* page end ? */"},{"line_number":97,"context_line":"\tbne\t\tread_loop\t\t\t\t\t/* if not, then next byte */"},{"line_number":98,"context_line":"page_end:"},{"line_number":99,"context_line":"\twait_busy\t\t\t\t\t\t\t/* wait for transfer completed */"},{"line_number":100,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"exit:"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_1cfadd73","line":99,"range":{"start_line":99,"start_character":1,"end_line":99,"end_character":10},"in_reply_to":"8e7fc396_5c7055a3","updated":"2019-07-23 20:46:58.000000000","message":"wait_busy dropped here","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":100,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"exit:"},{"line_number":103,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":104,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_9c46ed53","line":103,"range":{"start_line":103,"start_character":24,"end_line":103,"end_character":37},"updated":"2019-06-26 05:41:10.000000000","message":"We get here in two cases: if the host sets the FIFO read pointer to zero, or if we reach the end of the bytes we were asked to read. In the former case, r0 will be set to the number of bytes left unread; in the latter case, it will be set to zero (which is also the number of bytes left unread). At the top of this file, the comment describes the return value in r0 as “status”, but I don’t think that’s a good description of what’s being returned here.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":100,"context_line":"\tb\t\tstart_read\t\t\t\t\t/* then next page */"},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"exit:"},{"line_number":103,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":104,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_dcf3059b","line":103,"range":{"start_line":103,"start_character":24,"end_line":103,"end_character":37},"in_reply_to":"8e7fc396_9c46ed53","updated":"2019-07-23 20:46:58.000000000","message":"\u003d\u003d 0 -\u003e ok, all written\n!\u003d 0 -\u003e error or abort requested\n\nThe sense is inverted in contrast to the usual C rules, that\u0027s right. Will change he comment.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":103,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":104,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"},{"line_number":107,"context_line":"\tbkpt\t#0\t\t\t\t\t\t\t/* before code end for exit_point */"},{"line_number":108,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word */"},{"line_number":109,"context_line":""}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_5c285532","line":106,"range":{"start_line":106,"start_character":42,"end_line":106,"end_character":43},"updated":"2019-06-26 05:41:10.000000000","message":"s/4/12/ for this algorithm.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":103,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":104,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"},{"line_number":107,"context_line":"\tbkpt\t#0\t\t\t\t\t\t\t/* before code end for exit_point */"},{"line_number":108,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word */"},{"line_number":109,"context_line":""}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_7f9663f5","line":106,"range":{"start_line":106,"start_character":42,"end_line":106,"end_character":43},"in_reply_to":"8e7fc396_3cff9964","updated":"2019-07-29 19:35:48.000000000","message":"I’m afraid I can’t remember exactly what we were talking about any more! It seems to me that: (1) the BKPT instruction itself is half a word or 2 bytes long; (2) the alignment of said instruction, and of the thing following it, is one word or 4 bytes due to .align; and (3) the size of the control structures following the BKPT instruction is 12 words or 48 bytes (with layout defined by ccr_buffer in qspi_read_write_block).\n\nSo what was this discussion about? And what was “4 words” supposed to refer to? And your suggestion of 16?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":103,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":104,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"},{"line_number":107,"context_line":"\tbkpt\t#0\t\t\t\t\t\t\t/* before code end for exit_point */"},{"line_number":108,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word */"},{"line_number":109,"context_line":""}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_3cff9964","line":106,"range":{"start_line":106,"start_character":42,"end_line":106,"end_character":43},"in_reply_to":"8e7fc396_5c285532","updated":"2019-07-23 20:46:58.000000000","message":"Hm, this should resemble the longest/most complicated as close as possible. Otherwise s/4/16/. And the \u0027read\u0027 block doesn\u0027t fit at all.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"contrib/loaders/flash/stmqspi/stmqspi_write.S":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":145,"context_line":"\tmovs\tr0, #0\t\t\t\t\t\t/* return 0xFFFFFFFF */"},{"line_number":146,"context_line":"\tsubs\tr0, r0, #2\t\t\t\t\t/* for error */"},{"line_number":147,"context_line":"exit:"},{"line_number":148,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":149,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_1c6addb1","line":148,"range":{"start_line":148,"start_character":24,"end_line":148,"end_character":37},"updated":"2019-06-26 05:41:10.000000000","message":"We get here in two cases: if the host sets the FIFO read pointer to zero, or if we reach the end of the bytes we were asked to read. In the former case, r0 will be set to the number of bytes left unwritten (or −1 if a write enable fails); in the latter case, it will be set to zero (which is also the number of bytes left unwritten). At the top of this file, the comment describes the return value in r0 as “status”, but I don’t think that’s a good description of what’s being returned here.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":145,"context_line":"\tmovs\tr0, #0\t\t\t\t\t\t/* return 0xFFFFFFFF */"},{"line_number":146,"context_line":"\tsubs\tr0, r0, #2\t\t\t\t\t/* for error */"},{"line_number":147,"context_line":"exit:"},{"line_number":148,"context_line":"\tadds\tr0, r0, #1\t\t\t\t\t/* correct count */"},{"line_number":149,"context_line":"\tqspi_abort\t\t\t\t\t\t\t/* to idle state */"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\t.align\t2\t\t\t\t\t\t\t/* align to word, bkpt is 4 words */"}],"source_content_type":"text/x-asm","patch_set":6,"id":"8e7fc396_9ced8db7","line":148,"range":{"start_line":148,"start_character":24,"end_line":148,"end_character":37},"in_reply_to":"8e7fc396_1c6addb1","updated":"2019-07-23 20:46:58.000000000","message":"As in *_read.S","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"contrib/stm32_gpio_conf.pl":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9db8a79b52b38c5e6ca4ae4f4bfdaba913803bb3","unresolved":false,"context_lines":[{"line_number":1,"context_line":"#!/usr/bin/perl"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"use strict;"},{"line_number":4,"context_line":"use Getopt::Std;"},{"line_number":5,"context_line":""}],"source_content_type":"text/x-perl","patch_set":3,"id":"2e489777_773318c1","line":2,"updated":"2018-01-16 15:35:11.000000000","message":"What does it generate? A comment would be nice...","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6e4bd383acec2d38cc13643adf2f8fcac817911e","unresolved":false,"context_lines":[{"line_number":1,"context_line":"#!/usr/bin/perl"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"use strict;"},{"line_number":4,"context_line":"use Getopt::Std;"},{"line_number":5,"context_line":""}],"source_content_type":"text/x-perl","patch_set":3,"id":"0e83d3c5_e21bc61f","line":2,"in_reply_to":"2e489777_773318c1","updated":"2018-01-20 18:36:26.000000000","message":"Ok, I\u0027ll add a description. Unfortunately this script is of limited use, it\u0027s intended to extract the GPIO setup e. g. from CubeMX generated files, but this output is not very consistent and requires some manual rework.","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"}],"doc/openocd.texi":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":5040,"context_line":""},{"line_number":5041,"context_line":"The setup command only requires the @var{base} parameter and the extra"},{"line_number":5042,"context_line":"parameter @var{io_base} in order to identify the memory bank. All other"},{"line_number":5043,"context_line":"parameters are ignored."},{"line_number":5044,"context_line":""},{"line_number":5045,"context_line":"The controllers must be initialized after each reset, the setup is quite board"},{"line_number":5046,"context_line":"specific (that\u0027s why booting from this memory is not possible) and the flash"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_b72f3885","line":5043,"updated":"2018-10-14 22:56:00.000000000","message":"How do I specify which port the Flash is connected to? This paragraph claims that between the base and io_base parameters I can do this, but it’s not clear how. According to the STM32F74/75 documentation, 0x90000000 is the base address for memory mapped mode regardless of which port is in use (QUADSPI_CR.FSEL chooses between the two ports, or QUADSPI_CR.DFM to use both interleaved), and 0xA0001000 is the base address of the control registers, again regardless of which port is being used. So which bit of configuration tells the driver which port to use?\n\nActually, in the example config files, it appears that FSEL is set by an mww operation in the reset-init handler, and the flash bank command has no impact on this at all. Which seems like a problem: what if I want to attach two chips, but not in dual-Flash mode because I want to use them for different purposes? Ideally those two chips would show up as two separate Flash banks (it’s absolutely true that *in hardware* only one can be enabled for memory mapping at a time, but the *driver* ought IMO to expose both banks and then operate the control registers appropriately to switch between them as the user types commands).","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":5040,"context_line":""},{"line_number":5041,"context_line":"The setup command only requires the @var{base} parameter and the extra"},{"line_number":5042,"context_line":"parameter @var{io_base} in order to identify the memory bank. All other"},{"line_number":5043,"context_line":"parameters are ignored."},{"line_number":5044,"context_line":""},{"line_number":5045,"context_line":"The controllers must be initialized after each reset, the setup is quite board"},{"line_number":5046,"context_line":"specific (that\u0027s why booting from this memory is not possible) and the flash"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_b232e604","line":5043,"in_reply_to":"6e936f18_b72f3885","updated":"2018-11-02 19:20:01.000000000","message":"Yes, indeed, that could be described in more detail.\nFor two (maybe even different) chips: Manually set FSEL/DFM appropiately and then issue a \u0027flash probe ...\u0027 The current setting is then used afterwards.\n\nTo expose two banks is not easily possible, as the bank base address is fixed. Of course, an option would be to use a \u0027fake\u0027 base address for the second bank, but this will break e. g. the verify_image command as it uses plain memory reads.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":5044,"context_line":""},{"line_number":5045,"context_line":"The controllers must be initialized after each reset, the setup is quite board"},{"line_number":5046,"context_line":"specific (that\u0027s why booting from this memory is not possible) and the flash"},{"line_number":5047,"context_line":"driver infers all parameters from current controller register values."},{"line_number":5048,"context_line":""},{"line_number":5049,"context_line":"Normal OpenOCD commands like @command{mdw} can be used to display"},{"line_number":5050,"context_line":"the flash content, but only after proper controller initialization."}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_d72c4492","line":5047,"updated":"2018-10-14 22:56:00.000000000","message":"I have a concern about this documentation. “The controllers must be initialized after each reset” is a bit unclear. A successful read from an SPI Flash using memory mapped mode involves these steps:\n1. Enable the clock to the GPIO and QUADSPI blocks in the RCC (and maybe reset them at the same time, if you see fit).\n2. Set all the GPIO_AF*, GPIO_OSPEEDR, and GPIO_MODER bits needed for the pins your board uses.\n3. Set the QUADSPI registers to enable memory mapped mode, with appropriate choice of Flash size, port number, and baud rate.\n4. Actually read the memory.\n\nSo which steps are done by the QuadSPI driver, and which steps is my board config expected to do directly with mww commands in the reset-init handler? The documentation doesn’t make this entirely clear.\n\nFor that matter, from the example board configs, it looks like steps 1 through 3 are all done by the board config. If that’s the case, then I think the documentation needs to really, *really* clearly explain in exactly what state the QUADSPI module has to be placed in order for the driver to work (i.e. not just “must be initialized”, but something like “the PRESCALER, FSEL, DFM, SSHIFT, FSIZE, CSHT, and CKMODE bits must be set properly for your Flash, the foo and bar bits must be 1, the baz and quux bits must be 0, …”.\n\nFor example, in stmqspi.c you have the comment “The command \"reset init\" has to initialize QSPI controller and put it in memory mapped mode”, but IMO that would be much more appropriate here, as that’s something that the user needs to know. And IMO even more detail.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"37e8dc0a8b0b919753c07ae63a2d1ec640f0bf6d","unresolved":false,"context_lines":[{"line_number":5044,"context_line":""},{"line_number":5045,"context_line":"The controllers must be initialized after each reset, the setup is quite board"},{"line_number":5046,"context_line":"specific (that\u0027s why booting from this memory is not possible) and the flash"},{"line_number":5047,"context_line":"driver infers all parameters from current controller register values."},{"line_number":5048,"context_line":""},{"line_number":5049,"context_line":"Normal OpenOCD commands like @command{mdw} can be used to display"},{"line_number":5050,"context_line":"the flash content, but only after proper controller initialization."}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_86644b47","line":5047,"in_reply_to":"6e936f18_721c5e7d","updated":"2018-11-14 20:56:01.000000000","message":"\"initalize and set to memory mapped mode so that the flash is readable by CPU / debug interface\" sounds fine to me. Even that is a lot more detail than what’s written there right now!","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":5044,"context_line":""},{"line_number":5045,"context_line":"The controllers must be initialized after each reset, the setup is quite board"},{"line_number":5046,"context_line":"specific (that\u0027s why booting from this memory is not possible) and the flash"},{"line_number":5047,"context_line":"driver infers all parameters from current controller register values."},{"line_number":5048,"context_line":""},{"line_number":5049,"context_line":"Normal OpenOCD commands like @command{mdw} can be used to display"},{"line_number":5050,"context_line":"the flash content, but only after proper controller initialization."}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_721c5e7d","line":5047,"in_reply_to":"6e936f18_d72c4492","updated":"2018-11-02 19:20:01.000000000","message":"I think just saying \"initalize and set to memory mapped mode so that the flash is readable by CPU / debug interface\" should be sufficient. Naturally the setup is somewhat complicated, and the user has to verify each and every register against the RM anyway.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":5082,"context_line":"@example"},{"line_number":5083,"context_line":"stmqspi spicmd bank_id 1 0x05 0x00 0x00 0x00 0x00"},{"line_number":5084,"context_line":"@end example"},{"line_number":5085,"context_line":"should return the status register contents."},{"line_number":5086,"context_line":""},{"line_number":5087,"context_line":"If @var{resp_num} is not zero, cmd and at most four following data bytes are"},{"line_number":5088,"context_line":"sent, in dual mode *simultaneously* to both chips. Then @var{resp_num} bytes"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_d7b9a42a","line":5085,"updated":"2018-10-14 22:56:00.000000000","message":"This @example sets resp_num to 1, but it is under the paragraph about the case where resp_num is 0. Perhaps it should be moved down, to under the paragraph about what happens when resp_num is nonzero?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":5082,"context_line":"@example"},{"line_number":5083,"context_line":"stmqspi spicmd bank_id 1 0x05 0x00 0x00 0x00 0x00"},{"line_number":5084,"context_line":"@end example"},{"line_number":5085,"context_line":"should return the status register contents."},{"line_number":5086,"context_line":""},{"line_number":5087,"context_line":"If @var{resp_num} is not zero, cmd and at most four following data bytes are"},{"line_number":5088,"context_line":"sent, in dual mode *simultaneously* to both chips. Then @var{resp_num} bytes"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"6e936f18_9221eaae","line":5085,"in_reply_to":"6e936f18_d7b9a42a","updated":"2018-11-02 19:20:01.000000000","message":"Right, although it was primarily intended as a comment regarding dummy address in 8-line mode only.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5090,"context_line":"Verify the image @file{filename} to the current target\u0027s flash bank(s)."},{"line_number":5091,"context_line":"Parameters follow the description of \u0027flash write_image\u0027."},{"line_number":5092,"context_line":"In contrast to the \u0027verify_image\u0027 command, the flash driver\u0027s internal"},{"line_number":5093,"context_line":"verify methods are used (if available) but not the usual target\u0027s read"},{"line_number":5094,"context_line":"memory methods. This is necessary for flash banks not readable by"},{"line_number":5095,"context_line":"ordinary memory reads."},{"line_number":5096,"context_line":"This command gives only an overall good/bad result for each bank, not"},{"line_number":5097,"context_line":"addresses of individual failed bytes as it\u0027s intended only as quick"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_3c6f99c2","line":5094,"range":{"start_line":5093,"start_character":39,"end_line":5094,"end_character":14},"updated":"2019-06-26 05:41:10.000000000","message":"To me, “but not the read memory methods” means that the read memory methods will *never* be used. Actually, they *will* be used if a verify algorithm is not available. I would maybe say something like “instead of the usual target\u0027s read memory methods”, or even just leave these words out.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5090,"context_line":"Verify the image @file{filename} to the current target\u0027s flash bank(s)."},{"line_number":5091,"context_line":"Parameters follow the description of \u0027flash write_image\u0027."},{"line_number":5092,"context_line":"In contrast to the \u0027verify_image\u0027 command, the flash driver\u0027s internal"},{"line_number":5093,"context_line":"verify methods are used (if available) but not the usual target\u0027s read"},{"line_number":5094,"context_line":"memory methods. This is necessary for flash banks not readable by"},{"line_number":5095,"context_line":"ordinary memory reads."},{"line_number":5096,"context_line":"This command gives only an overall good/bad result for each bank, not"},{"line_number":5097,"context_line":"addresses of individual failed bytes as it\u0027s intended only as quick"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_9ca82d76","line":5094,"range":{"start_line":5093,"start_character":39,"end_line":5094,"end_character":14},"in_reply_to":"8e7fc396_3c6f99c2","updated":"2019-07-23 20:46:58.000000000","message":"The \u0027(if available)\u0027 should have made it clear, but I\u0027ll rephrase that.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5364,"context_line":"Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface\u0027\u0027"},{"line_number":5365,"context_line":"(e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface\u0027\u0027 (e. g. STM32L4+)"},{"line_number":5366,"context_line":"controller able to drive one or even two (dual mode) external SPI flash devices."},{"line_number":5367,"context_line":"The OctoSPI is a superset of QuadSPI, it\u0027s presence is detected automatically."},{"line_number":5368,"context_line":"Currently only the regular command mode is supported, whereas the HyperFlash"},{"line_number":5369,"context_line":"mode is not."},{"line_number":5370,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_dc6305d9","line":5367,"range":{"start_line":5367,"start_character":38,"end_line":5367,"end_character":42},"updated":"2019-06-26 05:41:10.000000000","message":"s/it\u0027s/its/","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5364,"context_line":"Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface\u0027\u0027"},{"line_number":5365,"context_line":"(e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface\u0027\u0027 (e. g. STM32L4+)"},{"line_number":5366,"context_line":"controller able to drive one or even two (dual mode) external SPI flash devices."},{"line_number":5367,"context_line":"The OctoSPI is a superset of QuadSPI, it\u0027s presence is detected automatically."},{"line_number":5368,"context_line":"Currently only the regular command mode is supported, whereas the HyperFlash"},{"line_number":5369,"context_line":"mode is not."},{"line_number":5370,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_bca5e99c","line":5367,"range":{"start_line":5367,"start_character":38,"end_line":5367,"end_character":42},"in_reply_to":"8e7fc396_dc6305d9","updated":"2019-07-23 20:46:58.000000000","message":"Right ;-)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5370,"context_line":""},{"line_number":5371,"context_line":"QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address"},{"line_number":5372,"context_line":"space; in case of dual mode both devices must be of the same type and are"},{"line_number":5373,"context_line":"mapped in the same memory bank (even and odd adresses interleaved)."},{"line_number":5374,"context_line":"CPU can directly read data, execute code (but not boot) from QuadSPI bank."},{"line_number":5375,"context_line":""},{"line_number":5376,"context_line":"The \u0027flash bank\u0027 command only requires the @var{base} parameter and the extra"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_fc6041ce","line":5373,"range":{"start_line":5373,"start_character":45,"end_line":5373,"end_character":53},"updated":"2019-06-26 05:41:10.000000000","message":"s/adresses/addresses/","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5370,"context_line":""},{"line_number":5371,"context_line":"QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address"},{"line_number":5372,"context_line":"space; in case of dual mode both devices must be of the same type and are"},{"line_number":5373,"context_line":"mapped in the same memory bank (even and odd adresses interleaved)."},{"line_number":5374,"context_line":"CPU can directly read data, execute code (but not boot) from QuadSPI bank."},{"line_number":5375,"context_line":""},{"line_number":5376,"context_line":"The \u0027flash bank\u0027 command only requires the @var{base} parameter and the extra"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_5cb295e5","line":5373,"range":{"start_line":5373,"start_character":45,"end_line":5373,"end_character":53},"in_reply_to":"8e7fc396_fc6041ce","updated":"2019-07-23 20:46:58.000000000","message":"Oh yes ...","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5412,"context_line":"@end example"},{"line_number":5413,"context_line":""},{"line_number":5414,"context_line":"There are three specific commands"},{"line_number":5415,"context_line":"@deffn Command {stmqspi mass_erase} num"},{"line_number":5416,"context_line":"Clears sector protections and performs a mass erase. Works only if there is no"},{"line_number":5417,"context_line":"chip specific write protection engaged."},{"line_number":5418,"context_line":"@end deffn"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_9cbcad1c","line":5415,"range":{"start_line":5415,"start_character":36,"end_line":5415,"end_character":39},"updated":"2019-06-26 05:41:10.000000000","message":"What is num? Is it a bank number? All the other commands call it bank_id instead.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5412,"context_line":"@end example"},{"line_number":5413,"context_line":""},{"line_number":5414,"context_line":"There are three specific commands"},{"line_number":5415,"context_line":"@deffn Command {stmqspi mass_erase} num"},{"line_number":5416,"context_line":"Clears sector protections and performs a mass erase. Works only if there is no"},{"line_number":5417,"context_line":"chip specific write protection engaged."},{"line_number":5418,"context_line":"@end deffn"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_7cb751d4","line":5415,"range":{"start_line":5415,"start_character":36,"end_line":5415,"end_character":39},"in_reply_to":"8e7fc396_9cbcad1c","updated":"2019-07-23 20:46:58.000000000","message":"Good point.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5424,"context_line":"@var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}"},{"line_number":5425,"context_line":"and @var{sector_erase_cmd} are optional."},{"line_number":5426,"context_line":""},{"line_number":5427,"context_line":"This command is required if chip id is not hardcoded yet and e. g. for EEPROMs or FRAMs"},{"line_number":5428,"context_line":"which don\u0027t support an id command."},{"line_number":5429,"context_line":""},{"line_number":5430,"context_line":"In dual mode parameters of both chips are set identically. The parameters refer to"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_dcb22548","line":5427,"range":{"start_line":5427,"start_character":61,"end_line":5427,"end_character":65},"updated":"2019-06-26 05:41:10.000000000","message":"extraneous space","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5424,"context_line":"@var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}"},{"line_number":5425,"context_line":"and @var{sector_erase_cmd} are optional."},{"line_number":5426,"context_line":""},{"line_number":5427,"context_line":"This command is required if chip id is not hardcoded yet and e. g. for EEPROMs or FRAMs"},{"line_number":5428,"context_line":"which don\u0027t support an id command."},{"line_number":5429,"context_line":""},{"line_number":5430,"context_line":"In dual mode parameters of both chips are set identically. The parameters refer to"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_1cac1d84","line":5427,"range":{"start_line":5427,"start_character":61,"end_line":5427,"end_character":65},"in_reply_to":"8e7fc396_dcb22548","updated":"2019-07-23 20:46:58.000000000","message":";-)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":5433,"context_line":""},{"line_number":5434,"context_line":"@deffn Command {stmqspi cmd} bank_id resp_num cmd_byte ..."},{"line_number":5435,"context_line":"If @var{resp_num} is zero, sends command @var{cmd_byte} and following data"},{"line_number":5436,"context_line":"bytes. In dual mode command byte is sent to *both* chips but data bytes are sent"},{"line_number":5437,"context_line":"*alternatingly* to chip 1 and 2, first to flash 1, second to flash 2, etc.,"},{"line_number":5438,"context_line":"i.e. the total number of bytes must be odd."},{"line_number":5439,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_bcb9692b","line":5436,"range":{"start_line":5436,"start_character":44,"end_line":5436,"end_character":50},"updated":"2019-06-26 05:41:10.000000000","message":"I think you want @emph for emphasizing italics, not asterisks. (2 more below)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":5433,"context_line":""},{"line_number":5434,"context_line":"@deffn Command {stmqspi cmd} bank_id resp_num cmd_byte ..."},{"line_number":5435,"context_line":"If @var{resp_num} is zero, sends command @var{cmd_byte} and following data"},{"line_number":5436,"context_line":"bytes. In dual mode command byte is sent to *both* chips but data bytes are sent"},{"line_number":5437,"context_line":"*alternatingly* to chip 1 and 2, first to flash 1, second to flash 2, etc.,"},{"line_number":5438,"context_line":"i.e. the total number of bytes must be odd."},{"line_number":5439,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"8e7fc396_3cb1d9dc","line":5436,"range":{"start_line":5436,"start_character":44,"end_line":5436,"end_character":50},"in_reply_to":"8e7fc396_bcb9692b","updated":"2019-07-23 20:46:58.000000000","message":"Well, yes and no, in the resulting document italics don\u0027t look that impressive. Italics with underlining would be nice.\nBut you\u0027re right, I should follow the conventions.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"src/flash/nor/core.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"54721541156e680eb302c92dd2d81df79fefb5d3","unresolved":false,"context_lines":[{"line_number":750,"context_line":"\tif (written)"},{"line_number":751,"context_line":"\t\t*written \u003d 0;"},{"line_number":752,"context_line":""},{"line_number":753,"context_line":"\tif (erase \u0026\u0026 write) {"},{"line_number":754,"context_line":"\t\t/* assume all sectors need erasing - stops any problems"},{"line_number":755,"context_line":"\t\t * when flash_write is called multiple times */"},{"line_number":756,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_13488e8b","line":753,"range":{"start_line":753,"start_character":10,"end_line":753,"end_character":19},"updated":"2020-10-30 21:36:05.000000000","message":"This is kind of contra-intuitive. If somebody wants to erase and verify or erase only let him to do so.","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"abfd260a5bcb50ec68aa07537a9971dd14711602","unresolved":false,"context_lines":[{"line_number":750,"context_line":"\tif (written)"},{"line_number":751,"context_line":"\t\t*written \u003d 0;"},{"line_number":752,"context_line":""},{"line_number":753,"context_line":"\tif (erase \u0026\u0026 write) {"},{"line_number":754,"context_line":"\t\t/* assume all sectors need erasing - stops any problems"},{"line_number":755,"context_line":"\t\t * when flash_write is called multiple times */"},{"line_number":756,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_d6b2f447","line":753,"range":{"start_line":753,"start_character":10,"end_line":753,"end_character":19},"in_reply_to":"ceda9b01_13488e8b","updated":"2020-11-01 16:16:13.000000000","message":"The name \u0027write\u0027 is certainly misleading, as when \u0027false\u0027 it is only intended to disallow any flash modification. \u0027ro\u0027 or \u0027read-only\u0027 might be better, but then it\u0027s inverted. Something like \u0027enable\u0027 wouldn\u0027t be very intuitive either. But for the current usage of this function, the \u0027\u0026\u0026 write\u0027 can indeed be dropped altogether.","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"54721541156e680eb302c92dd2d81df79fefb5d3","unresolved":false,"context_lines":[{"line_number":958,"context_line":""},{"line_number":959,"context_line":"\t\tretval \u003d ERROR_OK;"},{"line_number":960,"context_line":""},{"line_number":961,"context_line":"\t\tif (unlock \u0026\u0026 write)"},{"line_number":962,"context_line":"\t\t\tretval \u003d flash_unlock_address_range(target, run_address, run_size);"},{"line_number":963,"context_line":"\t\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":964,"context_line":"\t\t\tif (erase \u0026\u0026 write) {"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_334d929c","line":961,"range":{"start_line":961,"start_character":12,"end_line":961,"end_character":21},"updated":"2020-10-30 21:36:05.000000000","message":"as above","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"abfd260a5bcb50ec68aa07537a9971dd14711602","unresolved":false,"context_lines":[{"line_number":958,"context_line":""},{"line_number":959,"context_line":"\t\tretval \u003d ERROR_OK;"},{"line_number":960,"context_line":""},{"line_number":961,"context_line":"\t\tif (unlock \u0026\u0026 write)"},{"line_number":962,"context_line":"\t\t\tretval \u003d flash_unlock_address_range(target, run_address, run_size);"},{"line_number":963,"context_line":"\t\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":964,"context_line":"\t\t\tif (erase \u0026\u0026 write) {"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_f6aff8dc","line":961,"range":{"start_line":961,"start_character":12,"end_line":961,"end_character":21},"in_reply_to":"ceda9b01_334d929c","updated":"2020-11-01 16:16:13.000000000","message":"Done","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"54721541156e680eb302c92dd2d81df79fefb5d3","unresolved":false,"context_lines":[{"line_number":961,"context_line":"\t\tif (unlock \u0026\u0026 write)"},{"line_number":962,"context_line":"\t\t\tretval \u003d flash_unlock_address_range(target, run_address, run_size);"},{"line_number":963,"context_line":"\t\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":964,"context_line":"\t\t\tif (erase \u0026\u0026 write) {"},{"line_number":965,"context_line":"\t\t\t\t/* calculate and erase sectors */"},{"line_number":966,"context_line":"\t\t\t\tretval \u003d flash_erase_address_range(target,"},{"line_number":967,"context_line":"\t\t\t\t\t\ttrue, run_address, run_size);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_d361a602","line":964,"range":{"start_line":964,"start_character":12,"end_line":964,"end_character":21},"updated":"2020-10-30 21:36:05.000000000","message":"as above","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"abfd260a5bcb50ec68aa07537a9971dd14711602","unresolved":false,"context_lines":[{"line_number":961,"context_line":"\t\tif (unlock \u0026\u0026 write)"},{"line_number":962,"context_line":"\t\t\tretval \u003d flash_unlock_address_range(target, run_address, run_size);"},{"line_number":963,"context_line":"\t\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":964,"context_line":"\t\t\tif (erase \u0026\u0026 write) {"},{"line_number":965,"context_line":"\t\t\t\t/* calculate and erase sectors */"},{"line_number":966,"context_line":"\t\t\t\tretval \u003d flash_erase_address_range(target,"},{"line_number":967,"context_line":"\t\t\t\t\t\ttrue, run_address, run_size);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"ceda9b01_96bc6c1c","line":964,"range":{"start_line":964,"start_character":12,"end_line":964,"end_character":21},"in_reply_to":"ceda9b01_d361a602","updated":"2020-11-01 16:16:13.000000000","message":"Done","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"}],"src/flash/nor/core.h":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":221,"context_line":" * @returns ERROR_OK if successful; otherwise, an error code."},{"line_number":222,"context_line":" */"},{"line_number":223,"context_line":"int default_flash_verify(struct flash_bank *bank,"},{"line_number":224,"context_line":"\t\tconst uint8_t *buffer, uint32_t offset, uint32_t count);"},{"line_number":225,"context_line":""},{"line_number":226,"context_line":"/**"},{"line_number":227,"context_line":" * Provides default erased-bank check handling. Checks to see if"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1c809d4a","line":224,"updated":"2019-06-26 05:41:10.000000000","message":"The comments for default_flash_read and default_flash_verify got mixed up. They both say “default read implementation” (one of them should say verify), and their @params are all backwards.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":221,"context_line":" * @returns ERROR_OK if successful; otherwise, an error code."},{"line_number":222,"context_line":" */"},{"line_number":223,"context_line":"int default_flash_verify(struct flash_bank *bank,"},{"line_number":224,"context_line":"\t\tconst uint8_t *buffer, uint32_t offset, uint32_t count);"},{"line_number":225,"context_line":""},{"line_number":226,"context_line":"/**"},{"line_number":227,"context_line":" * Provides default erased-bank check handling. Checks to see if"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fcc28138","line":224,"in_reply_to":"8e7fc396_1c809d4a","updated":"2019-07-23 20:46:58.000000000","message":"Fixed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"src/flash/nor/sfdp.c":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":27,"context_line":"#define SFDP_BASIC_FLASH\t0xFF00"},{"line_number":28,"context_line":"#define SFDP_4BYTE_ADDR\t\t0xFF84"},{"line_number":29,"context_line":""},{"line_number":30,"context_line":"const char *sfdp_name \u003d \"sfdp\";"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"struct sfdp_hdr {"},{"line_number":33,"context_line":"\tuint32_t\t\t\tsignature;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dc99c5c9","line":30,"updated":"2019-06-26 05:41:10.000000000","message":"This is not accessed outside this file and could therefore by static.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":27,"context_line":"#define SFDP_BASIC_FLASH\t0xFF00"},{"line_number":28,"context_line":"#define SFDP_4BYTE_ADDR\t\t0xFF84"},{"line_number":29,"context_line":""},{"line_number":30,"context_line":"const char *sfdp_name \u003d \"sfdp\";"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"struct sfdp_hdr {"},{"line_number":33,"context_line":"\tuint32_t\t\t\tsignature;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3ce8f9ae","line":30,"in_reply_to":"8e7fc396_dc99c5c9","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":83,"context_line":"\tmemset(\u0026header, 0, sizeof(header));"},{"line_number":84,"context_line":"\tretval \u003d read_sfdp_block(bank, 0x0, sizeof(header) \u003e\u003e 2, (uint32_t *) \u0026header);"},{"line_number":85,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":86,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":87,"context_line":"\tLOG_DEBUG(\"header 0x%08\" PRIx32 \" 0x%08\" PRIx32, header.signature, header.revision);"},{"line_number":88,"context_line":"\tif (header.signature !\u003d SFDP_MAGIC) {"},{"line_number":89,"context_line":"\t\tLOG_INFO(\"no SDFP found\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fc960197","line":86,"updated":"2019-06-26 05:41:10.000000000","message":"Should we be squashing this error? Why not return retval and let the caller see the exact error cause?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":83,"context_line":"\tmemset(\u0026header, 0, sizeof(header));"},{"line_number":84,"context_line":"\tretval \u003d read_sfdp_block(bank, 0x0, sizeof(header) \u003e\u003e 2, (uint32_t *) \u0026header);"},{"line_number":85,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":86,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":87,"context_line":"\tLOG_DEBUG(\"header 0x%08\" PRIx32 \" 0x%08\" PRIx32, header.signature, header.revision);"},{"line_number":88,"context_line":"\tif (header.signature !\u003d SFDP_MAGIC) {"},{"line_number":89,"context_line":"\t\tLOG_INFO(\"no SDFP found\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bceac99a","line":86,"in_reply_to":"8e7fc396_fc960197","updated":"2019-07-23 20:46:58.000000000","message":"Good point.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":87,"context_line":"\tLOG_DEBUG(\"header 0x%08\" PRIx32 \" 0x%08\" PRIx32, header.signature, header.revision);"},{"line_number":88,"context_line":"\tif (header.signature !\u003d SFDP_MAGIC) {"},{"line_number":89,"context_line":"\t\tLOG_INFO(\"no SDFP found\");"},{"line_number":90,"context_line":"\t\treturn ERROR_TARGET_NOT_EXAMINED;"},{"line_number":91,"context_line":"\t}"},{"line_number":92,"context_line":"\tif (((header.revision \u003e\u003e 24) \u0026 0xFF) !\u003d SFDP_ACCESS_PROT) {"},{"line_number":93,"context_line":"\t\tLOG_ERROR(\"access protocol 0x%02\" PRIx8 \" not implemented\","}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c934da6","line":90,"updated":"2019-06-26 05:41:10.000000000","message":"(here and three more places below) I’m not sure ERROR_TARGET_NOT_EXAMINED is the best choice. This has nothing to do with targets, which probably *have* been examined by now. Maybe ERROR_FLASH_BANK_NOT_PROBED, or even just ERROR_FAIL?\n\nIf this change is made, stmqspi.c will also need updating accordingly because it checks for the specific error code.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":87,"context_line":"\tLOG_DEBUG(\"header 0x%08\" PRIx32 \" 0x%08\" PRIx32, header.signature, header.revision);"},{"line_number":88,"context_line":"\tif (header.signature !\u003d SFDP_MAGIC) {"},{"line_number":89,"context_line":"\t\tLOG_INFO(\"no SDFP found\");"},{"line_number":90,"context_line":"\t\treturn ERROR_TARGET_NOT_EXAMINED;"},{"line_number":91,"context_line":"\t}"},{"line_number":92,"context_line":"\tif (((header.revision \u003e\u003e 24) \u0026 0xFF) !\u003d SFDP_ACCESS_PROT) {"},{"line_number":93,"context_line":"\t\tLOG_ERROR(\"access protocol 0x%02\" PRIx8 \" not implemented\","}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5c2ff5f3","line":90,"in_reply_to":"8e7fc396_9c934da6","updated":"2019-07-23 20:46:58.000000000","message":"Well, I\u0027m not particulary happy with this choice either. If you consider the controller and the external flash as a single functional unit, then not beeing able to get the flash parameters means the target\u0027s properties aren\u0027t known (completely), so the target hasn\u0027t been (successfully) identified. ERROR_FLASH_BANK_NOT_PROBED doesn\u0027t fit nicely as the flash\u0027s id had already been successfully retrieved, but only the interpretation is missing (SFDP is only the fallback). And that\u0027s not a real error but only missing functionality. I don\u0027t see any really appropriate error code around, but I can live with ERROR_FLASH_BANK_NOT_PROBED, too.\nReturning ERROR_FAIL would discard useful information. \nWill change it here and in stmqspi.c accordingly.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":119,"context_line":""},{"line_number":120,"context_line":"\t\t/* retrieve parameter table */"},{"line_number":121,"context_line":"\t\tif (ptable)"},{"line_number":122,"context_line":"\t\t\tfree(ptable);"},{"line_number":123,"context_line":"\t\tptable \u003d malloc(words \u003c\u003c 2);"},{"line_number":124,"context_line":"\t\tif (ptable \u003d\u003d NULL) {"},{"line_number":125,"context_line":"\t\t\tLOG_ERROR(\"not enough memory\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bc908999","line":122,"updated":"2019-06-26 05:41:10.000000000","message":"I don’t think this can ever happen, since you free(ptable) at the end of each loop iteration.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":119,"context_line":""},{"line_number":120,"context_line":"\t\t/* retrieve parameter table */"},{"line_number":121,"context_line":"\t\tif (ptable)"},{"line_number":122,"context_line":"\t\t\tfree(ptable);"},{"line_number":123,"context_line":"\t\tptable \u003d malloc(words \u003c\u003c 2);"},{"line_number":124,"context_line":"\t\tif (ptable \u003d\u003d NULL) {"},{"line_number":125,"context_line":"\t\t\tLOG_ERROR(\"not enough memory\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fc260111","line":122,"in_reply_to":"8e7fc396_bc908999","updated":"2019-07-23 20:46:58.000000000","message":"Right, even on error exit it\u0027s freed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\t\t\tif (dev-\u003esize_in_bytes \u003e (1UL \u003c\u003c 24)) {"},{"line_number":202,"context_line":"\t\t\t\tif (((table-\u003efast_addr \u003e\u003e 17) \u0026 0x3) \u003d\u003d 0x0)"},{"line_number":203,"context_line":"\t\t\t\t\tLOG_ERROR(\"device needs paging - not implemented\");"},{"line_number":204,"context_line":""},{"line_number":205,"context_line":"\t\t\t\t/* 4-byte addresses needed if more than 16 MBytes */"},{"line_number":206,"context_line":"\t\t\t\tif (((offsetof(struct sfdp_basic_flash_param, addr_reset) \u003e\u003e 2) \u003c words) \u0026\u0026"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1cf73df4","line":203,"updated":"2019-06-26 05:41:10.000000000","message":"Should this result in an error return rather than just logging and continuing execution normally?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\t\t\tif (dev-\u003esize_in_bytes \u003e (1UL \u003c\u003c 24)) {"},{"line_number":202,"context_line":"\t\t\t\tif (((table-\u003efast_addr \u003e\u003e 17) \u0026 0x3) \u003d\u003d 0x0)"},{"line_number":203,"context_line":"\t\t\t\t\tLOG_ERROR(\"device needs paging - not implemented\");"},{"line_number":204,"context_line":""},{"line_number":205,"context_line":"\t\t\t\t/* 4-byte addresses needed if more than 16 MBytes */"},{"line_number":206,"context_line":"\t\t\t\tif (((offsetof(struct sfdp_basic_flash_param, addr_reset) \u003e\u003e 2) \u003c words) \u0026\u0026"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c234d00","line":203,"in_reply_to":"8e7fc396_1cf73df4","updated":"2019-07-23 20:46:58.000000000","message":"In this case it\u0027s still possible to access the bottom 16 MByte (and usually any other 16 MByte segment). Most (all?) devices beyond 16 MBytes have an extended address register holding an extra address byte which is cleared on power-up and not affected by a continuous read crossing segment border. Even if this is not described in SFPD data. Setting the extended address register must then performed manually by special SPI command. Cumbersome, but possible. So, a warning only seems appropriate.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":65,"context_line":"struct sfdp_4byte_addr_param {"},{"line_number":66,"context_line":"\tuint32_t\t\t\tflags;\t\t\t/* 01: various flags */"},{"line_number":67,"context_line":"\tuint32_t\t\t\terase_t1234;\t/* 02: erase commands */"},{"line_number":68,"context_line":"};"},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"/* Try to get parameters from flash via SFDP */"},{"line_number":71,"context_line":"int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_9fdc964d","line":68,"updated":"2020-03-12 12:10:51.000000000","message":"You could get rid of most/all of the pointer casts below if using uint32_t arrays (with enums to define the meaning of the elements) instead of structs.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":65,"context_line":"struct sfdp_4byte_addr_param {"},{"line_number":66,"context_line":"\tuint32_t\t\t\tflags;\t\t\t/* 01: various flags */"},{"line_number":67,"context_line":"\tuint32_t\t\t\terase_t1234;\t/* 02: erase commands */"},{"line_number":68,"context_line":"};"},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"/* Try to get parameters from flash via SFDP */"},{"line_number":71,"context_line":"int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0ed113e2_d87a25b9","line":68,"in_reply_to":"2e76d7c5_9fdc964d","updated":"2020-05-24 14:00:44.000000000","message":"That was my idea at first too. However, dealing with multiple arrays of various sizes and some similarly named tags is quite error prone. Albeit a bit clumsy the structure approach gives type safety and no bounds checking is necessary after casting to the appropriate structure. enum indices give no type safety at all.\nArguably there is currently only one \"big\" table type at all, and this one appears in short vs. extended versions, so the theoretical benefit is rather limited. But if there is more to come ...\nTherefor I\u0027d prefer to leave it this way.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":124,"context_line":"\t\t\tretval \u003d ERROR_FAIL;"},{"line_number":125,"context_line":"\t\t\tgoto err;"},{"line_number":126,"context_line":"\t\t}"},{"line_number":127,"context_line":"\t\tretval \u003d read_sfdp_block(bank, ptr, words, (uint32_t *) ptable);"},{"line_number":128,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":129,"context_line":"\t\t\tgoto err;"},{"line_number":130,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_3fcea2ba","line":127,"range":{"start_line":127,"start_character":45,"end_line":127,"end_character":58},"updated":"2020-03-12 12:10:51.000000000","message":"useless cast","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":124,"context_line":"\t\t\tretval \u003d ERROR_FAIL;"},{"line_number":125,"context_line":"\t\t\tgoto err;"},{"line_number":126,"context_line":"\t\t}"},{"line_number":127,"context_line":"\t\tretval \u003d read_sfdp_block(bank, ptr, words, (uint32_t *) ptable);"},{"line_number":128,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":129,"context_line":"\t\t\tgoto err;"},{"line_number":130,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0ed113e2_b8816194","line":127,"range":{"start_line":127,"start_character":45,"end_line":127,"end_character":58},"in_reply_to":"2e76d7c5_3fcea2ba","updated":"2020-05-24 14:00:44.000000000","message":"Indeed, removed.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":129,"context_line":"\t\t\tgoto err;"},{"line_number":130,"context_line":""},{"line_number":131,"context_line":"\t\tfor (j \u003d 0; j \u003c words; j++)"},{"line_number":132,"context_line":"\t\t\tLOG_DEBUG(\"word %02d 0x%08X\", j + 1, ((uint32_t *) ptable)[j]);"},{"line_number":133,"context_line":""},{"line_number":134,"context_line":"\t\tif (id \u003d\u003d SFDP_BASIC_FLASH) {"},{"line_number":135,"context_line":"\t\t\tstruct sfdp_basic_flash_param *table \u003d (struct sfdp_basic_flash_param *) ptable;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_5fd35e61","line":132,"range":{"start_line":132,"start_character":41,"end_line":132,"end_character":54},"updated":"2020-03-12 12:10:51.000000000","message":"same","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":129,"context_line":"\t\t\tgoto err;"},{"line_number":130,"context_line":""},{"line_number":131,"context_line":"\t\tfor (j \u003d 0; j \u003c words; j++)"},{"line_number":132,"context_line":"\t\t\tLOG_DEBUG(\"word %02d 0x%08X\", j + 1, ((uint32_t *) ptable)[j]);"},{"line_number":133,"context_line":""},{"line_number":134,"context_line":"\t\tif (id \u003d\u003d SFDP_BASIC_FLASH) {"},{"line_number":135,"context_line":"\t\t\tstruct sfdp_basic_flash_param *table \u003d (struct sfdp_basic_flash_param *) ptable;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0ed113e2_584e359d","line":132,"range":{"start_line":132,"start_character":41,"end_line":132,"end_character":54},"in_reply_to":"2e76d7c5_5fd35e61","updated":"2020-05-24 14:00:44.000000000","message":"dto.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":218,"context_line":""},{"line_number":219,"context_line":"\t\t\tif (words \u003c 2) {"},{"line_number":220,"context_line":"\t\t\t\tLOG_ERROR(\"parameter table id\u003d0x%04\" PRIx16 \" invalid length %d\", id, words);"},{"line_number":221,"context_line":"\t\t\t\tcontinue;"},{"line_number":222,"context_line":"\t\t\t}"},{"line_number":223,"context_line":"\t\t\tLOG_INFO(\"4-byte address parameter table\");"},{"line_number":224,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_df120e01","line":221,"updated":"2020-03-12 12:10:51.000000000","message":"This leaks ptable","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":218,"context_line":""},{"line_number":219,"context_line":"\t\t\tif (words \u003c 2) {"},{"line_number":220,"context_line":"\t\t\t\tLOG_ERROR(\"parameter table id\u003d0x%04\" PRIx16 \" invalid length %d\", id, words);"},{"line_number":221,"context_line":"\t\t\t\tcontinue;"},{"line_number":222,"context_line":"\t\t\t}"},{"line_number":223,"context_line":"\t\t\tLOG_INFO(\"4-byte address parameter table\");"},{"line_number":224,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0ed113e2_7853f943","line":221,"in_reply_to":"2e76d7c5_df120e01","updated":"2020-05-24 14:00:44.000000000","message":"Right, rearranged.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":255,"context_line":"\t}"},{"line_number":256,"context_line":""},{"line_number":257,"context_line":"err:"},{"line_number":258,"context_line":"\tif (pheaders)"},{"line_number":259,"context_line":"\t\tfree(pheaders);"},{"line_number":260,"context_line":"\tif (ptable)"},{"line_number":261,"context_line":"\t\tfree(ptable);"},{"line_number":262,"context_line":""},{"line_number":263,"context_line":"\treturn retval;"},{"line_number":264,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_bf15d2eb","line":261,"range":{"start_line":258,"start_character":0,"end_line":261,"end_character":15},"updated":"2020-03-12 12:10:51.000000000","message":"just free both unconditionally","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":255,"context_line":"\t}"},{"line_number":256,"context_line":""},{"line_number":257,"context_line":"err:"},{"line_number":258,"context_line":"\tif (pheaders)"},{"line_number":259,"context_line":"\t\tfree(pheaders);"},{"line_number":260,"context_line":"\tif (ptable)"},{"line_number":261,"context_line":"\t\tfree(ptable);"},{"line_number":262,"context_line":""},{"line_number":263,"context_line":"\treturn retval;"},{"line_number":264,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0ed113e2_1848ad8b","line":261,"range":{"start_line":258,"start_character":0,"end_line":261,"end_character":15},"in_reply_to":"2e76d7c5_bf15d2eb","updated":"2020-05-24 14:00:44.000000000","message":"Ok.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"}],"src/flash/nor/sfdp.h":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":18,"context_line":"#define OPENOCD_FLASH_NOR_SFDP_H"},{"line_number":19,"context_line":""},{"line_number":20,"context_line":"/* per JESD216D \u0027addr\u0027 is *byte* based but must be word aligned,"},{"line_number":21,"context_line":" * \u0027buffer\u0027 is word based, word aligned and always little-endian encoded,"},{"line_number":22,"context_line":" * \u0027addr_len\u0027 is 3 or 4, \u0027dummy\u0027 usually 8 */"},{"line_number":23,"context_line":"typedef int (*read_sfdp_block_t)(struct flash_bank *bank, uint32_t addr,"},{"line_number":24,"context_line":"\t\tint words, uint32_t *buffer);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5cd4d54b","line":21,"updated":"2019-06-26 05:41:10.000000000","message":"The only consumer of this code, stmqspi, fills the buffer by means of target_read_u32, which converts target endianness to host endianness, not to specifically little endian. Therefore, buffer is host-endian, not little-endian, isn’t it?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":18,"context_line":"#define OPENOCD_FLASH_NOR_SFDP_H"},{"line_number":19,"context_line":""},{"line_number":20,"context_line":"/* per JESD216D \u0027addr\u0027 is *byte* based but must be word aligned,"},{"line_number":21,"context_line":" * \u0027buffer\u0027 is word based, word aligned and always little-endian encoded,"},{"line_number":22,"context_line":" * \u0027addr_len\u0027 is 3 or 4, \u0027dummy\u0027 usually 8 */"},{"line_number":23,"context_line":"typedef int (*read_sfdp_block_t)(struct flash_bank *bank, uint32_t addr,"},{"line_number":24,"context_line":"\t\tint words, uint32_t *buffer);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7cde7116","line":21,"in_reply_to":"8e7fc396_5cd4d54b","updated":"2019-07-23 20:46:58.000000000","message":"Yes and no. There are two endiannesses involved: Once when the individual bytes are read from the flash, packed into words in the QSPI FIFO and stored by the host in buffer. That\u0027s host endianness. But the byte sequence as read from the flash chip and reassembled into words is always little endian. So the comment might indeed be misleading as it refers to the data in the chip, not to buffer.\nTherefore it\u0027s presumed to be converted to host endianness by the read function. This last point is indeed missing in the comment.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"src/flash/nor/spi.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9db8a79b52b38c5e6ca4ae4f4bfdaba913803bb3","unresolved":false,"context_lines":[{"line_number":33,"context_line":" /* Shared table of known SPI flash devices for SPI-based flash drivers. Taken"},{"line_number":34,"context_line":"  * from device datasheets and Linux SPI flash drivers. */"},{"line_number":35,"context_line":"const struct flash_device flash_devices[] \u003d {"},{"line_number":36,"context_line":"\t/* name, read_cmd, pprog_cmd, erase_cmd, chip_erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */"},{"line_number":37,"context_line":"\tFLASH_ID(\"st m25p05\",           0x03, 0x02, 0xd8, 0xc7, 0x00102020, 0x80,  0x8000,  0x10000),"},{"line_number":38,"context_line":"\tFLASH_ID(\"st m25p10\",           0x03, 0x02, 0xd8, 0xc7, 0x00112020, 0x80,  0x8000,  0x20000),"},{"line_number":39,"context_line":"\tFLASH_ID(\"st m25p20\",           0x03, 0x02, 0xd8, 0xc7, 0x00122020, 0x100, 0x10000, 0x40000),"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"2e489777_373da08b","line":36,"range":{"start_line":36,"start_character":10,"end_line":36,"end_character":29},"updated":"2018-01-16 15:35:11.000000000","message":"You added new cmd fields. It is reasonable.\nI wonder what happens if an other driver (mrvlqspi.c or not yet merged fslqspi.c) works with one of the new added flash devices which have non standard read_cmd and pprog_cmd values?","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6e4bd383acec2d38cc13643adf2f8fcac817911e","unresolved":false,"context_lines":[{"line_number":33,"context_line":" /* Shared table of known SPI flash devices for SPI-based flash drivers. Taken"},{"line_number":34,"context_line":"  * from device datasheets and Linux SPI flash drivers. */"},{"line_number":35,"context_line":"const struct flash_device flash_devices[] \u003d {"},{"line_number":36,"context_line":"\t/* name, read_cmd, pprog_cmd, erase_cmd, chip_erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */"},{"line_number":37,"context_line":"\tFLASH_ID(\"st m25p05\",           0x03, 0x02, 0xd8, 0xc7, 0x00102020, 0x80,  0x8000,  0x10000),"},{"line_number":38,"context_line":"\tFLASH_ID(\"st m25p10\",           0x03, 0x02, 0xd8, 0xc7, 0x00112020, 0x80,  0x8000,  0x20000),"},{"line_number":39,"context_line":"\tFLASH_ID(\"st m25p20\",           0x03, 0x02, 0xd8, 0xc7, 0x00122020, 0x100, 0x10000, 0x40000),"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"0e83d3c5_42271260","line":36,"range":{"start_line":36,"start_character":10,"end_line":36,"end_character":29},"in_reply_to":"2e489777_373da08b","updated":"2018-01-20 18:36:26.000000000","message":"This should currently be no problem. All devices larger than 16 MBytes with new commands support both the legacy and the new commands (i. e. 0x03 vs. 0x13 read, 0x02 vs. 0x12 pprog) except that the old ones use 3-byte address by default and have a command to switch to 4-byte addresses for the old ones. The new ones always use 4-byte addresses.\n\nOnly exception seems to be the octo-spi MX25LM51245 (fitted on L4R9I-disco) which does NOT support 4-byte addresses with legacy commands at all. So strictly speaking, only this chip requires the new commands (and maybe MT35XL512ABA, too, but no datasheet without signing an NDA ...).","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"}],"src/flash/nor/stmqspi.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9db8a79b52b38c5e6ca4ae4f4bfdaba913803bb3","unresolved":false,"context_lines":[{"line_number":1192,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1193,"context_line":"\tpage_size \u003d stmqspi_info-\u003edev.pagesize \u003c\u003c dual;"},{"line_number":1194,"context_line":"\tfifo_size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"},{"line_number":1195,"context_line":"\twhile (buffer_size \u003d write_code_size + 2 * sizeof(uint32_t) + fifo_size,"},{"line_number":1196,"context_line":"\t\t\ttarget_alloc_working_area_try(target, buffer_size, \u0026write_algorithm) !\u003d ERROR_OK) {"},{"line_number":1197,"context_line":"\t\tfifo_size /\u003d 2;"},{"line_number":1198,"context_line":"\t\tif (fifo_size \u003c page_size) {"},{"line_number":1199,"context_line":"\t\t\tLOG_WARNING(\"not enough working area, can\u0027t do QSPI page writes\");"},{"line_number":1200,"context_line":"\t\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"},{"line_number":1201,"context_line":"\t\t}"},{"line_number":1202,"context_line":"\t};"},{"line_number":1203,"context_line":""},{"line_number":1204,"context_line":"\t/* prepare flash write code, excluding ccr_buffer */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"2e489777_f746e825","line":1201,"range":{"start_line":1195,"start_character":0,"end_line":1201,"end_character":3},"updated":"2018-01-16 15:35:11.000000000","message":"Please use target_get_working_area_avail() instead of iterating","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6e4bd383acec2d38cc13643adf2f8fcac817911e","unresolved":false,"context_lines":[{"line_number":1192,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1193,"context_line":"\tpage_size \u003d stmqspi_info-\u003edev.pagesize \u003c\u003c dual;"},{"line_number":1194,"context_line":"\tfifo_size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"},{"line_number":1195,"context_line":"\twhile (buffer_size \u003d write_code_size + 2 * sizeof(uint32_t) + fifo_size,"},{"line_number":1196,"context_line":"\t\t\ttarget_alloc_working_area_try(target, buffer_size, \u0026write_algorithm) !\u003d ERROR_OK) {"},{"line_number":1197,"context_line":"\t\tfifo_size /\u003d 2;"},{"line_number":1198,"context_line":"\t\tif (fifo_size \u003c page_size) {"},{"line_number":1199,"context_line":"\t\t\tLOG_WARNING(\"not enough working area, can\u0027t do QSPI page writes\");"},{"line_number":1200,"context_line":"\t\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"},{"line_number":1201,"context_line":"\t\t}"},{"line_number":1202,"context_line":"\t};"},{"line_number":1203,"context_line":""},{"line_number":1204,"context_line":"\t/* prepare flash write code, excluding ccr_buffer */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"0e83d3c5_a215beeb","line":1201,"range":{"start_line":1195,"start_character":0,"end_line":1201,"end_character":3},"in_reply_to":"2e489777_f746e825","updated":"2018-01-20 18:36:26.000000000","message":"Seems to be new, didn\u0027t realize this to be present before. Thanks for the hint.","commit_id":"2a9a9d5cf9f99fd6981cd2ba34e411304260291a"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":45,"context_line":"#include \u003ctarget/armv7m.h\u003e"},{"line_number":46,"context_line":"#include \"stmqspi.h\""},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"#define READ_REG(a)\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":49,"context_line":"({\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":50,"context_line":"\tuint32_t __v;\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":51,"context_line":"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_57427414","line":48,"updated":"2018-10-14 22:56:00.000000000","message":"This macro reads a register, but also has the unexpected side effect of overwriting the retval variable in the calling scope. This is IMO a bit confusing, and you only use it in two places (both in stmqspi_probe). If you don’t care about checking for errors, would it make sense to turn this into a function which returns the data value and use the function everywhere except those two places in stmqspi_probe?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":47,"context_line":""},{"line_number":48,"context_line":"#define READ_REG(a)\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":49,"context_line":"({\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":50,"context_line":"\tuint32_t __v;\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":51,"context_line":"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":52,"context_line":"\tretval \u003d target_read_u32(target, io_base + (a), \u0026__v);\t\\"},{"line_number":53,"context_line":"\t(retval \u003d\u003d ERROR_OK) ? __v : 0x0;\t\t\t\t\t\t\\"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_7749b069","line":50,"updated":"2018-10-14 22:56:00.000000000","message":"Names starting with two underscores are reserved for the compiler or standard library, per ISO C. Also, does this even benefit from being a macro? Wouldn’t it be simpler to make it a function (static, and inline if you’re concerned about performance)?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":119,"context_line":""},{"line_number":120,"context_line":"#define OPI_CMD(cmd) (OPI_MODE ? ((((uint16_t) cmd)\u003c\u003c8) | (~cmd \u0026 0xFF)) : cmd)"},{"line_number":121,"context_line":""},{"line_number":122,"context_line":"#define OCTOSPI_CMD(mode, ccr, ir)\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":123,"context_line":"({\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":124,"context_line":"\tretval \u003d target_write_u32(target, io_base + OCTOSPI_CR,\t\t\t\t\\"},{"line_number":125,"context_line":"\t\tOCTOSPI_MODE | mode);\t\t\t\t\t\t\t\t\t\t\t\\"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_974ebc71","line":122,"updated":"2018-10-14 22:56:00.000000000","message":"Every single place you call this macro, you take its return value and assign it to the local retval variable. Therefore, this could be a static function instead of a macro, which would IMO be tidier and clearer because it would not have the side effect of implicitly overwriting retval in a non-obvious way (although that side effect is never actually used right now).","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":137,"context_line":"})"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"/* convert uint32_t into 4 uint8_t in little endian byte order */"},{"line_number":140,"context_line":"static inline uint32_t h_to_le_32(uint32_t val)"},{"line_number":141,"context_line":"{"},{"line_number":142,"context_line":"\tunion {"},{"line_number":143,"context_line":"\t\tuint32_t word;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_3753281c","line":140,"updated":"2018-10-14 22:56:00.000000000","message":"There is an h_u32_to_le function in helper/types.h; could you use it?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":137,"context_line":"})"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"/* convert uint32_t into 4 uint8_t in little endian byte order */"},{"line_number":140,"context_line":"static inline uint32_t h_to_le_32(uint32_t val)"},{"line_number":141,"context_line":"{"},{"line_number":142,"context_line":"\tunion {"},{"line_number":143,"context_line":"\t\tuint32_t word;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_66581f36","line":140,"in_reply_to":"6e936f18_3753281c","updated":"2018-11-02 19:20:01.000000000","message":"Could, but I do prefer to initialize ccr_buffer properly in the first place, and not to correct the endianness in a separate step.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":165,"context_line":"};"},{"line_number":166,"context_line":""},{"line_number":167,"context_line":"struct stmqspi_flash_bank {"},{"line_number":168,"context_line":"\tint probed;"},{"line_number":169,"context_line":"\tchar devname[32];"},{"line_number":170,"context_line":"\tbool octo;"},{"line_number":171,"context_line":"\tstruct flash_device dev;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_57583435","line":168,"updated":"2018-10-14 22:56:00.000000000","message":"This is only ever set to 0 and 1. Why not make it a bool?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":165,"context_line":"};"},{"line_number":166,"context_line":""},{"line_number":167,"context_line":"struct stmqspi_flash_bank {"},{"line_number":168,"context_line":"\tint probed;"},{"line_number":169,"context_line":"\tchar devname[32];"},{"line_number":170,"context_line":"\tbool octo;"},{"line_number":171,"context_line":"\tstruct flash_device dev;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e62c2f92","line":168,"in_reply_to":"6e936f18_57583435","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":186,"context_line":"\tif (CMD_ARGC \u003c 7)"},{"line_number":187,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], bank-\u003ebase);"},{"line_number":190,"context_line":"\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], io_base);"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"\tstmqspi_info \u003d malloc(sizeof(struct stmqspi_flash_bank));"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f73ce0be","line":189,"updated":"2018-10-14 22:56:00.000000000","message":"The common code (in src/flash/nor/tcl.c) already fills in bank-\u003ebase. No need to parse it here.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":186,"context_line":"\tif (CMD_ARGC \u003c 7)"},{"line_number":187,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], bank-\u003ebase);"},{"line_number":190,"context_line":"\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], io_base);"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"\tstmqspi_info \u003d malloc(sizeof(struct stmqspi_flash_bank));"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_46a963db","line":189,"in_reply_to":"6e936f18_f73ce0be","updated":"2018-11-02 19:20:01.000000000","message":"dropped","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":213,"context_line":"\tlong long endtime;"},{"line_number":214,"context_line":""},{"line_number":215,"context_line":"\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0)"},{"line_number":216,"context_line":"\t\treturn ERROR_OK;"},{"line_number":217,"context_line":""},{"line_number":218,"context_line":"\tendtime \u003d timeval_ms() + timeout;"},{"line_number":219,"context_line":"\tdo {"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_173aacc0","line":216,"updated":"2018-10-14 22:56:00.000000000","message":"READ_REG returns 0 if communication with the target fails. Therefore this will return ERROR_OK when there is an error.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":213,"context_line":"\tlong long endtime;"},{"line_number":214,"context_line":""},{"line_number":215,"context_line":"\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0)"},{"line_number":216,"context_line":"\t\treturn ERROR_OK;"},{"line_number":217,"context_line":""},{"line_number":218,"context_line":"\tendtime \u003d timeval_ms() + timeout;"},{"line_number":219,"context_line":"\tdo {"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e6b98f2a","line":216,"in_reply_to":"6e936f18_173aacc0","updated":"2018-11-02 19:20:01.000000000","message":"changed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":218,"context_line":"\tendtime \u003d timeval_ms() + timeout;"},{"line_number":219,"context_line":"\tdo {"},{"line_number":220,"context_line":"\t\talive_sleep(1);"},{"line_number":221,"context_line":"\t\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0) {"},{"line_number":222,"context_line":"\t\t\t/* Clear transmit finished flag */"},{"line_number":223,"context_line":"\t\t\tretval \u003d target_write_u32(target, io_base + SPI_FCR, (1\u003c\u003cSPI_TCF));"},{"line_number":224,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_57fcb4d5","line":221,"updated":"2018-10-14 22:56:00.000000000","message":"READ_REG returns 0 if communication with the target fails. Therefore this could return ERROR_OK if there is a temporary error reading from the register.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":218,"context_line":"\tendtime \u003d timeval_ms() + timeout;"},{"line_number":219,"context_line":"\tdo {"},{"line_number":220,"context_line":"\t\talive_sleep(1);"},{"line_number":221,"context_line":"\t\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0) {"},{"line_number":222,"context_line":"\t\t\t/* Clear transmit finished flag */"},{"line_number":223,"context_line":"\t\t\tretval \u003d target_write_u32(target, io_base + SPI_FCR, (1\u003c\u003cSPI_TCF));"},{"line_number":224,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_86868b69","line":221,"in_reply_to":"6e936f18_57fcb4d5","updated":"2018-11-02 19:20:01.000000000","message":"changed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":220,"context_line":"\t\talive_sleep(1);"},{"line_number":221,"context_line":"\t\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0) {"},{"line_number":222,"context_line":"\t\t\t/* Clear transmit finished flag */"},{"line_number":223,"context_line":"\t\t\tretval \u003d target_write_u32(target, io_base + SPI_FCR, (1\u003c\u003cSPI_TCF));"},{"line_number":224,"context_line":"\t\t\treturn retval;"},{"line_number":225,"context_line":"\t\t} else"},{"line_number":226,"context_line":"\t\t\tLOG_DEBUG(\"busy: 0x%08X\", READ_REG(SPI_SR));"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b7465853","line":223,"updated":"2018-10-14 22:56:00.000000000","message":"What if the operation finished really quickly? Then you will see that the BUSY bit is clear before entering the loop, so you will return right away, which means you will not clear TCF. But if the operation takes a bit longer, then you will get into the loop, and when BUSY goes to 0, then you will clear TCF.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":220,"context_line":"\t\talive_sleep(1);"},{"line_number":221,"context_line":"\t\tif ((READ_REG(SPI_SR) \u0026 (1\u003c\u003cSPI_BUSY)) \u003d\u003d 0) {"},{"line_number":222,"context_line":"\t\t\t/* Clear transmit finished flag */"},{"line_number":223,"context_line":"\t\t\tretval \u003d target_write_u32(target, io_base + SPI_FCR, (1\u003c\u003cSPI_TCF));"},{"line_number":224,"context_line":"\t\t\treturn retval;"},{"line_number":225,"context_line":"\t\t} else"},{"line_number":226,"context_line":"\t\t\tLOG_DEBUG(\"busy: 0x%08X\", READ_REG(SPI_SR));"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_c69333a5","line":223,"in_reply_to":"6e936f18_b7465853","updated":"2018-11-02 19:20:01.000000000","message":"loop rearranged and busy check outside removed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":305,"context_line":"\t\tgoto err;"},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":308,"context_line":"\t\tgoto err;"},{"line_number":309,"context_line":""},{"line_number":310,"context_line":"\t*status \u003d 0;"},{"line_number":311,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_97f23c02","line":308,"updated":"2018-10-14 22:56:00.000000000","message":"These two lines are a copy of the lines above, and don’t do anything.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":305,"context_line":"\t\tgoto err;"},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":308,"context_line":"\t\tgoto err;"},{"line_number":309,"context_line":""},{"line_number":310,"context_line":"\t*status \u003d 0;"},{"line_number":311,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a6006705","line":308,"in_reply_to":"6e936f18_97f23c02","updated":"2018-11-02 19:20:01.000000000","message":"Correct.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":330,"context_line":"\tLOG_DEBUG(\"flash status regs: 0x%04\" PRIx16, *status);"},{"line_number":331,"context_line":""},{"line_number":332,"context_line":"err:"},{"line_number":333,"context_line":"\treturn retval;"},{"line_number":334,"context_line":"}"},{"line_number":335,"context_line":""},{"line_number":336,"context_line":"/* check for WIP (write in progress) bit(s) in status register(s) */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_7770d0a3","line":333,"updated":"2018-10-14 22:56:00.000000000","message":"Given that there’s only one statement here at the err label, why not just write “return retval;” in each place where you currently have “goto err;”?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":330,"context_line":"\tLOG_DEBUG(\"flash status regs: 0x%04\" PRIx16, *status);"},{"line_number":331,"context_line":""},{"line_number":332,"context_line":"err:"},{"line_number":333,"context_line":"\treturn retval;"},{"line_number":334,"context_line":"}"},{"line_number":335,"context_line":""},{"line_number":336,"context_line":"/* check for WIP (write in progress) bit(s) in status register(s) */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_c646d354","line":333,"in_reply_to":"6e936f18_7770d0a3","updated":"2018-11-02 19:20:01.000000000","message":"just consistency","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":354,"context_line":"\t} while (timeval_ms() \u003c endtime);"},{"line_number":355,"context_line":""},{"line_number":356,"context_line":"\tLOG_ERROR(\"timeout\");"},{"line_number":357,"context_line":"\treturn ERROR_FAIL;"},{"line_number":358,"context_line":"}"},{"line_number":359,"context_line":""},{"line_number":360,"context_line":"/* Send \"write enable\" command to SPI flash chip(s). */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_576fd4c0","line":357,"updated":"2018-10-14 22:56:00.000000000","message":"How about ERROR_FLASH_OPERATION_FAILED?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":354,"context_line":"\t} while (timeval_ms() \u003c endtime);"},{"line_number":355,"context_line":""},{"line_number":356,"context_line":"\tLOG_ERROR(\"timeout\");"},{"line_number":357,"context_line":"\treturn ERROR_FAIL;"},{"line_number":358,"context_line":"}"},{"line_number":359,"context_line":""},{"line_number":360,"context_line":"/* Send \"write enable\" command to SPI flash chip(s). */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a68b8771","line":357,"in_reply_to":"6e936f18_576fd4c0","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":398,"context_line":"\t/* Check write enabled for flash 1 */"},{"line_number":399,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":400,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_WE_BIT) \u003d\u003d 0)) {"},{"line_number":401,"context_line":"\t\tLOG_ERROR(\"Cannot write enable flash1. Status\u003d0x%02\" PRIx8, status \u0026 0xFF);"},{"line_number":402,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":403,"context_line":"\t}"},{"line_number":404,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_d75a0422","line":401,"updated":"2018-10-14 22:56:00.000000000","message":"PRIx8 is supposed to be passed a uint8_t, is it not? Whereas status is a uint32_t? So I think you should cast it (yes, there will be the usual integer promotions for a varargs function, but if uint32_t is bigger than int on the platform in question then you would still have a problem).","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":398,"context_line":"\t/* Check write enabled for flash 1 */"},{"line_number":399,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":400,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_WE_BIT) \u003d\u003d 0)) {"},{"line_number":401,"context_line":"\t\tLOG_ERROR(\"Cannot write enable flash1. Status\u003d0x%02\" PRIx8, status \u0026 0xFF);"},{"line_number":402,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":403,"context_line":"\t}"},{"line_number":404,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a675c794","line":401,"in_reply_to":"6e936f18_d75a0422","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":399,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":400,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_WE_BIT) \u003d\u003d 0)) {"},{"line_number":401,"context_line":"\t\tLOG_ERROR(\"Cannot write enable flash1. Status\u003d0x%02\" PRIx8, status \u0026 0xFF);"},{"line_number":402,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":403,"context_line":"\t}"},{"line_number":404,"context_line":""},{"line_number":405,"context_line":"\t/* Check write enabled for flash 2 */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b75df81c","line":402,"updated":"2018-10-14 22:56:00.000000000","message":"ERROR_FLASH_OPERATION_FAILED, here and on line 409?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":399,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":400,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_WE_BIT) \u003d\u003d 0)) {"},{"line_number":401,"context_line":"\t\tLOG_ERROR(\"Cannot write enable flash1. Status\u003d0x%02\" PRIx8, status \u0026 0xFF);"},{"line_number":402,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":403,"context_line":"\t}"},{"line_number":404,"context_line":""},{"line_number":405,"context_line":"\t/* Check write enabled for flash 2 */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_0664bbe0","line":402,"in_reply_to":"6e936f18_b75df81c","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":410,"context_line":"\t}"},{"line_number":411,"context_line":""},{"line_number":412,"context_line":"err:"},{"line_number":413,"context_line":"\treturn retval;"},{"line_number":414,"context_line":"}"},{"line_number":415,"context_line":""},{"line_number":416,"context_line":"COMMAND_HANDLER(stmqspi_handle_mass_erase_command)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f76380d8","line":413,"updated":"2018-10-14 22:56:00.000000000","message":"Given that there’s only one statement here at the err label, why not just write “return retval;” in each place where you currently have “goto err;”?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":410,"context_line":"\t}"},{"line_number":411,"context_line":""},{"line_number":412,"context_line":"err:"},{"line_number":413,"context_line":"\treturn retval;"},{"line_number":414,"context_line":"}"},{"line_number":415,"context_line":""},{"line_number":416,"context_line":"COMMAND_HANDLER(stmqspi_handle_mass_erase_command)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e643cf41","line":413,"in_reply_to":"6e936f18_f76380d8","updated":"2018-11-02 19:20:01.000000000","message":"as above","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":452,"context_line":"\tfor (sector \u003d 0; sector \u003c\u003d bank-\u003enum_sectors; sector++) {"},{"line_number":453,"context_line":"\t\tif (bank-\u003esectors[sector].is_protected) {"},{"line_number":454,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":455,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":456,"context_line":"\t\t}"},{"line_number":457,"context_line":"\t}"},{"line_number":458,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_779f70ba","line":455,"updated":"2018-10-14 22:56:00.000000000","message":"How about ERROR_FLASH_PROTECTED?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":452,"context_line":"\tfor (sector \u003d 0; sector \u003c\u003d bank-\u003enum_sectors; sector++) {"},{"line_number":453,"context_line":"\t\tif (bank-\u003esectors[sector].is_protected) {"},{"line_number":454,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":455,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":456,"context_line":"\t\t}"},{"line_number":457,"context_line":"\t}"},{"line_number":458,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_c65d731c","line":455,"in_reply_to":"6e936f18_779f70ba","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":481,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":482,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_BSY_BIT) \u003d\u003d 0)) {"},{"line_number":483,"context_line":"\t\tLOG_ERROR(\"Mass erase command not accepted by flash1. Status\u003d0x%04\" PRIx16, status);"},{"line_number":484,"context_line":"\t\tretval \u003d ERROR_FAIL;"},{"line_number":485,"context_line":"\t\tgoto err;"},{"line_number":486,"context_line":"\t}"},{"line_number":487,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_97a47c06","line":484,"updated":"2018-10-14 22:56:00.000000000","message":"How about ERROR_FLASH_OPERATION_FAILED here and on line 492?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":481,"context_line":"\tif (((stmqspi_info-\u003esaved_cr \u0026 ((1\u003c\u003cSPI_DUAL_FLASH) | (1\u003c\u003cSPI_FSEL_FLASH)))"},{"line_number":482,"context_line":"\t\t!\u003d (1\u003c\u003cSPI_FSEL_FLASH)) \u0026\u0026 ((status \u0026 SPIFLASH_BSY_BIT) \u003d\u003d 0)) {"},{"line_number":483,"context_line":"\t\tLOG_ERROR(\"Mass erase command not accepted by flash1. Status\u003d0x%04\" PRIx16, status);"},{"line_number":484,"context_line":"\t\tretval \u003d ERROR_FAIL;"},{"line_number":485,"context_line":"\t\tgoto err;"},{"line_number":486,"context_line":"\t}"},{"line_number":487,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e690af9a","line":484,"in_reply_to":"6e936f18_97a47c06","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":517,"context_line":"\treturn retval;"},{"line_number":518,"context_line":"}"},{"line_number":519,"context_line":""},{"line_number":520,"context_line":"static int log2u(uint32_t word)"},{"line_number":521,"context_line":"{"},{"line_number":522,"context_line":"\tint result;"},{"line_number":523,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_37a9e8dc","line":520,"updated":"2018-10-14 22:56:00.000000000","message":"I noticed that you only use this function for two purposes: checking that a value is a power of two, and checking that it’s larger or smaller than some other value. For the first purpose, “(N \u0026 (N - 1)) \u003d\u003d 0” is true if and only if N is a power of two. For the second purpose, you could just compare the values directly. I think that would be more efficient than calculating the log, wouldn’t it?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":517,"context_line":"\treturn retval;"},{"line_number":518,"context_line":"}"},{"line_number":519,"context_line":""},{"line_number":520,"context_line":"static int log2u(uint32_t word)"},{"line_number":521,"context_line":"{"},{"line_number":522,"context_line":"\tint result;"},{"line_number":523,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_66fc9fd6","line":520,"in_reply_to":"6e936f18_37a9e8dc","updated":"2018-11-02 19:20:01.000000000","message":"For the second: yes, log2u removed.\nFor the first: no, this would require an extra check for zero. Would be more efficient, no doubt, but it\u0027s used just three times at all, so negligible. On the other hand, log2u expresses more precisely what\u0027s intended, I think.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":531,"context_line":"COMMAND_HANDLER(stmqspi_handle_setparms)"},{"line_number":532,"context_line":"{"},{"line_number":533,"context_line":"\tstruct flash_bank *bank \u003d NULL;"},{"line_number":534,"context_line":"\tstruct target *target \u003d NULL;"},{"line_number":535,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d NULL;"},{"line_number":536,"context_line":"\tstruct flash_sector *sectors \u003d NULL;"},{"line_number":537,"context_line":"\tuint32_t io_base, temp;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_978b1c72","line":534,"range":{"start_line":534,"start_character":16,"end_line":534,"end_character":22},"updated":"2018-10-14 22:56:00.000000000","message":"This variable is assigned a few lines down, but it is never used in this function. It can be deleted.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":531,"context_line":"COMMAND_HANDLER(stmqspi_handle_setparms)"},{"line_number":532,"context_line":"{"},{"line_number":533,"context_line":"\tstruct flash_bank *bank \u003d NULL;"},{"line_number":534,"context_line":"\tstruct target *target \u003d NULL;"},{"line_number":535,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d NULL;"},{"line_number":536,"context_line":"\tstruct flash_sector *sectors \u003d NULL;"},{"line_number":537,"context_line":"\tuint32_t io_base, temp;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_466ac3b2","line":534,"range":{"start_line":534,"start_character":16,"end_line":534,"end_character":22},"in_reply_to":"6e936f18_978b1c72","updated":"2018-11-02 19:20:01.000000000","message":"No, it IS used, but that\u0027s hidden in READ_REG","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":593,"context_line":"\tif (CMD_ARGC \u003e 6)"},{"line_number":594,"context_line":"\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[6], stmqspi_info-\u003edev.chip_erase_cmd);"},{"line_number":595,"context_line":"\telse"},{"line_number":596,"context_line":"\t\tstmqspi_info-\u003edev.chip_erase_cmd \u003d 0x00;"},{"line_number":597,"context_line":""},{"line_number":598,"context_line":"\tif (CMD_ARGC \u003e 7) {"},{"line_number":599,"context_line":"\t\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], temp);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_57aef4e5","line":596,"updated":"2018-10-14 22:56:00.000000000","message":"You already memset the struct, so this assignment is not necessary.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":593,"context_line":"\tif (CMD_ARGC \u003e 6)"},{"line_number":594,"context_line":"\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[6], stmqspi_info-\u003edev.chip_erase_cmd);"},{"line_number":595,"context_line":"\telse"},{"line_number":596,"context_line":"\t\tstmqspi_info-\u003edev.chip_erase_cmd \u003d 0x00;"},{"line_number":597,"context_line":""},{"line_number":598,"context_line":"\tif (CMD_ARGC \u003e 7) {"},{"line_number":599,"context_line":"\t\tCOMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], temp);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_3216d65b","line":596,"in_reply_to":"6e936f18_57aef4e5","updated":"2018-11-02 19:20:01.000000000","message":"Deliberately: Emphasize that 0x00 means no erase command avaliable.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":610,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":611,"context_line":"\t} else {"},{"line_number":612,"context_line":"\t\t/* no sector size / sector erase cmd given, treat whole bank as a single sector */"},{"line_number":613,"context_line":"\t\tstmqspi_info-\u003edev.erase_cmd \u003d 0x00;"},{"line_number":614,"context_line":"\t\tstmqspi_info-\u003edev.sectorsize \u003d stmqspi_info-\u003edev.size_in_bytes;"},{"line_number":615,"context_line":"\t}"},{"line_number":616,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f7b2a047","line":613,"updated":"2018-10-14 22:56:00.000000000","message":"You already memset the struct, so this assignment is not necessary.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":610,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":611,"context_line":"\t} else {"},{"line_number":612,"context_line":"\t\t/* no sector size / sector erase cmd given, treat whole bank as a single sector */"},{"line_number":613,"context_line":"\t\tstmqspi_info-\u003edev.erase_cmd \u003d 0x00;"},{"line_number":614,"context_line":"\t\tstmqspi_info-\u003edev.sectorsize \u003d stmqspi_info-\u003edev.size_in_bytes;"},{"line_number":615,"context_line":"\t}"},{"line_number":616,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_521b6282","line":613,"in_reply_to":"6e936f18_f7b2a047","updated":"2018-11-02 19:20:01.000000000","message":"As above","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":623,"context_line":"\tfsize \u003d (READ_REG(SPI_DCR)\u003e\u003eSPI_FSIZE_POS) \u0026 ((1U\u003c\u003cSPI_FSIZE_LEN) - 1);"},{"line_number":624,"context_line":"\tLOG_DEBUG(\"FSIZE \u003d 0x%04x\", fsize);"},{"line_number":625,"context_line":"\tif (bank-\u003esize !\u003d (1U\u003c\u003c(fsize + 1)))"},{"line_number":626,"context_line":"\t\tLOG_WARNING(\"FSIZE field in QSPI_DCR(1) doesn\u0027t match actual capacity.\");"},{"line_number":627,"context_line":""},{"line_number":628,"context_line":"\t/* create and fill sectors array */"},{"line_number":629,"context_line":"\tbank-\u003enum_sectors \u003d"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_17b06c3d","line":626,"updated":"2018-10-14 22:56:00.000000000","message":"What is “(1)” for?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":623,"context_line":"\tfsize \u003d (READ_REG(SPI_DCR)\u003e\u003eSPI_FSIZE_POS) \u0026 ((1U\u003c\u003cSPI_FSIZE_LEN) - 1);"},{"line_number":624,"context_line":"\tLOG_DEBUG(\"FSIZE \u003d 0x%04x\", fsize);"},{"line_number":625,"context_line":"\tif (bank-\u003esize !\u003d (1U\u003c\u003c(fsize + 1)))"},{"line_number":626,"context_line":"\t\tLOG_WARNING(\"FSIZE field in QSPI_DCR(1) doesn\u0027t match actual capacity.\");"},{"line_number":627,"context_line":""},{"line_number":628,"context_line":"\t/* create and fill sectors array */"},{"line_number":629,"context_line":"\tbank-\u003enum_sectors \u003d"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_120dda41","line":626,"in_reply_to":"6e936f18_17b06c3d","updated":"2018-11-02 19:20:01.000000000","message":"QuadSPI: QUADSPI_DCR\nOctoSPI: OCTOSPI_DCR1","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":638,"context_line":"\t\tsectors[sector].offset \u003d sector * (stmqspi_info-\u003edev.sectorsize \u003c\u003c dual);"},{"line_number":639,"context_line":"\t\tsectors[sector].size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"},{"line_number":640,"context_line":"\t\tsectors[sector].is_erased \u003d -1;"},{"line_number":641,"context_line":"\t\tsectors[sector].is_protected \u003d 0;"},{"line_number":642,"context_line":"\t}"},{"line_number":643,"context_line":""},{"line_number":644,"context_line":"\tbank-\u003esectors \u003d sectors;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b7bc181c","line":641,"updated":"2018-10-14 22:56:00.000000000","message":"Shouldn’t this be unknown at this point, not unprotected? The comment in src/flash/nor/core.h says 0\u003dunprotected, 1\u003dprotected, other\u003dunknown.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":638,"context_line":"\t\tsectors[sector].offset \u003d sector * (stmqspi_info-\u003edev.sectorsize \u003c\u003c dual);"},{"line_number":639,"context_line":"\t\tsectors[sector].size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"},{"line_number":640,"context_line":"\t\tsectors[sector].is_erased \u003d -1;"},{"line_number":641,"context_line":"\t\tsectors[sector].is_protected \u003d 0;"},{"line_number":642,"context_line":"\t}"},{"line_number":643,"context_line":""},{"line_number":644,"context_line":"\tbank-\u003esectors \u003d sectors;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e65aef21","line":641,"in_reply_to":"6e936f18_b7bc181c","updated":"2018-11-02 19:20:01.000000000","message":"No, as this only a \u0027soft\u0027 protection, it should be better set to unprotected so that doesn\u0027t disturb when this protection is not used at all. Only explicit activation should have any effect.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":648,"context_line":"\treturn ERROR_OK;"},{"line_number":649,"context_line":"}"},{"line_number":650,"context_line":""},{"line_number":651,"context_line":"COMMAND_HANDLER(stmqspi_handle_spicmd)"},{"line_number":652,"context_line":"{"},{"line_number":653,"context_line":"\tstruct target *target \u003d NULL;"},{"line_number":654,"context_line":"\tstruct flash_bank *bank;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b793b8a5","line":651,"updated":"2018-10-14 22:56:00.000000000","message":"This command just prints some formatted output right now. Would it be useful to make a low-level command that does the reading and writing and, in the case of a read, returns the read bytes as a TCL array? Then TCL code or RPC clients could use the low-level command to operate on the Flash, and it would get nice arrays of bytes back when doing a read.\n\nA high-level command that just prints the result could easily be written in TCL to wrap the low-level command for human usage.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":648,"context_line":"\treturn ERROR_OK;"},{"line_number":649,"context_line":"}"},{"line_number":650,"context_line":""},{"line_number":651,"context_line":"COMMAND_HANDLER(stmqspi_handle_spicmd)"},{"line_number":652,"context_line":"{"},{"line_number":653,"context_line":"\tstruct target *target \u003d NULL;"},{"line_number":654,"context_line":"\tstruct flash_bank *bank;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_4680834b","line":651,"in_reply_to":"6e936f18_b793b8a5","updated":"2018-11-02 19:20:01.000000000","message":"Hm, I can hardly image any use for this command except for configuration of the flash in a cfg file. It\u0027s too restricted regarding number of parameters etc. by hardware to be of general use. And I\u0027m not familiar with TCL at all ;-)","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":666,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":667,"context_line":""},{"line_number":668,"context_line":"\tnum_write \u003d CMD_ARGC - 2;"},{"line_number":669,"context_line":"\tif (num_write \u003e max) {"},{"line_number":670,"context_line":"\t\tLOG_ERROR(\"at most %d bytes may be send\", max);"},{"line_number":671,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":672,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_7786906c","line":669,"updated":"2018-10-14 22:56:00.000000000","message":"This check is redundant with the (CMD_ARGC \u003e max + 3) case in the preceding if block, although they check different values (the previous if block rejects when ARGC \u003e 24, while this case rejects when ARGC \u003e 23). Because there is a LOG_ERROR in this branch, I think the previous check should be deleted, so that the error message will always be visible if the user types too many bytes.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":666,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":667,"context_line":""},{"line_number":668,"context_line":"\tnum_write \u003d CMD_ARGC - 2;"},{"line_number":669,"context_line":"\tif (num_write \u003e max) {"},{"line_number":670,"context_line":"\t\tLOG_ERROR(\"at most %d bytes may be send\", max);"},{"line_number":671,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":672,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a6a4e705","line":669,"in_reply_to":"6e936f18_7786906c","updated":"2018-11-02 19:20:01.000000000","message":"Removed CMD_ARGC \u003e max + 3","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":688,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);"},{"line_number":689,"context_line":""},{"line_number":690,"context_line":"\tif (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":691,"context_line":"\t\tif ((num_write \u0026 1) \u003d\u003d 0) {"},{"line_number":692,"context_line":"\t\t\tLOG_ERROR(\"number of data bytes to write must be even in dual mode\");"},{"line_number":693,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":694,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_3780084b","line":691,"updated":"2018-10-14 22:56:00.000000000","message":"According to the documentation, if resp_num is nonzero, then cmd_byte and up to four following data bytes are sent simultaneously to both chips. So in that case, it should be OK for num_write to be odd, shouldn’t it? num_write only needs to be even if no reading is happening?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":688,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);"},{"line_number":689,"context_line":""},{"line_number":690,"context_line":"\tif (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":691,"context_line":"\t\tif ((num_write \u0026 1) \u003d\u003d 0) {"},{"line_number":692,"context_line":"\t\t\tLOG_ERROR(\"number of data bytes to write must be even in dual mode\");"},{"line_number":693,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":694,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f20f0e3a","line":691,"in_reply_to":"6e936f18_3780084b","updated":"2018-11-02 19:20:01.000000000","message":"No, there is a subtle difference: If num_read equals zero the first byte (command) is sent to both chips simultaneously (both receive the very same command). The following bytes (data) are sent alternatingly to both chips, i. e. flash 1 gets bytes 1, 3, 5, ... and flash 2 bytes 2, 4, 6, ...  \nIf num_read is non-zero all bytes to be send are sent simultaneously to both chips. \nThat\u0027s hardware dictated: instructions and addresses always go to both chips simultaneously, data bytes are always interleaved between both chips.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"37e8dc0a8b0b919753c07ae63a2d1ec640f0bf6d","unresolved":false,"context_lines":[{"line_number":688,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);"},{"line_number":689,"context_line":""},{"line_number":690,"context_line":"\tif (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":691,"context_line":"\t\tif ((num_write \u0026 1) \u003d\u003d 0) {"},{"line_number":692,"context_line":"\t\t\tLOG_ERROR(\"number of data bytes to write must be even in dual mode\");"},{"line_number":693,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":694,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a669471f","line":691,"in_reply_to":"6e936f18_f20f0e3a","updated":"2018-11-14 20:56:01.000000000","message":"That’s exactly my point: if num_read is nonzero, then num_write bytes are sent simultaneously to both chips. So it should be OK for num_write to be odd. Say, if num_write is 3 and num_read is 4, then that means you send write byte 1 to both chips, then write byte 2 to both chips, then write byte 3 to both chips, then you start reading. Only if num_read is zero, then the interleaving happens so num_write needs to be even. Isn’t that right?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f1ea7c0e27390b4d269b39c953becd46b7168f96","unresolved":false,"context_lines":[{"line_number":688,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);"},{"line_number":689,"context_line":""},{"line_number":690,"context_line":"\tif (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":691,"context_line":"\t\tif ((num_write \u0026 1) \u003d\u003d 0) {"},{"line_number":692,"context_line":"\t\t\tLOG_ERROR(\"number of data bytes to write must be even in dual mode\");"},{"line_number":693,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":694,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"ee703fc5_8e5f87e8","line":691,"in_reply_to":"6e936f18_f20f0e3a","updated":"2019-05-22 06:32:08.000000000","message":"Yes, you\u0027re right, I changed this accordingly. So:\nIf num_read \u003d\u003d 0 then first byte is interpreted as command (send to both chips), *all* following bytes are interleaved data, i. e. total number must be odd.  \nIf num_read !\u003d 0 then at most 5 bytes may be send (instr. and 0 to 4 address bytes, to both simultaneously), and num_read must be even.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":698,"context_line":"\t\t}"},{"line_number":699,"context_line":"\t}"},{"line_number":700,"context_line":""},{"line_number":701,"context_line":"\tif (((num_write \u003c 1) || (num_write \u003e 5)) \u0026\u0026 (num_read \u003e 0)) {"},{"line_number":702,"context_line":"\t\tLOG_ERROR(\"one cmd and up to four addr bytes must be send when reading\");"},{"line_number":703,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":704,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_57859459","line":701,"updated":"2018-10-14 22:56:00.000000000","message":"The num_write\u003c1 case is already checked by the CMD_ARGC\u003c3 check at the top.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":698,"context_line":"\t\t}"},{"line_number":699,"context_line":"\t}"},{"line_number":700,"context_line":""},{"line_number":701,"context_line":"\tif (((num_write \u003c 1) || (num_write \u003e 5)) \u0026\u0026 (num_read \u003e 0)) {"},{"line_number":702,"context_line":"\t\tLOG_ERROR(\"one cmd and up to four addr bytes must be send when reading\");"},{"line_number":703,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":704,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_869f6bb9","line":701,"in_reply_to":"6e936f18_57859459","updated":"2018-11-02 19:20:01.000000000","message":"Kept, but instead CMD_ARGC\u003c2, to get a more helpful error message here.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":737,"context_line":"\t\t/* send additional data bytes */"},{"line_number":738,"context_line":"\t\tfor (count \u003d 3; count \u003c CMD_ARGC; count++) {"},{"line_number":739,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);"},{"line_number":740,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":741,"context_line":"\t\t\tretval \u003d target_write_u8(target, io_base + SPI_DR, data); \\"},{"line_number":742,"context_line":""},{"line_number":743,"context_line":"\t\t\t/* on stm32h743, target_write_u8 returns ERROR_FAIL, even if the"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f79940c9","line":740,"updated":"2018-10-14 22:56:00.000000000","message":"data is a uint8_t, so I think the x should be a PRIx8.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":737,"context_line":"\t\t/* send additional data bytes */"},{"line_number":738,"context_line":"\t\tfor (count \u003d 3; count \u003c CMD_ARGC; count++) {"},{"line_number":739,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);"},{"line_number":740,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":741,"context_line":"\t\t\tretval \u003d target_write_u8(target, io_base + SPI_DR, data); \\"},{"line_number":742,"context_line":""},{"line_number":743,"context_line":"\t\t\t/* on stm32h743, target_write_u8 returns ERROR_FAIL, even if the"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_66aedfe6","line":740,"in_reply_to":"6e936f18_f79940c9","updated":"2018-11-02 19:20:01.000000000","message":"changed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4e50c53ea665c75dfeab266362f9cb8f7a1f53a8","unresolved":false,"context_lines":[{"line_number":741,"context_line":"\t\t\tretval \u003d target_write_u8(target, io_base + SPI_DR, data); \\"},{"line_number":742,"context_line":""},{"line_number":743,"context_line":"\t\t\t/* on stm32h743, target_write_u8 returns ERROR_FAIL, even if the"},{"line_number":744,"context_line":"\t\t\t * write was successful ... to be dropped when 4368 is merged */"},{"line_number":745,"context_line":"\t\t\tif (retval \u003d\u003d ERROR_FAIL)"},{"line_number":746,"context_line":"\t\t\t\tretval \u003d ERROR_OK;"},{"line_number":747,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"0e83d3c5_2510d8ac","line":744,"range":{"start_line":744,"start_character":50,"end_line":744,"end_character":64},"updated":"2018-02-03 15:42:22.000000000","message":"Done :-)","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":755,"context_line":"\t\taddr \u003d 0;"},{"line_number":756,"context_line":"\t\tfor (count \u003d 3; count \u003c CMD_ARGC; count++) {"},{"line_number":757,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);"},{"line_number":758,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":759,"context_line":"\t\t\taddr \u003d (addr \u003c\u003c 8) | data;"},{"line_number":760,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":761,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_17970c95","line":758,"updated":"2018-10-14 22:56:00.000000000","message":"Same comment regarding PRIx8.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":755,"context_line":"\t\taddr \u003d 0;"},{"line_number":756,"context_line":"\t\tfor (count \u003d 3; count \u003c CMD_ARGC; count++) {"},{"line_number":757,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);"},{"line_number":758,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":759,"context_line":"\t\t\taddr \u003d (addr \u003c\u003c 8) | data;"},{"line_number":760,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":761,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_06b35b4d","line":758,"in_reply_to":"6e936f18_17970c95","updated":"2018-11-02 19:20:01.000000000","message":"done","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":789,"context_line":"\t\t\tretval \u003d target_read_u8(target, io_base + SPI_DR, \u0026data);"},{"line_number":790,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":791,"context_line":"\t\t\t\tgoto err;"},{"line_number":792,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":793,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":794,"context_line":"\t\t}"},{"line_number":795,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_37f7a8f4","line":792,"updated":"2018-10-14 22:56:00.000000000","message":"Same comment regarding PRIx8.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":789,"context_line":"\t\t\tretval \u003d target_read_u8(target, io_base + SPI_DR, \u0026data);"},{"line_number":790,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":791,"context_line":"\t\t\t\tgoto err;"},{"line_number":792,"context_line":"\t\t\tsnprintf(temp, sizeof(temp), \"%02x \", data);"},{"line_number":793,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":794,"context_line":"\t\t}"},{"line_number":795,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_26b0d73d","line":792,"in_reply_to":"6e936f18_37f7a8f4","updated":"2018-11-02 19:20:01.000000000","message":"done","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":870,"context_line":"\tretval \u003d wait_till_ready(bank, SPI_MAX_TIMEOUT);"},{"line_number":871,"context_line":""},{"line_number":872,"context_line":"\t/* Erase takes a long time, so some sort of progress message is a good idea */"},{"line_number":873,"context_line":"\tLOG_DEBUG(\"sector %4d erased\", sector);"},{"line_number":874,"context_line":""},{"line_number":875,"context_line":"err:"},{"line_number":876,"context_line":"\t/* Switch to memory mapped mode before return to prompt */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f7e06027","line":873,"updated":"2018-10-14 22:56:00.000000000","message":"If wait_till_ready returns an error, maybe this message is wrong and should not be printed?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":870,"context_line":"\tretval \u003d wait_till_ready(bank, SPI_MAX_TIMEOUT);"},{"line_number":871,"context_line":""},{"line_number":872,"context_line":"\t/* Erase takes a long time, so some sort of progress message is a good idea */"},{"line_number":873,"context_line":"\tLOG_DEBUG(\"sector %4d erased\", sector);"},{"line_number":874,"context_line":""},{"line_number":875,"context_line":"err:"},{"line_number":876,"context_line":"\t/* Switch to memory mapped mode before return to prompt */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_4653a31a","line":873,"in_reply_to":"6e936f18_f7e06027","updated":"2018-11-02 19:20:01.000000000","message":"Moved before wait... and changed to \u0027erasING\u0027","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":879,"context_line":"\treturn retval;"},{"line_number":880,"context_line":"}"},{"line_number":881,"context_line":""},{"line_number":882,"context_line":"static int stmqspi_erase(struct flash_bank *bank, int first, int last)"},{"line_number":883,"context_line":"{"},{"line_number":884,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":885,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_17de2c71","line":882,"updated":"2018-10-14 22:56:00.000000000","message":"If first and last represent the entire bank, and the command is available, you could use a mass erase, which is probably faster than erasing by sectors. That way the normal erasing machinery would use the most efficient tool available, given which sectors it is asked to erase, rather than having to introduce a special command to do a mass erase.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":879,"context_line":"\treturn retval;"},{"line_number":880,"context_line":"}"},{"line_number":881,"context_line":""},{"line_number":882,"context_line":"static int stmqspi_erase(struct flash_bank *bank, int first, int last)"},{"line_number":883,"context_line":"{"},{"line_number":884,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":885,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_c62fb384","line":882,"in_reply_to":"6e936f18_17de2c71","updated":"2018-11-02 19:20:01.000000000","message":"If only part of flash is already used and needs to be erased, it\u0027s sometimes still much faster to do a mass erase. A write_image with erase would erase only the sectors to be touched. Therefore it\u0027s useful to have a separate mass_erase command anyway. And I think the commands should do exactly what their names suggest.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":911,"context_line":"\tfor (sector \u003d first; sector \u003c\u003d last; sector++) {"},{"line_number":912,"context_line":"\t\tif (bank-\u003esectors[sector].is_protected) {"},{"line_number":913,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":914,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":915,"context_line":"\t\t}"},{"line_number":916,"context_line":"\t}"},{"line_number":917,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b7ead803","line":914,"updated":"2018-10-14 22:56:00.000000000","message":"ERROR_FLASH_PROTECTED?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":911,"context_line":"\tfor (sector \u003d first; sector \u003c\u003d last; sector++) {"},{"line_number":912,"context_line":"\t\tif (bank-\u003esectors[sector].is_protected) {"},{"line_number":913,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":914,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":915,"context_line":"\t\t}"},{"line_number":916,"context_line":"\t}"},{"line_number":917,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_86ed2b25","line":914,"in_reply_to":"6e936f18_b7ead803","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":928,"context_line":"\treturn retval;"},{"line_number":929,"context_line":"}"},{"line_number":930,"context_line":""},{"line_number":931,"context_line":"static int stmqspi_protect(struct flash_bank *bank, int set,"},{"line_number":932,"context_line":"\tint first, int last)"},{"line_number":933,"context_line":"{"},{"line_number":934,"context_line":"\tint sector;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_d7e7643a","line":931,"updated":"2018-10-14 22:56:00.000000000","message":"Lots of Flash chips have hardware write protection capabilities. I think it would be misleading to support the protect command, but have it not actually do anything to the chip. I think either it should not be possible to protect sectors at all, or else the protection bits should be fully used (i.e. read during probe, write in this function, etc.).","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"37e8dc0a8b0b919753c07ae63a2d1ec640f0bf6d","unresolved":false,"context_lines":[{"line_number":928,"context_line":"\treturn retval;"},{"line_number":929,"context_line":"}"},{"line_number":930,"context_line":""},{"line_number":931,"context_line":"static int stmqspi_protect(struct flash_bank *bank, int set,"},{"line_number":932,"context_line":"\tint first, int last)"},{"line_number":933,"context_line":"{"},{"line_number":934,"context_line":"\tint sector;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_465e437d","line":931,"in_reply_to":"6e936f18_a64e2771","updated":"2018-11-14 20:56:01.000000000","message":"Meh. I’m still mildly opposed to having the protect command set implemented but not actually do anything (at the hardware level); to me it seems misleading (“But I ran the protect command and it worked! Why isn’t my chip write protected‽”) and I would think it makes more sense to just not include the feature at all. But, it’s not up to me; I defer to the OpenOCD maintainers to decide which way they want it.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":928,"context_line":"\treturn retval;"},{"line_number":929,"context_line":"}"},{"line_number":930,"context_line":""},{"line_number":931,"context_line":"static int stmqspi_protect(struct flash_bank *bank, int set,"},{"line_number":932,"context_line":"\tint first, int last)"},{"line_number":933,"context_line":"{"},{"line_number":934,"context_line":"\tint sector;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a64e2771","line":931,"in_reply_to":"6e936f18_d7e7643a","updated":"2018-11-02 19:20:01.000000000","message":"To deal with the hardware protection would be a real mess, too vendor/chip specific. Some have even OTP protection. That\u0027s far beyond scope. This is simply a \u0027soft\u0027 protection to prevent accidental modification. Clarified in docs.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":955,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32,"},{"line_number":956,"context_line":"\t\t__func__, offset, count);"},{"line_number":957,"context_line":""},{"line_number":958,"context_line":"\t/* see contrib/loaders/flash/stmqspi_write.S for src */"},{"line_number":959,"context_line":"\tstatic const uint8_t stmqspi_write_code[] \u003d {"},{"line_number":960,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc\""},{"line_number":961,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_77d4504c","line":958,"range":{"start_line":958,"start_character":8,"end_line":958,"end_character":45},"updated":"2018-10-14 22:56:00.000000000","message":"Actually “contrib/loaders/flash/stmqspi/stmqspi_write.S”.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":955,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32,"},{"line_number":956,"context_line":"\t\t__func__, offset, count);"},{"line_number":957,"context_line":""},{"line_number":958,"context_line":"\t/* see contrib/loaders/flash/stmqspi_write.S for src */"},{"line_number":959,"context_line":"\tstatic const uint8_t stmqspi_write_code[] \u003d {"},{"line_number":960,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc\""},{"line_number":961,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_66857f5a","line":958,"range":{"start_line":958,"start_character":8,"end_line":958,"end_character":45},"in_reply_to":"6e936f18_77d4504c","updated":"2018-11-02 19:20:01.000000000","message":"changed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":960,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc\""},{"line_number":961,"context_line":"\t};"},{"line_number":962,"context_line":""},{"line_number":963,"context_line":"\t/* see contrib/loaders/flash/stmoctospi_write.S for src */"},{"line_number":964,"context_line":"\tstatic const uint8_t stmoctospi_write_code[] \u003d {"},{"line_number":965,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmoctospi_write.inc\""},{"line_number":966,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_97d9dc85","line":963,"range":{"start_line":963,"start_character":8,"end_line":963,"end_character":48},"updated":"2018-10-14 22:56:00.000000000","message":"Actually “contrib/loaders/flash/stmqspi/stmoctospi_write.S”.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":960,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc\""},{"line_number":961,"context_line":"\t};"},{"line_number":962,"context_line":""},{"line_number":963,"context_line":"\t/* see contrib/loaders/flash/stmoctospi_write.S for src */"},{"line_number":964,"context_line":"\tstatic const uint8_t stmoctospi_write_code[] \u003d {"},{"line_number":965,"context_line":"#include \"../../../contrib/loaders/flash/stmqspi/stmoctospi_write.inc\""},{"line_number":966,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_069a7bbd","line":963,"range":{"start_line":963,"start_character":8,"end_line":963,"end_character":48},"in_reply_to":"6e936f18_97d9dc85","updated":"2018-11-02 19:20:01.000000000","message":"changed","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":996,"context_line":"\t\twrite_code_size \u003d sizeof(stmqspi_write_code);"},{"line_number":997,"context_line":"\t}"},{"line_number":998,"context_line":""},{"line_number":999,"context_line":"\t/* memory buffer, we assume sectorsize to be a power of 2 times page_size */"},{"line_number":1000,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1001,"context_line":"\tpage_size \u003d stmqspi_info-\u003edev.pagesize \u003c\u003c dual;"},{"line_number":1002,"context_line":"\tfifo_size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_37cec8ba","line":999,"range":{"start_line":999,"start_character":19,"end_line":999,"end_character":74},"updated":"2018-10-14 22:56:00.000000000","message":"In stmqspi_handle_setparms you verify that sector size and page size are both powers of two, and that they are no larger than the chip size, but you do not check that sector size ≥ page size. So this assumption could be wrong: page size could be greater than sector size.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":996,"context_line":"\t\twrite_code_size \u003d sizeof(stmqspi_write_code);"},{"line_number":997,"context_line":"\t}"},{"line_number":998,"context_line":""},{"line_number":999,"context_line":"\t/* memory buffer, we assume sectorsize to be a power of 2 times page_size */"},{"line_number":1000,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1001,"context_line":"\tpage_size \u003d stmqspi_info-\u003edev.pagesize \u003c\u003c dual;"},{"line_number":1002,"context_line":"\tfifo_size \u003d stmqspi_info-\u003edev.sectorsize \u003c\u003c dual;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a6f2a701","line":999,"range":{"start_line":999,"start_character":19,"end_line":999,"end_character":74},"in_reply_to":"6e936f18_37cec8ba","updated":"2018-11-02 19:20:01.000000000","message":"check for pagesize \u003c\u003d sectorsize added","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1096,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1097,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1098,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1099,"context_line":"\tint retval, sector, dual, octal_dtr;"},{"line_number":1100,"context_line":""},{"line_number":1101,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"},{"line_number":1102,"context_line":"\t\t__func__, offset, count);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_17c5cc90","line":1099,"range":{"start_line":1099,"start_character":27,"end_line":1099,"end_character":36},"updated":"2018-10-14 22:56:00.000000000","message":"I think octal_dtr could be a bool.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1096,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1097,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1098,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1099,"context_line":"\tint retval, sector, dual, octal_dtr;"},{"line_number":1100,"context_line":""},{"line_number":1101,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"},{"line_number":1102,"context_line":"\t\t__func__, offset, count);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_e6150f42","line":1099,"range":{"start_line":1099,"start_character":27,"end_line":1099,"end_character":36},"in_reply_to":"6e936f18_17c5cc90","updated":"2018-11-02 19:20:01.000000000","message":"Yes, but it should be consistent with \u0027dual\u0027. And at other places \u0027dual\u0027 is used as a shift count.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1119,"context_line":"\t\t\t\u0026\u0026 ((offset + count - 1) \u003e\u003d bank-\u003esectors[sector].offset)"},{"line_number":1120,"context_line":"\t\t\t\u0026\u0026 bank-\u003esectors[sector].is_protected) {"},{"line_number":1121,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":1122,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1123,"context_line":"\t\t}"},{"line_number":1124,"context_line":"\t}"},{"line_number":1125,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f7c70099","line":1122,"range":{"start_line":1122,"start_character":10,"end_line":1122,"end_character":20},"updated":"2018-10-14 22:56:00.000000000","message":"ERROR_FLASH_PROTECTED?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1119,"context_line":"\t\t\t\u0026\u0026 ((offset + count - 1) \u003e\u003d bank-\u003esectors[sector].offset)"},{"line_number":1120,"context_line":"\t\t\t\u0026\u0026 bank-\u003esectors[sector].is_protected) {"},{"line_number":1121,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":1122,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1123,"context_line":"\t\t}"},{"line_number":1124,"context_line":"\t}"},{"line_number":1125,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_26977795","line":1122,"range":{"start_line":1122,"start_character":10,"end_line":1122,"end_character":20},"in_reply_to":"6e936f18_f7c70099","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1125,"context_line":""},{"line_number":1126,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1127,"context_line":"\toctal_dtr \u003d IS_OCTOSPI \u0026\u0026 (stmqspi_info-\u003esaved_ccr \u0026 (1\u003c\u003cOCTOSPI_DDTR));"},{"line_number":1128,"context_line":"\tif ((dual || octal_dtr) \u0026 ((offset \u0026 1) !\u003d 0 || (count \u0026 1) !\u003d 0)) {"},{"line_number":1129,"context_line":"\t\tLOG_ERROR(\"In dual-QSPI and octal-DTR modes writes must be two byte aligned: \""},{"line_number":1130,"context_line":"\t\t\t\"%s: address\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32, __func__, offset, count);"},{"line_number":1131,"context_line":"\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b7c17885","line":1128,"range":{"start_line":1128,"start_character":25,"end_line":1128,"end_character":26},"updated":"2018-10-14 22:56:00.000000000","message":"I think this outermost \u0026 should be \u0026\u0026.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1125,"context_line":""},{"line_number":1126,"context_line":"\tdual \u003d (stmqspi_info-\u003esaved_cr \u0026 (1\u003c\u003cSPI_DUAL_FLASH)) ? 1 : 0;"},{"line_number":1127,"context_line":"\toctal_dtr \u003d IS_OCTOSPI \u0026\u0026 (stmqspi_info-\u003esaved_ccr \u0026 (1\u003c\u003cOCTOSPI_DDTR));"},{"line_number":1128,"context_line":"\tif ((dual || octal_dtr) \u0026 ((offset \u0026 1) !\u003d 0 || (count \u0026 1) !\u003d 0)) {"},{"line_number":1129,"context_line":"\t\tLOG_ERROR(\"In dual-QSPI and octal-DTR modes writes must be two byte aligned: \""},{"line_number":1130,"context_line":"\t\t\t\"%s: address\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32, __func__, offset, count);"},{"line_number":1131,"context_line":"\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b2098636","line":1128,"range":{"start_line":1128,"start_character":25,"end_line":1128,"end_character":26},"in_reply_to":"6e936f18_b7c17885","updated":"2018-11-02 19:20:01.000000000","message":"Indeed.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1128,"context_line":"\tif ((dual || octal_dtr) \u0026 ((offset \u0026 1) !\u003d 0 || (count \u0026 1) !\u003d 0)) {"},{"line_number":1129,"context_line":"\t\tLOG_ERROR(\"In dual-QSPI and octal-DTR modes writes must be two byte aligned: \""},{"line_number":1130,"context_line":"\t\t\t\"%s: address\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32, __func__, offset, count);"},{"line_number":1131,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1132,"context_line":"\t}"},{"line_number":1133,"context_line":""},{"line_number":1134,"context_line":"\t/* Abort any previous operation */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_d7be84fa","line":1131,"range":{"start_line":1131,"start_character":9,"end_line":1131,"end_character":19},"updated":"2018-10-14 22:56:00.000000000","message":"ERROR_FLASH_DST_BREAKS_ALIGNMENT?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1128,"context_line":"\tif ((dual || octal_dtr) \u0026 ((offset \u0026 1) !\u003d 0 || (count \u0026 1) !\u003d 0)) {"},{"line_number":1129,"context_line":"\t\tLOG_ERROR(\"In dual-QSPI and octal-DTR modes writes must be two byte aligned: \""},{"line_number":1130,"context_line":"\t\t\t\"%s: address\u003d0x%08\" PRIx32 \" len\u003d0x%08\" PRIx32, __func__, offset, count);"},{"line_number":1131,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1132,"context_line":"\t}"},{"line_number":1133,"context_line":""},{"line_number":1134,"context_line":"\t/* Abort any previous operation */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_666fbfc1","line":1131,"range":{"start_line":1131,"start_character":9,"end_line":1131,"end_character":19},"in_reply_to":"6e936f18_d7be84fa","updated":"2018-11-02 19:20:01.000000000","message":"ok","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1146,"context_line":"}"},{"line_number":1147,"context_line":""},{"line_number":1148,"context_line":"/* Return ID of flash device(s) */"},{"line_number":1149,"context_line":"/* On exit, indirect mode is kept */"},{"line_number":1150,"context_line":"static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)"},{"line_number":1151,"context_line":"{"},{"line_number":1152,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_7733f0c0","line":1149,"updated":"2018-10-14 22:56:00.000000000","message":"No it isn’t. You call set_mm_mode at the bottom.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1146,"context_line":"}"},{"line_number":1147,"context_line":""},{"line_number":1148,"context_line":"/* Return ID of flash device(s) */"},{"line_number":1149,"context_line":"/* On exit, indirect mode is kept */"},{"line_number":1150,"context_line":"static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)"},{"line_number":1151,"context_line":"{"},{"line_number":1152,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_a62707b1","line":1149,"in_reply_to":"6e936f18_7733f0c0","updated":"2018-11-02 19:20:01.000000000","message":"Correct.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1147,"context_line":""},{"line_number":1148,"context_line":"/* Return ID of flash device(s) */"},{"line_number":1149,"context_line":"/* On exit, indirect mode is kept */"},{"line_number":1150,"context_line":"static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)"},{"line_number":1151,"context_line":"{"},{"line_number":1152,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1153,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_9738fc9c","line":1150,"updated":"2018-10-14 22:56:00.000000000","message":"I think it would make sense for this function to set *id1 and *id2 to zero before starting to do work. That way they are just normal out-parameters, instead of the caller having to clear them before calling this function.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1147,"context_line":""},{"line_number":1148,"context_line":"/* Return ID of flash device(s) */"},{"line_number":1149,"context_line":"/* On exit, indirect mode is kept */"},{"line_number":1150,"context_line":"static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)"},{"line_number":1151,"context_line":"{"},{"line_number":1152,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1153,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_46f723f3","line":1150,"in_reply_to":"6e936f18_9738fc9c","updated":"2018-11-02 19:20:01.000000000","message":"done, but still setting them to zero in the caller to prevent compiler from complaining","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1295,"context_line":""},{"line_number":1296,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"},{"line_number":1297,"context_line":"\tretval \u003d read_flash_id(bank, \u0026id1, \u0026id2);"},{"line_number":1298,"context_line":"\tset_mm_mode(bank);"},{"line_number":1299,"context_line":"\tLOG_DEBUG(\"id1 0x%06\" PRIx32 \", id2 0x%06\" PRIx32, id1, id2);"},{"line_number":1300,"context_line":""},{"line_number":1301,"context_line":"\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_373d688b","line":1298,"updated":"2018-10-14 22:56:00.000000000","message":"read_flash_id calls set_mm_mode before returning, so this is not necessary.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1295,"context_line":""},{"line_number":1296,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"},{"line_number":1297,"context_line":"\tretval \u003d read_flash_id(bank, \u0026id1, \u0026id2);"},{"line_number":1298,"context_line":"\tset_mm_mode(bank);"},{"line_number":1299,"context_line":"\tLOG_DEBUG(\"id1 0x%06\" PRIx32 \", id2 0x%06\" PRIx32, id1, id2);"},{"line_number":1300,"context_line":""},{"line_number":1301,"context_line":"\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_8670cba4","line":1298,"in_reply_to":"6e936f18_373d688b","updated":"2018-11-02 19:20:01.000000000","message":"dropped","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1329,"context_line":"\t\t\t\t\t(stmqspi_info-\u003edev.sectorsize !\u003d p-\u003esectorsize) ||"},{"line_number":1330,"context_line":"\t\t\t\t\t(stmqspi_info-\u003edev.size_in_bytes !\u003d p-\u003esize_in_bytes)) {"},{"line_number":1331,"context_line":"\t\t\t\t\tLOG_WARNING(\"Incompatible flash1/flash2 devices\");"},{"line_number":1332,"context_line":"\t\t\t\t}"},{"line_number":1333,"context_line":"\t\t\tbreak;"},{"line_number":1334,"context_line":"\t\t}"},{"line_number":1335,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_f7462026","line":1332,"updated":"2018-10-14 22:56:00.000000000","message":"If you have two Flash chips of different types, but their commands and page/sector/chip sizes are the same, then there will be no warning, but only the first device name will be shown. Is this a problem?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1329,"context_line":"\t\t\t\t\t(stmqspi_info-\u003edev.sectorsize !\u003d p-\u003esectorsize) ||"},{"line_number":1330,"context_line":"\t\t\t\t\t(stmqspi_info-\u003edev.size_in_bytes !\u003d p-\u003esize_in_bytes)) {"},{"line_number":1331,"context_line":"\t\t\t\t\tLOG_WARNING(\"Incompatible flash1/flash2 devices\");"},{"line_number":1332,"context_line":"\t\t\t\t}"},{"line_number":1333,"context_line":"\t\t\tbreak;"},{"line_number":1334,"context_line":"\t\t}"},{"line_number":1335,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_263a17c1","line":1332,"in_reply_to":"6e936f18_f7462026","updated":"2018-11-02 19:20:01.000000000","message":"Both names are logged here unconditionally. But you\u0027re right, only one name is saved for later. However, I don\u0027t see any problem in that.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1344,"context_line":"\tfsize \u003d ((READ_REG(SPI_DCR)\u003e\u003eSPI_FSIZE_POS) \u0026 ((1U\u003c\u003cSPI_FSIZE_LEN) - 1));"},{"line_number":1345,"context_line":"\tLOG_DEBUG(\"FSIZE \u003d 0x%04x\", fsize);"},{"line_number":1346,"context_line":"\tif (bank-\u003esize !\u003d (1U\u003c\u003c(fsize + 1)))"},{"line_number":1347,"context_line":"\t\tLOG_WARNING(\"FSIZE field in QSPI_DCR(1) doesn\u0027t match actual capacity.\");"},{"line_number":1348,"context_line":""},{"line_number":1349,"context_line":"\tif (stmqspi_info-\u003edev.sectorsize !\u003d 0) {"},{"line_number":1350,"context_line":"\t\t/* create and fill sectors array */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_1744ec1b","line":1347,"updated":"2018-10-14 22:56:00.000000000","message":"What is “(1)” for?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1344,"context_line":"\tfsize \u003d ((READ_REG(SPI_DCR)\u003e\u003eSPI_FSIZE_POS) \u0026 ((1U\u003c\u003cSPI_FSIZE_LEN) - 1));"},{"line_number":1345,"context_line":"\tLOG_DEBUG(\"FSIZE \u003d 0x%04x\", fsize);"},{"line_number":1346,"context_line":"\tif (bank-\u003esize !\u003d (1U\u003c\u003c(fsize + 1)))"},{"line_number":1347,"context_line":"\t\tLOG_WARNING(\"FSIZE field in QSPI_DCR(1) doesn\u0027t match actual capacity.\");"},{"line_number":1348,"context_line":""},{"line_number":1349,"context_line":"\tif (stmqspi_info-\u003edev.sectorsize !\u003d 0) {"},{"line_number":1350,"context_line":"\t\t/* create and fill sectors array */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_d2069223","line":1347,"in_reply_to":"6e936f18_1744ec1b","updated":"2018-11-02 19:20:01.000000000","message":"As before.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1396,"context_line":"\t}"},{"line_number":1397,"context_line":""},{"line_number":1398,"context_line":"\tsnprintf(buf, buf_size, \"\\\u0027%s\\\u0027 %dkbytes id \u003d 0x%06\" PRIx32,"},{"line_number":1399,"context_line":"\t\tstmqspi_info-\u003edev.name, bank-\u003esize\u003e\u003e10, stmqspi_info-\u003edev.device_id);"},{"line_number":1400,"context_line":""},{"line_number":1401,"context_line":"\treturn ERROR_OK;"},{"line_number":1402,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_b75098da","line":1399,"updated":"2018-10-14 22:56:00.000000000","message":"bank-\u003esize is a uint32_t, so I think %\" PRIu32 \" would be appropriate, not %d.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1396,"context_line":"\t}"},{"line_number":1397,"context_line":""},{"line_number":1398,"context_line":"\tsnprintf(buf, buf_size, \"\\\u0027%s\\\u0027 %dkbytes id \u003d 0x%06\" PRIx32,"},{"line_number":1399,"context_line":"\t\tstmqspi_info-\u003edev.name, bank-\u003esize\u003e\u003e10, stmqspi_info-\u003edev.device_id);"},{"line_number":1400,"context_line":""},{"line_number":1401,"context_line":"\treturn ERROR_OK;"},{"line_number":1402,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_c6bc931d","line":1399,"in_reply_to":"6e936f18_b75098da","updated":"2018-11-02 19:20:01.000000000","message":"Hm, yes. Actually, across the various other flash drivers there is a huge variation: d lu ld PRIu32 PRId32","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":1410,"context_line":"\t\t.help \u003d \"Mass erase entire flash device.\","},{"line_number":1411,"context_line":"\t},"},{"line_number":1412,"context_line":"\t{"},{"line_number":1413,"context_line":"\t\t.name \u003d \"setparms\","},{"line_number":1414,"context_line":"\t\t.handler \u003d stmqspi_handle_setparms,"},{"line_number":1415,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":1416,"context_line":"\t\t.usage \u003d \"bank_id name chip_size page_size read_cmd pprg_cmd \""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_d74d2441","line":1413,"updated":"2018-10-14 22:56:00.000000000","message":"There are over a thousand instances of the word “params” in OpenOCD, but this is the only place where “parms” is used. Maybe this should be spelled “params” to be like the others?","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"1d2413116524de4c8fa156e74ccea7174430d450","unresolved":false,"context_lines":[{"line_number":1410,"context_line":"\t\t.help \u003d \"Mass erase entire flash device.\","},{"line_number":1411,"context_line":"\t},"},{"line_number":1412,"context_line":"\t{"},{"line_number":1413,"context_line":"\t\t.name \u003d \"setparms\","},{"line_number":1414,"context_line":"\t\t.handler \u003d stmqspi_handle_setparms,"},{"line_number":1415,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":1416,"context_line":"\t\t.usage \u003d \"bank_id name chip_size page_size read_cmd pprg_cmd \""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6e936f18_86fbeb10","line":1413,"in_reply_to":"6e936f18_d74d2441","updated":"2018-11-02 19:20:01.000000000","message":"Pure laziness, already shortened to just \u0027cmd\u0027.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":49,"context_line":""},{"line_number":50,"context_line":"#define READ_REG(a)\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":51,"context_line":"({\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":52,"context_line":"\tuint32_t __v;\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":53,"context_line":"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":54,"context_line":"\tretval \u003d target_read_u32(target, io_base + (a), \u0026__v);\t\\"},{"line_number":55,"context_line":"\t(retval \u003d\u003d ERROR_OK) ? __v : 0x0;\t\t\t\t\t\t\\"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1cce5dba","line":52,"updated":"2019-06-26 05:41:10.000000000","message":"According to ISO C, “All identifiers that begin with an underscore and either an uppercase letter or another underscore are always reserved for any use.” Could __v be renamed to something else?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":49,"context_line":""},{"line_number":50,"context_line":"#define READ_REG(a)\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":51,"context_line":"({\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":52,"context_line":"\tuint32_t __v;\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":53,"context_line":"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\"},{"line_number":54,"context_line":"\tretval \u003d target_read_u32(target, io_base + (a), \u0026__v);\t\\"},{"line_number":55,"context_line":"\t(retval \u003d\u003d ERROR_OK) ? __v : 0x0;\t\t\t\t\t\t\\"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1fe3afd5","line":52,"in_reply_to":"8e7fc396_1cce5dba","updated":"2019-07-23 20:46:58.000000000","message":"Renamed. As this was originally taken from src/flash/nor/stmsmi.c changed there, too.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":176,"context_line":"\tres.byte[3] \u003d (val\u003e\u003e24) \u0026 0xFF;"},{"line_number":177,"context_line":""},{"line_number":178,"context_line":"\treturn res.word;"},{"line_number":179,"context_line":"}"},{"line_number":180,"context_line":""},{"line_number":181,"context_line":"/* Timeout in ms */"},{"line_number":182,"context_line":"#define SPI_CMD_TIMEOUT\t\t\t(100)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9cc10d86","line":179,"updated":"2019-06-26 05:41:10.000000000","message":"This function (by a slightly different name and slightly different calling convention) already exists in src/helper/types.h. Even if you want to keep the return of a uint32_t rather than using a buffer pointer, how about making this function call h_u32_to_le instead of a reimplementation?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":176,"context_line":"\tres.byte[3] \u003d (val\u003e\u003e24) \u0026 0xFF;"},{"line_number":177,"context_line":""},{"line_number":178,"context_line":"\treturn res.word;"},{"line_number":179,"context_line":"}"},{"line_number":180,"context_line":""},{"line_number":181,"context_line":"/* Timeout in ms */"},{"line_number":182,"context_line":"#define SPI_CMD_TIMEOUT\t\t\t(100)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7fde6316","line":179,"in_reply_to":"8e7fc396_9cc10d86","updated":"2019-07-23 20:46:58.000000000","message":"Referring to h_u32_to_le now.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":196,"context_line":"\tbool octo;"},{"line_number":197,"context_line":"\tstruct flash_device dev;"},{"line_number":198,"context_line":"\tuint32_t io_base;"},{"line_number":199,"context_line":"\tuint32_t saved_cr;\t/* FSEL and DFM bit mask in QUADSPI_CR / OCTOSPI_CR */"},{"line_number":200,"context_line":"\tuint32_t saved_ccr;"},{"line_number":201,"context_line":"\tuint32_t saved_tcr;\t/* only for OCTOSPI */"},{"line_number":202,"context_line":"\tuint32_t saved_ir;\t/* only for OCTOSPI */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1c3dfd8a","line":199,"updated":"2019-06-26 05:41:10.000000000","message":"This is more than just those two bits. It also covers anything else needed to talk to the Flash properly (e.g. PRESCALER and SSHIFT would be important), and it also includes the EN bit, I think, doesn’t it? (this also applies to a comment in stmqspi_probe which says the same thing)","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":196,"context_line":"\tbool octo;"},{"line_number":197,"context_line":"\tstruct flash_device dev;"},{"line_number":198,"context_line":"\tuint32_t io_base;"},{"line_number":199,"context_line":"\tuint32_t saved_cr;\t/* FSEL and DFM bit mask in QUADSPI_CR / OCTOSPI_CR */"},{"line_number":200,"context_line":"\tuint32_t saved_ccr;"},{"line_number":201,"context_line":"\tuint32_t saved_tcr;\t/* only for OCTOSPI */"},{"line_number":202,"context_line":"\tuint32_t saved_ir;\t/* only for OCTOSPI */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5c7db5e3","line":199,"in_reply_to":"8e7fc396_1c3dfd8a","updated":"2019-07-23 20:46:58.000000000","message":"The name is descriptive enough, I think. The comment just emphasizes that FSEL and DFM are present in *BOTH* QUADSPI_CR and OCTOSPI_CR, and at the very same bit positions (whereas a lot of other bits are not at the same position in QUAD/OCTO case). Clarified.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":248,"context_line":"\t\t\t}"},{"line_number":249,"context_line":"\t\t\treturn retval;"},{"line_number":250,"context_line":"\t\t} else"},{"line_number":251,"context_line":"\t\t\tLOG_DEBUG(\"busy: 0x%08X\", READ_REG(SPI_SR));"},{"line_number":252,"context_line":"\t\talive_sleep(1);"},{"line_number":253,"context_line":"\t} while (timeval_ms() \u003c endtime);"},{"line_number":254,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3c423914","line":251,"updated":"2019-06-26 05:41:10.000000000","message":"This might print the word “busy” followed by a hex byte that does not include the BUSY flag, which would be confusing, because it does a second read. Better IMO to use a variable to store the original byte.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":248,"context_line":"\t\t\t}"},{"line_number":249,"context_line":"\t\t\treturn retval;"},{"line_number":250,"context_line":"\t\t} else"},{"line_number":251,"context_line":"\t\t\tLOG_DEBUG(\"busy: 0x%08X\", READ_REG(SPI_SR));"},{"line_number":252,"context_line":"\t\talive_sleep(1);"},{"line_number":253,"context_line":"\t} while (timeval_ms() \u003c endtime);"},{"line_number":254,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7c82f1ce","line":251,"in_reply_to":"8e7fc396_3c423914","updated":"2019-07-23 20:46:58.000000000","message":"Changed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":248,"context_line":"\t\t\t}"},{"line_number":249,"context_line":"\t\t\treturn retval;"},{"line_number":250,"context_line":"\t\t} else"},{"line_number":251,"context_line":"\t\t\tLOG_DEBUG(\"busy: 0x%08X\", READ_REG(SPI_SR));"},{"line_number":252,"context_line":"\t\talive_sleep(1);"},{"line_number":253,"context_line":"\t} while (timeval_ms() \u003c endtime);"},{"line_number":254,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3fa0eb3d","line":251,"in_reply_to":"8e7fc396_7c82f1ce","updated":"2019-07-29 19:35:48.000000000","message":"Cool. The format string should be \"busy: 0x%08\" PRIX32 since spi_sr is a uint32_t.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":271,"context_line":""},{"line_number":272,"context_line":"\t/* Abort any previous operation */"},{"line_number":273,"context_line":"\tretval \u003d target_write_u32(target, io_base + SPI_CR,"},{"line_number":274,"context_line":"\t\tREAD_REG(SPI_CR) | (1U\u003c\u003cSPI_ABORT));"},{"line_number":275,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":276,"context_line":"\t\treturn retval;"},{"line_number":277,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dc46a526","line":274,"updated":"2019-06-26 05:41:10.000000000","message":"If READ_REG fails, retval will be overwritten by the return value of target_write_u32 and the error might not get reported. There are many occurrences of this in this file, where READ_REG’s return value is passed to target_write_u32 and retval is overwritten; if changing this, please remember to change all the occurrences.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":271,"context_line":""},{"line_number":272,"context_line":"\t/* Abort any previous operation */"},{"line_number":273,"context_line":"\tretval \u003d target_write_u32(target, io_base + SPI_CR,"},{"line_number":274,"context_line":"\t\tREAD_REG(SPI_CR) | (1U\u003c\u003cSPI_ABORT));"},{"line_number":275,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":276,"context_line":"\t\treturn retval;"},{"line_number":277,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1c873dde","line":274,"in_reply_to":"8e7fc396_dc46a526","updated":"2019-07-23 20:46:58.000000000","message":"That\u0027s correct but intentional. The abort is intended as last resort after a serious failure, regardless of the contents of cr, so the only purpose is to set the ABORT bit, and only the successful setting of this bit is checked for. Another option would be to write saved_cr with ABORT bit set. I\u0027ll think about that.\n\nIf the read fails but the write succeeds, the required contents will be restored by the next operation.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":355,"context_line":"\t\t\tgoto err;"},{"line_number":356,"context_line":"\t\t*status |\u003d ((uint16_t) data) \u003c\u003c 8;"},{"line_number":357,"context_line":"\t}"},{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\tLOG_DEBUG(\"flash status regs: 0x%04\" PRIx16, *status);"},{"line_number":360,"context_line":""},{"line_number":361,"context_line":"err:"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c502ddb","line":358,"updated":"2019-06-26 05:41:10.000000000","message":"Should we have a workaround for STM32F74 erratum 2.4.1 (extra data written in the FIFO at the end of a quad DDR read transfer in indirect read with clock AHB/2) here? There are probably a few other places in this file where the same thing could happen—basically anywhere indirect read mode is used, AFAICT; we don’t know whether quad, DDR, or AHB/2 will be used in any particular case since that’s up to the config file, so we must assume any indirect read could potentially fall into that category.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":355,"context_line":"\t\t\tgoto err;"},{"line_number":356,"context_line":"\t\t*status |\u003d ((uint16_t) data) \u003c\u003c 8;"},{"line_number":357,"context_line":"\t}"},{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\tLOG_DEBUG(\"flash status regs: 0x%04\" PRIx16, *status);"},{"line_number":360,"context_line":""},{"line_number":361,"context_line":"err:"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dc70e509","line":358,"in_reply_to":"8e7fc396_9c502ddb","updated":"2019-07-23 20:46:58.000000000","message":"Not only for this particular erratum, but possibly others as well. That\u0027s why all (hopefully I got all occasions) operations start with abort.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":557,"context_line":"\t\t\tduration_kbps(\u0026bench, bank-\u003esize));"},{"line_number":558,"context_line":"\t} else {"},{"line_number":559,"context_line":"\t\tcommand_print(CMD, \"stmqspi mass erase failed after %fs\","},{"line_number":560,"context_line":"\t\t\tduration_elapsed(\u0026bench));"},{"line_number":561,"context_line":"\t}"},{"line_number":562,"context_line":""},{"line_number":563,"context_line":"err:"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5c5a95fa","line":560,"updated":"2019-06-26 05:41:10.000000000","message":"The only way to get here is if wait_till_ready returns an error (any other error case results in “goto err”). If that happens, it seems likely that the mass erase hasn’t actually failed (there is no way to communicate failure of the erase via SR1), but rather is still happening and you lost communication with the Flash. So I think this message could be improved.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":557,"context_line":"\t\t\tduration_kbps(\u0026bench, bank-\u003esize));"},{"line_number":558,"context_line":"\t} else {"},{"line_number":559,"context_line":"\t\tcommand_print(CMD, \"stmqspi mass erase failed after %fs\","},{"line_number":560,"context_line":"\t\t\tduration_elapsed(\u0026bench));"},{"line_number":561,"context_line":"\t}"},{"line_number":562,"context_line":""},{"line_number":563,"context_line":"err:"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fc54c158","line":560,"in_reply_to":"8e7fc396_5c5a95fa","updated":"2019-07-23 20:46:58.000000000","message":"Loss of communication is one possibility, the other is timeout exceeded. So \" ... not completed after ...\" might be more appropriate.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":571,"context_line":"{"},{"line_number":572,"context_line":"\tint result;"},{"line_number":573,"context_line":""},{"line_number":574,"context_line":"\tfor (result \u003d 0; (unsigned int) result \u003c sizeof(unsigned long) * 8; result++)"},{"line_number":575,"context_line":"\t\tif (word \u003d\u003d (1UL\u003c\u003cresult))"},{"line_number":576,"context_line":"\t\t\treturn result;"},{"line_number":577,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7c5f51e9","line":574,"range":{"start_line":574,"start_character":49,"end_line":574,"end_character":62},"updated":"2019-06-26 05:41:10.000000000","message":"uint32_t?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":571,"context_line":"{"},{"line_number":572,"context_line":"\tint result;"},{"line_number":573,"context_line":""},{"line_number":574,"context_line":"\tfor (result \u003d 0; (unsigned int) result \u003c sizeof(unsigned long) * 8; result++)"},{"line_number":575,"context_line":"\t\tif (word \u003d\u003d (1UL\u003c\u003cresult))"},{"line_number":576,"context_line":"\t\t\treturn result;"},{"line_number":577,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_df6d3798","line":574,"range":{"start_line":574,"start_character":49,"end_line":574,"end_character":62},"in_reply_to":"8e7fc396_7c5f51e9","updated":"2019-07-23 20:46:58.000000000","message":"Yes.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":590,"context_line":""},{"line_number":591,"context_line":"\tLOG_DEBUG(\"%s\", __func__);"},{"line_number":592,"context_line":""},{"line_number":593,"context_line":"\tif ((CMD_ARGC \u003c 6) || (CMD_ARGC \u003e 10))"},{"line_number":594,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":595,"context_line":""},{"line_number":596,"context_line":"\tretval \u003d CALL_COMMAND_HANDLER(flash_command_get_bank, 0, \u0026bank);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3c59d901","line":593,"range":{"start_line":593,"start_character":17,"end_line":593,"end_character":18},"updated":"2019-06-26 05:41:10.000000000","message":"Should this be 7? The minimum required parameters are bank_id, name, chip_size, page_size, read_cmd, qread_cmd, pprg_cmd, which are seven parameters.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":590,"context_line":""},{"line_number":591,"context_line":"\tLOG_DEBUG(\"%s\", __func__);"},{"line_number":592,"context_line":""},{"line_number":593,"context_line":"\tif ((CMD_ARGC \u003c 6) || (CMD_ARGC \u003e 10))"},{"line_number":594,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":595,"context_line":""},{"line_number":596,"context_line":"\tretval \u003d CALL_COMMAND_HANDLER(flash_command_get_bank, 0, \u0026bank);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_ff435313","line":593,"range":{"start_line":593,"start_character":17,"end_line":593,"end_character":18},"in_reply_to":"8e7fc396_3c59d901","updated":"2019-07-23 20:46:58.000000000","message":"Right, 7 to 10.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":606,"context_line":"\tbank-\u003esize \u003d 0;"},{"line_number":607,"context_line":"\tbank-\u003enum_sectors \u003d 0;"},{"line_number":608,"context_line":"\tbank-\u003esectors \u003d NULL;"},{"line_number":609,"context_line":"\tstmqspi_info-\u003eprobed \u003d 0;"},{"line_number":610,"context_line":"\tmemset(\u0026stmqspi_info-\u003edev, 0, sizeof(stmqspi_info-\u003edev));"},{"line_number":611,"context_line":"\tstmqspi_info-\u003edev.name \u003d \"unknown\";"},{"line_number":612,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1c541dc9","line":609,"range":{"start_line":609,"start_character":24,"end_line":609,"end_character":25},"updated":"2019-06-26 05:41:10.000000000","message":"false","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":606,"context_line":"\tbank-\u003esize \u003d 0;"},{"line_number":607,"context_line":"\tbank-\u003enum_sectors \u003d 0;"},{"line_number":608,"context_line":"\tbank-\u003esectors \u003d NULL;"},{"line_number":609,"context_line":"\tstmqspi_info-\u003eprobed \u003d 0;"},{"line_number":610,"context_line":"\tmemset(\u0026stmqspi_info-\u003edev, 0, sizeof(stmqspi_info-\u003edev));"},{"line_number":611,"context_line":"\tstmqspi_info-\u003edev.name \u003d \"unknown\";"},{"line_number":612,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fc6da12e","line":609,"range":{"start_line":609,"start_character":24,"end_line":609,"end_character":25},"in_reply_to":"8e7fc396_1c541dc9","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":783,"context_line":"\t\t\t}"},{"line_number":784,"context_line":"\t\t}"},{"line_number":785,"context_line":"\t} else {"},{"line_number":786,"context_line":"\t\t/* read mode, one command byte and up to for following address bytes */"},{"line_number":787,"context_line":"\t\tif (stmqspi_info-\u003esaved_cr \u0026 (1U\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":788,"context_line":"\t\t\tif ((num_read \u0026 1) !\u003d 0) {"},{"line_number":789,"context_line":"\t\t\t\tLOG_ERROR(\"number of bytes to read must be even in dual mode\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fc6a817d","line":786,"range":{"start_line":786,"start_character":43,"end_line":786,"end_character":46},"updated":"2019-06-26 05:41:10.000000000","message":"four","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":783,"context_line":"\t\t\t}"},{"line_number":784,"context_line":"\t\t}"},{"line_number":785,"context_line":"\t} else {"},{"line_number":786,"context_line":"\t\t/* read mode, one command byte and up to for following address bytes */"},{"line_number":787,"context_line":"\t\tif (stmqspi_info-\u003esaved_cr \u0026 (1U\u003c\u003cSPI_DUAL_FLASH)) {"},{"line_number":788,"context_line":"\t\t\tif ((num_read \u0026 1) !\u003d 0) {"},{"line_number":789,"context_line":"\t\t\t\tLOG_ERROR(\"number of bytes to read must be even in dual mode\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c7a6de6","line":786,"range":{"start_line":786,"start_character":43,"end_line":786,"end_character":46},"in_reply_to":"8e7fc396_fc6a817d","updated":"2019-07-23 20:46:58.000000000","message":"Right.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":881,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":882,"context_line":"\t\t}"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":"\tcommand_print(CMD, \"%s\", output);"},{"line_number":885,"context_line":""},{"line_number":886,"context_line":"err:"},{"line_number":887,"context_line":"\t/* Switch to memory mapped mode before return to prompt */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bc6409b0","line":884,"updated":"2019-06-26 05:41:10.000000000","message":"This function seems like it could be useful for scripting. Would it make any sense to provide a more machine-readable output (maybe that doesn’t include the written bytes and the arrow) and something else, perhaps a Tcl proc, for human consumption?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":881,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":882,"context_line":"\t\t}"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":"\tcommand_print(CMD, \"%s\", output);"},{"line_number":885,"context_line":""},{"line_number":886,"context_line":"err:"},{"line_number":887,"context_line":"\t/* Switch to memory mapped mode before return to prompt */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_df8457b8","line":884,"in_reply_to":"8e7fc396_9c510d68","updated":"2019-07-29 19:35:48.000000000","message":"Yes, I was thinking something like a script that’s used in a production setting during board bringup, which pokes a few registers in the Flash chip to get it into the mode that the firmware expects (e.g. quad-mode on or off, dummy cycle count, etc.). In that case the author of the script would know the exact model of microcontroller and the exact model of Flash chip.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":881,"context_line":"\t\t\tstrncat(output, temp, sizeof(output) - strlen(output) - 1);"},{"line_number":882,"context_line":"\t\t}"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":"\tcommand_print(CMD, \"%s\", output);"},{"line_number":885,"context_line":""},{"line_number":886,"context_line":"err:"},{"line_number":887,"context_line":"\t/* Switch to memory mapped mode before return to prompt */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c510d68","line":884,"in_reply_to":"8e7fc396_bc6409b0","updated":"2019-07-23 20:46:58.000000000","message":"Depends. It\u0027s mainly intended for configuration of the flash chips. The registers (except the status reg.) and settings are a complete chaos ... \nCommunication with the flash chip is easily lost if a setting is modified (e.g. from SPI to QPI), sometimes a power cycle of the flash is the most simple way to regain access.\n \nThat\u0027s all quite fragile, and any script doing this automatically must be tailored precisely to the chip and its original settings. And error recovery if something goes wrong ...","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1007,"context_line":"\t\t\treturn ERROR_FLASH_PROTECTED;"},{"line_number":1008,"context_line":"\t\t}"},{"line_number":1009,"context_line":"\t}"},{"line_number":1010,"context_line":""},{"line_number":1011,"context_line":"\tfor (sector \u003d first; sector \u003c\u003d last; sector++) {"},{"line_number":1012,"context_line":"\t\tretval \u003d qspi_erase_sector(bank, sector);"},{"line_number":1013,"context_line":"\t\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1c0bbdda","line":1010,"updated":"2019-06-26 05:41:10.000000000","message":"If first\u003d0 and last\u003dnum_sectors−1 and chip_erase_cmd≠0, should we do a chip erase instead? It’s functionally equivalent and probably faster than erasing all the sectors one by one, and “flash erase bank_id 0 last” is a nice standard way to erase all of a Flash regardless of what type.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1007,"context_line":"\t\t\treturn ERROR_FLASH_PROTECTED;"},{"line_number":1008,"context_line":"\t\t}"},{"line_number":1009,"context_line":"\t}"},{"line_number":1010,"context_line":""},{"line_number":1011,"context_line":"\tfor (sector \u003d first; sector \u003c\u003d last; sector++) {"},{"line_number":1012,"context_line":"\t\tretval \u003d qspi_erase_sector(bank, sector);"},{"line_number":1013,"context_line":"\t\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bc7729fd","line":1010,"in_reply_to":"8e7fc396_1c0bbdda","updated":"2019-07-23 20:46:58.000000000","message":"The command name should clearly say what it does. Even if this automatism is convenient, it breaks this rule.\n\nIndeed, the proper way would be a general \u0027flash mass_erase [bank_id]\u0027 command.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1025,"context_line":"\treturn retval;"},{"line_number":1026,"context_line":"}"},{"line_number":1027,"context_line":""},{"line_number":1028,"context_line":"static int stmqspi_protect(struct flash_bank *bank, int set,"},{"line_number":1029,"context_line":"\tint first, int last)"},{"line_number":1030,"context_line":"{"},{"line_number":1031,"context_line":"\tint sector;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3c10f903","line":1028,"updated":"2019-06-26 05:41:10.000000000","message":"Can this print a warning that the protection is software-only and doesn’t actually set any read-only bits in the chip?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1025,"context_line":"\treturn retval;"},{"line_number":1026,"context_line":"}"},{"line_number":1027,"context_line":""},{"line_number":1028,"context_line":"static int stmqspi_protect(struct flash_bank *bank, int set,"},{"line_number":1029,"context_line":"\tint first, int last)"},{"line_number":1030,"context_line":"{"},{"line_number":1031,"context_line":"\tint sector;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bc4e49c3","line":1028,"in_reply_to":"8e7fc396_3c10f903","updated":"2019-07-23 20:46:58.000000000","message":"That\u0027s already mentioned explicitly in the doc, but of course, an additional warning doesn\u0027t do any harm.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1045,"context_line":"\tstruct reg_param reg_params[2];"},{"line_number":1046,"context_line":"\tstruct armv7m_algorithm armv7m_info;"},{"line_number":1047,"context_line":"\tstruct working_area *algorithm;"},{"line_number":1048,"context_line":"\tstatic const uint8_t *code;"},{"line_number":1049,"context_line":"\tstruct sector_info erase_check_info;"},{"line_number":1050,"context_line":"\tuint32_t codesize, maxsize, result, exit_point;"},{"line_number":1051,"context_line":"\tint num_sectors, sector, index, count, retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fcf121db","line":1048,"updated":"2019-06-26 05:41:10.000000000","message":"There’s no need for this to be static.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1045,"context_line":"\tstruct reg_param reg_params[2];"},{"line_number":1046,"context_line":"\tstruct armv7m_algorithm armv7m_info;"},{"line_number":1047,"context_line":"\tstruct working_area *algorithm;"},{"line_number":1048,"context_line":"\tstatic const uint8_t *code;"},{"line_number":1049,"context_line":"\tstruct sector_info erase_check_info;"},{"line_number":1050,"context_line":"\tuint32_t codesize, maxsize, result, exit_point;"},{"line_number":1051,"context_line":"\tint num_sectors, sector, index, count, retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5c64d545","line":1048,"in_reply_to":"8e7fc396_fcf121db","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1106,"context_line":"\t};"},{"line_number":1107,"context_line":""},{"line_number":1108,"context_line":"\tmaxsize \u003d target_get_working_area_avail(target);"},{"line_number":1109,"context_line":"\tif (maxsize \u003c codesize + 2 * sizeof(erase_check_info)) {"},{"line_number":1110,"context_line":"\t\tLOG_ERROR(\"Not enough working area, can\u0027t do QSPI blank check\");"},{"line_number":1111,"context_line":"\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"},{"line_number":1112,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bcfba9b9","line":1109,"range":{"start_line":1109,"start_character":26,"end_line":1109,"end_character":27},"updated":"2019-06-26 05:41:10.000000000","message":"Why does this need to be 2? The algorithm could run on one sector at a time, in which case only one erase_check_info would be needed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1106,"context_line":"\t};"},{"line_number":1107,"context_line":""},{"line_number":1108,"context_line":"\tmaxsize \u003d target_get_working_area_avail(target);"},{"line_number":1109,"context_line":"\tif (maxsize \u003c codesize + 2 * sizeof(erase_check_info)) {"},{"line_number":1110,"context_line":"\t\tLOG_ERROR(\"Not enough working area, can\u0027t do QSPI blank check\");"},{"line_number":1111,"context_line":"\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"},{"line_number":1112,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_ff6a737d","line":1109,"range":{"start_line":1109,"start_character":26,"end_line":1109,"end_character":27},"in_reply_to":"8e7fc396_bcfba9b9","updated":"2019-07-23 20:46:58.000000000","message":"Indeed, the 2 is somewhat arbitrary. Even less than a factor of 16, say, would be quite exceptional. And write and read wouldn\u0027t work either with only that amount of working area. \nChanged to 1.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1173,"context_line":"\t\t\t0, NULL,"},{"line_number":1174,"context_line":"\t\t\t2, reg_params,"},{"line_number":1175,"context_line":"\t\t\talgorithm-\u003eaddress, exit_point,"},{"line_number":1176,"context_line":"\t\t\tcount * (bank-\u003esectors[sector].size \u003e\u003e 8),"},{"line_number":1177,"context_line":"\t\t\t\u0026armv7m_info);"},{"line_number":1178,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1179,"context_line":"\t\t\tbreak;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7c2d1141","line":1176,"updated":"2019-06-26 05:41:10.000000000","message":"This seems like an odd calculation for the timeout in milliseconds. For a small sector, and particularly for a low SPI clock rate, it would be a very short time. Wouldn’t it be better to make the timeout quite large? It’s only used in case of catastrophic failure, so making it a bit slower is a good tradeoff if it’s more robust.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1173,"context_line":"\t\t\t0, NULL,"},{"line_number":1174,"context_line":"\t\t\t2, reg_params,"},{"line_number":1175,"context_line":"\t\t\talgorithm-\u003eaddress, exit_point,"},{"line_number":1176,"context_line":"\t\t\tcount * (bank-\u003esectors[sector].size \u003e\u003e 8),"},{"line_number":1177,"context_line":"\t\t\t\u0026armv7m_info);"},{"line_number":1178,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1179,"context_line":"\t\t\tbreak;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9f67bfb4","line":1176,"in_reply_to":"8e7fc396_7c2d1141","updated":"2019-07-23 20:46:58.000000000","message":"Hm, yes, that\u0027s a relict from debugging where failure happened occasionally. But I\u0027ve no idea about a really good value as the SPI and CPU clock can be made arbitrarily slow.\nOn the other hand, why would one use extremely slow clocks? Just makes programming slow. The current code leaves approx. 4us per byte, so SPI clock well above 2 MHz will be sufficient. This is no problem even for older EEPROMs. For extremly small sectors the overhead for starting the algorithm etc. will be more significant, but additional 1ms per sector and 1s per block should be enough.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1252,"context_line":"\tif (pagesize \u003d\u003d 0)"},{"line_number":1253,"context_line":"\t\tpagesize \u003d stmqspi_info-\u003edev.pagesize;"},{"line_number":1254,"context_line":"\tif (pagesize \u003d\u003d 0)"},{"line_number":1255,"context_line":"\t\tpagesize \u003d SPIFLASH_DEF_PAGESIZE;"},{"line_number":1256,"context_line":""},{"line_number":1257,"context_line":"\t/* adjust size according to dual flash mode */"},{"line_number":1258,"context_line":"\tpagesize \u003d (stmqspi_info-\u003esaved_cr \u0026 (1U\u003c\u003cSPI_DUAL_FLASH)) ? pagesize \u003c\u003c 1 : pagesize;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3c279961","line":1255,"updated":"2019-06-26 05:41:10.000000000","message":"Why not just issue a single read command to the chip covering the entire image? That would simplify this function and also the algorithm code. This would also apply to qspi_read_write_block.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1252,"context_line":"\tif (pagesize \u003d\u003d 0)"},{"line_number":1253,"context_line":"\t\tpagesize \u003d stmqspi_info-\u003edev.pagesize;"},{"line_number":1254,"context_line":"\tif (pagesize \u003d\u003d 0)"},{"line_number":1255,"context_line":"\t\tpagesize \u003d SPIFLASH_DEF_PAGESIZE;"},{"line_number":1256,"context_line":""},{"line_number":1257,"context_line":"\t/* adjust size according to dual flash mode */"},{"line_number":1258,"context_line":"\tpagesize \u003d (stmqspi_info-\u003esaved_cr \u0026 (1U\u003c\u003cSPI_DUAL_FLASH)) ? pagesize \u003c\u003c 1 : pagesize;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7c69911c","line":1255,"in_reply_to":"8e7fc396_3c279961","updated":"2019-07-23 20:46:58.000000000","message":"1) simplifies implementation and maintenance: read etc. are just stripped-down versions of write\n2) predictable (and same behaviour as for write) result even if flash with more than 16MBytes doesn\u0027t support 4-byte addressing but segments via extended address register: a single continuous read would silently cross the segment boundary *without* updating this register whereas the \u0027page\u0027 based method will always stay in the segment set by this register. requires sectorsize \u003c\u003d 16 MBytes, of course\nBTW: similar problem in memory mapped mode: pure sequential accesses without large delays will keep CS active for continuous read crossing the segment boundary. timeout (if activated) or non-sequential access terminates the read, and a new command with new address must be issued. this will start in the \u0027old\u0027 segment again","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1450,"context_line":""},{"line_number":1451,"context_line":"\t/* fifo size at most sector size, and multiple of page size */"},{"line_number":1452,"context_line":"\tmaxsize -\u003d (codesize + 2 * sizeof(uint32_t));"},{"line_number":1453,"context_line":"\tfifosize \u003d ((maxsize \u003c fifosize) ? maxsize : fifosize) \u0026 ~(pagesize - 1);"},{"line_number":1454,"context_line":""},{"line_number":1455,"context_line":"\tif (target_alloc_working_area_try(target,"},{"line_number":1456,"context_line":"\t\tcodesize + 2 * sizeof(uint32_t) + fifosize, \u0026algorithm) !\u003d ERROR_OK) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9c158dec","line":1453,"updated":"2019-06-26 05:41:10.000000000","message":"This code is being really careful to allocate a FIFO that’s a multiple of the page size, but why? The algorithm code checks for FIFO wrapping after every byte, so it would work with a FIFO of any size.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1450,"context_line":""},{"line_number":1451,"context_line":"\t/* fifo size at most sector size, and multiple of page size */"},{"line_number":1452,"context_line":"\tmaxsize -\u003d (codesize + 2 * sizeof(uint32_t));"},{"line_number":1453,"context_line":"\tfifosize \u003d ((maxsize \u003c fifosize) ? maxsize : fifosize) \u0026 ~(pagesize - 1);"},{"line_number":1454,"context_line":""},{"line_number":1455,"context_line":"\tif (target_alloc_working_area_try(target,"},{"line_number":1456,"context_line":"\t\tcodesize + 2 * sizeof(uint32_t) + fifosize, \u0026algorithm) !\u003d ERROR_OK) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5cc3750a","line":1453,"in_reply_to":"8e7fc396_9c158dec","updated":"2019-07-23 20:46:58.000000000","message":"Yes, the \u0026 ~(pagesize -1) isn\u0027t necessary at all, the fifo should just be sized reasonanbly. But an \u0027even\u0027 size looks better and makes debugging easier for me - without using a calculator for address computations ...","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1556,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1557,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1558,"context_line":"\t}"},{"line_number":1559,"context_line":""},{"line_number":1560,"context_line":"\tif (offset + count \u003e bank-\u003esize) {"},{"line_number":1561,"context_line":"\t\tLOG_WARNING(\"Read beyond end of flash. Extra data to be ignored.\");"},{"line_number":1562,"context_line":"\t\tcount \u003d bank-\u003esize - offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5cd7f528","line":1559,"updated":"2019-06-26 05:41:10.000000000","message":"Should you check for probed here?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1556,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1557,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1558,"context_line":"\t}"},{"line_number":1559,"context_line":""},{"line_number":1560,"context_line":"\tif (offset + count \u003e bank-\u003esize) {"},{"line_number":1561,"context_line":"\t\tLOG_WARNING(\"Read beyond end of flash. Extra data to be ignored.\");"},{"line_number":1562,"context_line":"\t\tcount \u003d bank-\u003esize - offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9f501fdb","line":1559,"in_reply_to":"8e7fc396_5cd7f528","updated":"2019-07-23 20:46:58.000000000","message":"Yes.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1591,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1592,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1593,"context_line":"\t}"},{"line_number":1594,"context_line":""},{"line_number":1595,"context_line":"\tif (offset + count \u003e bank-\u003esize) {"},{"line_number":1596,"context_line":"\t\tLOG_WARNING(\"Write beyond end of flash. Extra data discarded.\");"},{"line_number":1597,"context_line":"\t\tcount \u003d bank-\u003esize - offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7cdc314c","line":1594,"updated":"2019-06-26 05:41:10.000000000","message":"Should you check for probed here?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1591,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1592,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1593,"context_line":"\t}"},{"line_number":1594,"context_line":""},{"line_number":1595,"context_line":"\tif (offset + count \u003e bank-\u003esize) {"},{"line_number":1596,"context_line":"\t\tLOG_WARNING(\"Write beyond end of flash. Extra data discarded.\");"},{"line_number":1597,"context_line":"\t\tcount \u003d bank-\u003esize - offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bf4ddb41","line":1594,"in_reply_to":"8e7fc396_7cdc314c","updated":"2019-07-23 20:46:58.000000000","message":"As above, yes.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1897,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1898,"context_line":"\tuint8_t byte;"},{"line_number":1899,"context_line":"\tint type, count, len1, len2, retval;"},{"line_number":1900,"context_line":"\tbool end;"},{"line_number":1901,"context_line":""},{"line_number":1902,"context_line":"\t/* invalidate both ids */"},{"line_number":1903,"context_line":"\t*id1 \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1cb89de1","line":1900,"range":{"start_line":1900,"start_character":6,"end_line":1900,"end_character":9},"updated":"2019-06-26 05:41:10.000000000","message":"This variable is only used to control loop iteration, but it is only set to true after the loop has already finished. It could be completely deleted.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1897,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1898,"context_line":"\tuint8_t byte;"},{"line_number":1899,"context_line":"\tint type, count, len1, len2, retval;"},{"line_number":1900,"context_line":"\tbool end;"},{"line_number":1901,"context_line":""},{"line_number":1902,"context_line":"\t/* invalidate both ids */"},{"line_number":1903,"context_line":"\t*id1 \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5f5a87fa","line":1900,"range":{"start_line":1900,"start_character":6,"end_line":1900,"end_character":9},"in_reply_to":"8e7fc396_1cb89de1","updated":"2019-07-23 20:46:58.000000000","message":"Right, deleted.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1903,"context_line":"\t*id1 \u003d 0;"},{"line_number":1904,"context_line":"\t*id2 \u003d 0;"},{"line_number":1905,"context_line":""},{"line_number":1906,"context_line":"\tif ((target-\u003estate !\u003d TARGET_HALTED) \u0026\u0026 (target-\u003estate !\u003d TARGET_RESET)) {"},{"line_number":1907,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1908,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1909,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dcea25d7","line":1906,"range":{"start_line":1906,"start_character":37,"end_line":1906,"end_character":72},"updated":"2019-06-26 05:41:10.000000000","message":"Does this code actually work with SRST asserted? I would imagine that, while the target is held in reset, the RCC module turns off the clocks to the QUADSPI.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1903,"context_line":"\t*id1 \u003d 0;"},{"line_number":1904,"context_line":"\t*id2 \u003d 0;"},{"line_number":1905,"context_line":""},{"line_number":1906,"context_line":"\tif ((target-\u003estate !\u003d TARGET_HALTED) \u0026\u0026 (target-\u003estate !\u003d TARGET_RESET)) {"},{"line_number":1907,"context_line":"\t\tLOG_ERROR(\"Target not halted\");"},{"line_number":1908,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":1909,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7cc8b125","line":1906,"range":{"start_line":1906,"start_character":37,"end_line":1906,"end_character":72},"in_reply_to":"8e7fc396_dcea25d7","updated":"2019-07-23 20:46:58.000000000","message":"Didn\u0027t really check, but most certainly no, right. Deleted.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1996,"context_line":"\t\tif ((*id1 \u003d\u003d 0x000000) || (*id1 \u003d\u003d 0xFFFFFF)) {"},{"line_number":1997,"context_line":"\t\t\t/* no id retrieved, so id must be set manually */"},{"line_number":1998,"context_line":"\t\t\tLOG_INFO(\"No id from flash1\");"},{"line_number":1999,"context_line":"\t\t\tretval \u003d ERROR_TARGET_NOT_EXAMINED;"},{"line_number":2000,"context_line":"\t\t} else"},{"line_number":2001,"context_line":"\t\t\tend \u003d true;"},{"line_number":2002,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bcc88978","line":1999,"range":{"start_line":1999,"start_character":12,"end_line":1999,"end_character":37},"updated":"2019-06-26 05:41:10.000000000","message":"I don’t think this is the best choice of return value (here or a few lines down for the other chip); this isn’t about the target being examined or not, in fact it has nothing to do with the target. See other thread about the same thing in SFDP.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1996,"context_line":"\t\tif ((*id1 \u003d\u003d 0x000000) || (*id1 \u003d\u003d 0xFFFFFF)) {"},{"line_number":1997,"context_line":"\t\t\t/* no id retrieved, so id must be set manually */"},{"line_number":1998,"context_line":"\t\t\tLOG_INFO(\"No id from flash1\");"},{"line_number":1999,"context_line":"\t\t\tretval \u003d ERROR_TARGET_NOT_EXAMINED;"},{"line_number":2000,"context_line":"\t\t} else"},{"line_number":2001,"context_line":"\t\t\tend \u003d true;"},{"line_number":2002,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1ccdfd34","line":1999,"range":{"start_line":1999,"start_character":12,"end_line":1999,"end_character":37},"in_reply_to":"8e7fc396_bcc88978","updated":"2019-07-23 20:46:58.000000000","message":"Changed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2051,"context_line":"\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, magic);"},{"line_number":2052,"context_line":"\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":2053,"context_line":"\t\tretval \u003d target_read_u32(target, io_base + QSPI_ABR, \u0026data);"},{"line_number":2054,"context_line":"\t\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, 0);"},{"line_number":2055,"context_line":"\t}"},{"line_number":2056,"context_line":""},{"line_number":2057,"context_line":"\tif (data \u003d\u003d magic) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3cbd59d2","line":2054,"updated":"2019-06-26 05:41:10.000000000","message":"retval is set here, but then completely ignored; given that the previous write succeeded, you know that ABR exists, so shouldn’t failures on subsequent accesses give up, print a message, and return failure?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2051,"context_line":"\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, magic);"},{"line_number":2052,"context_line":"\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":2053,"context_line":"\t\tretval \u003d target_read_u32(target, io_base + QSPI_ABR, \u0026data);"},{"line_number":2054,"context_line":"\t\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, 0);"},{"line_number":2055,"context_line":"\t}"},{"line_number":2056,"context_line":""},{"line_number":2057,"context_line":"\tif (data \u003d\u003d magic) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3cd239d6","line":2054,"in_reply_to":"8e7fc396_3cbd59d2","updated":"2019-07-23 20:46:58.000000000","message":"Unfortunately the write succeeds for the OctoSPI interface on L4R5, too, although the address is marked as reserved (the read succeeds too, and always returns 0x0). But I\u0027ve no idea whether this is intended behaviour. Same for the OCTOSPI_MAGIC register, this returns the correct id (indicating OctoSPI present) on G474, but this device has a QuadSPI, no OctoSPI. Both might change on future devices, so I think it\u0027s better not to rely on (non-) accessability of any of these two registers, but only on (in-) valid data in both registers.\n\nIf there\u0027s a communication problem, the accesses further down will most certainly fail anyway, so the risk of not detecting an error is quite limited.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":2051,"context_line":"\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, magic);"},{"line_number":2052,"context_line":"\tif (retval \u003d\u003d ERROR_OK) {"},{"line_number":2053,"context_line":"\t\tretval \u003d target_read_u32(target, io_base + QSPI_ABR, \u0026data);"},{"line_number":2054,"context_line":"\t\tretval \u003d target_write_u32(target, io_base + QSPI_ABR, 0);"},{"line_number":2055,"context_line":"\t}"},{"line_number":2056,"context_line":""},{"line_number":2057,"context_line":"\tif (data \u003d\u003d magic) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_ff8113a5","line":2054,"in_reply_to":"8e7fc396_3cd239d6","updated":"2019-07-29 19:35:48.000000000","message":"OK, that sounds fine. Perhaps omit the assignments to retval then, to make it clear that you didn’t intend to check for errors?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2103,"context_line":"\t\t\tLOG_DEBUG(\"QSPI at 0x%08\" PRIx64 \", io_base at 0x%08\" PRIx32 \", QSPI_CR 0x%08\""},{"line_number":2104,"context_line":"\t\t\t\tPRIx32 \", QSPI_CCR 0x%08\" PRIx32 \", %d-byte addr\", bank-\u003ebase, io_base,"},{"line_number":2105,"context_line":"\t\t\t\tstmqspi_info-\u003esaved_cr, stmqspi_info-\u003esaved_ccr, SPI_ADSIZE);"},{"line_number":2106,"context_line":"\t\t} else {"},{"line_number":2107,"context_line":"\t\t\tLOG_ERROR(\"No QSPI at io_base 0x%08\" PRIx32, io_base);"},{"line_number":2108,"context_line":"\t\t\tstmqspi_info-\u003eprobed \u003d false;"},{"line_number":2109,"context_line":"\t\t\tstmqspi_info-\u003edev.name \u003d \"none\";"},{"line_number":2110,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":2111,"context_line":"\t\t}"},{"line_number":2112,"context_line":"\t}"},{"line_number":2113,"context_line":""},{"line_number":2114,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fcce0186","line":2111,"range":{"start_line":2106,"start_character":4,"end_line":2111,"end_character":3},"updated":"2019-06-26 05:41:10.000000000","message":"This branch is never taken; retval is already checked after the read of CCR.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2103,"context_line":"\t\t\tLOG_DEBUG(\"QSPI at 0x%08\" PRIx64 \", io_base at 0x%08\" PRIx32 \", QSPI_CR 0x%08\""},{"line_number":2104,"context_line":"\t\t\t\tPRIx32 \", QSPI_CCR 0x%08\" PRIx32 \", %d-byte addr\", bank-\u003ebase, io_base,"},{"line_number":2105,"context_line":"\t\t\t\tstmqspi_info-\u003esaved_cr, stmqspi_info-\u003esaved_ccr, SPI_ADSIZE);"},{"line_number":2106,"context_line":"\t\t} else {"},{"line_number":2107,"context_line":"\t\t\tLOG_ERROR(\"No QSPI at io_base 0x%08\" PRIx32, io_base);"},{"line_number":2108,"context_line":"\t\t\tstmqspi_info-\u003eprobed \u003d false;"},{"line_number":2109,"context_line":"\t\t\tstmqspi_info-\u003edev.name \u003d \"none\";"},{"line_number":2110,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":2111,"context_line":"\t\t}"},{"line_number":2112,"context_line":"\t}"},{"line_number":2113,"context_line":""},{"line_number":2114,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3f59cb01","line":2111,"range":{"start_line":2106,"start_character":4,"end_line":2111,"end_character":3},"in_reply_to":"8e7fc396_fcce0186","updated":"2019-07-23 20:46:58.000000000","message":"Rearranged, more verbose message if cr or ccr read failed.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2111,"context_line":"\t\t}"},{"line_number":2112,"context_line":"\t}"},{"line_number":2113,"context_line":""},{"line_number":2114,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"},{"line_number":2115,"context_line":"\tretval \u003d read_flash_id(bank, \u0026id1, \u0026id2);"},{"line_number":2116,"context_line":"\tLOG_DEBUG(\"id1 0x%06\" PRIx32 \", id2 0x%06\" PRIx32, id1, id2);"},{"line_number":2117,"context_line":"\tif (retval \u003d\u003d ERROR_TARGET_NOT_EXAMINED) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9ccb4d75","line":2114,"range":{"start_line":2114,"start_character":30,"end_line":2114,"end_character":59},"updated":"2019-06-26 05:41:10.000000000","message":"The comment above read_flash_id says that it leaves the QUADSPI in indirect mode. I think this is handled fine in code, but the comment is wrong.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2111,"context_line":"\t\t}"},{"line_number":2112,"context_line":"\t}"},{"line_number":2113,"context_line":""},{"line_number":2114,"context_line":"\t/* read and decode flash ID; returns in memory mapped mode */"},{"line_number":2115,"context_line":"\tretval \u003d read_flash_id(bank, \u0026id1, \u0026id2);"},{"line_number":2116,"context_line":"\tLOG_DEBUG(\"id1 0x%06\" PRIx32 \", id2 0x%06\" PRIx32, id1, id2);"},{"line_number":2117,"context_line":"\tif (retval \u003d\u003d ERROR_TARGET_NOT_EXAMINED) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dcd6a5c8","line":2114,"range":{"start_line":2114,"start_character":30,"end_line":2114,"end_character":59},"in_reply_to":"8e7fc396_9ccb4d75","updated":"2019-07-23 20:46:58.000000000","message":"Right.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2211,"context_line":"\t\t\tLOG_INFO(\"flash2 \\\u0027%s\\\u0027 id \u003d 0x%06\" PRIx32 \" size \u003d %\" PRIu32"},{"line_number":2212,"context_line":"\t\t\t\t\"kbytes\", temp.name, id2, temp.size_in_bytes / 1024);"},{"line_number":2213,"context_line":"\t\t\t/* save info and retrieved *good* id as spi_sfdp clears all info */"},{"line_number":2214,"context_line":"\t\t\tmemcpy(\u0026stmqspi_info-\u003edev, \u0026temp, sizeof(temp));"},{"line_number":2215,"context_line":"\t\t\tstmqspi_info-\u003edev.device_id \u003d id2;"},{"line_number":2216,"context_line":"\t\t} else {"},{"line_number":2217,"context_line":"\t\t\t/* even not identified by SFDP, then give up */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_5ca5b5b0","line":2214,"range":{"start_line":2214,"start_character":3,"end_line":2214,"end_character":51},"updated":"2019-06-26 05:41:10.000000000","message":"This memcpy will overwrite stmqspi_info-\u003edev even if you already filled it by identifying Flash 1. In that case, you will, a little further down, compare to see if the two Flash chips are compatible, but that will always pass because it is actually comparing Flash 2 to itself, not Flash 2 to Flash 1.\n\nThis memcpy should be deleted; if there is only Flash 2, then the memcpy on line 2225 will do the job, while if there are both, then the compatibility check will work properly.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2211,"context_line":"\t\t\tLOG_INFO(\"flash2 \\\u0027%s\\\u0027 id \u003d 0x%06\" PRIx32 \" size \u003d %\" PRIu32"},{"line_number":2212,"context_line":"\t\t\t\t\"kbytes\", temp.name, id2, temp.size_in_bytes / 1024);"},{"line_number":2213,"context_line":"\t\t\t/* save info and retrieved *good* id as spi_sfdp clears all info */"},{"line_number":2214,"context_line":"\t\t\tmemcpy(\u0026stmqspi_info-\u003edev, \u0026temp, sizeof(temp));"},{"line_number":2215,"context_line":"\t\t\tstmqspi_info-\u003edev.device_id \u003d id2;"},{"line_number":2216,"context_line":"\t\t} else {"},{"line_number":2217,"context_line":"\t\t\t/* even not identified by SFDP, then give up */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_bf64fbaf","line":2214,"range":{"start_line":2214,"start_character":3,"end_line":2214,"end_character":51},"in_reply_to":"8e7fc396_5ca5b5b0","updated":"2019-07-23 20:46:58.000000000","message":"Yes, deleted.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2296,"context_line":"\tif (stmqspi_info-\u003eprobed)"},{"line_number":2297,"context_line":"\t\treturn ERROR_OK;"},{"line_number":2298,"context_line":"\tstmqspi_probe(bank);"},{"line_number":2299,"context_line":"\treturn ERROR_OK;"},{"line_number":2300,"context_line":"}"},{"line_number":2301,"context_line":""},{"line_number":2302,"context_line":"static int stmqspi_protect_check(struct flash_bank *bank)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7caaf183","line":2299,"range":{"start_line":2299,"start_character":8,"end_line":2299,"end_character":16},"updated":"2019-06-26 05:41:10.000000000","message":"Was throwing out the return value from stmqspi_probe intentional?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2296,"context_line":"\tif (stmqspi_info-\u003eprobed)"},{"line_number":2297,"context_line":"\t\treturn ERROR_OK;"},{"line_number":2298,"context_line":"\tstmqspi_probe(bank);"},{"line_number":2299,"context_line":"\treturn ERROR_OK;"},{"line_number":2300,"context_line":"}"},{"line_number":2301,"context_line":""},{"line_number":2302,"context_line":"static int stmqspi_protect_check(struct flash_bank *bank)"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fcd361d5","line":2299,"range":{"start_line":2299,"start_character":8,"end_line":2299,"end_character":16},"in_reply_to":"8e7fc396_7caaf183","updated":"2019-07-23 20:46:58.000000000","message":"Yes, as an unsuccessful probe might not be a real error, but only due to the flash to not (yet) being included in spi.c.\nThe specific reason is output anyway, and returning an error here adds only some clutter.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2316,"context_line":"\t}"},{"line_number":2317,"context_line":""},{"line_number":2318,"context_line":"\tsnprintf(buf, buf_size, \"flash%s%s \\\u0027%s\\\u0027, device id \u003d 0x%06\" PRIx32"},{"line_number":2319,"context_line":"\t\t\t\", flash size \u003d %\" PRIu32 \"%sbytes\\n(page size \u003d %d, read \u003d 0x%02\" PRIx8"},{"line_number":2320,"context_line":"\t\t\t\", qread \u003d 0x%02\" PRIx8 \", pprog \u003d 0x%02\" PRIx8"},{"line_number":2321,"context_line":"\t\t\t\", mass_erase \u003d 0x%02\" PRIx8 \", sector size \u003d %\" PRIu32 \"%sbytes\""},{"line_number":2322,"context_line":"\t\t\t\", sector_erase \u003d 0x%02\" PRIx8 \")\","}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1caf3d93","line":2319,"range":{"start_line":2319,"start_character":52,"end_line":2319,"end_character":54},"updated":"2019-06-26 05:41:10.000000000","message":"pagesize is a uint32_t; PRIu32 would be appropriate.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2316,"context_line":"\t}"},{"line_number":2317,"context_line":""},{"line_number":2318,"context_line":"\tsnprintf(buf, buf_size, \"flash%s%s \\\u0027%s\\\u0027, device id \u003d 0x%06\" PRIx32"},{"line_number":2319,"context_line":"\t\t\t\", flash size \u003d %\" PRIu32 \"%sbytes\\n(page size \u003d %d, read \u003d 0x%02\" PRIx8"},{"line_number":2320,"context_line":"\t\t\t\", qread \u003d 0x%02\" PRIx8 \", pprog \u003d 0x%02\" PRIx8"},{"line_number":2321,"context_line":"\t\t\t\", mass_erase \u003d 0x%02\" PRIx8 \", sector size \u003d %\" PRIu32 \"%sbytes\""},{"line_number":2322,"context_line":"\t\t\t\", sector_erase \u003d 0x%02\" PRIx8 \")\","}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7f5f43e9","line":2319,"range":{"start_line":2319,"start_character":52,"end_line":2319,"end_character":54},"in_reply_to":"8e7fc396_1caf3d93","updated":"2019-07-23 20:46:58.000000000","message":"Ok.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":2349,"context_line":"\t\t.name \u003d \"set\","},{"line_number":2350,"context_line":"\t\t.handler \u003d stmqspi_handle_set,"},{"line_number":2351,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":2352,"context_line":"\t\t.usage \u003d \"bank_id name chip_size page_size read_cmd pprg_cmd \""},{"line_number":2353,"context_line":"\t\t\t\"[ mass_erase_cmd ] [ sector_size sector_erase_cmd ]\","},{"line_number":2354,"context_line":"\t\t.help \u003d \"Set params of single flash chip\","},{"line_number":2355,"context_line":"\t},"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dc6d4598","line":2352,"updated":"2019-06-26 05:41:10.000000000","message":"qread_cmd is missing between read_cmd and pprg_cmd.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":2349,"context_line":"\t\t.name \u003d \"set\","},{"line_number":2350,"context_line":"\t\t.handler \u003d stmqspi_handle_set,"},{"line_number":2351,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":2352,"context_line":"\t\t.usage \u003d \"bank_id name chip_size page_size read_cmd pprg_cmd \""},{"line_number":2353,"context_line":"\t\t\t\"[ mass_erase_cmd ] [ sector_size sector_erase_cmd ]\","},{"line_number":2354,"context_line":"\t\t.help \u003d \"Set params of single flash chip\","},{"line_number":2355,"context_line":"\t},"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1f540fc9","line":2352,"in_reply_to":"8e7fc396_dc6d4598","updated":"2019-07-23 20:46:58.000000000","message":"Inserted.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c27bf2f0d0d93be69f33a9b083b64e5cf245f4ff","unresolved":false,"context_lines":[{"line_number":310,"context_line":"\tint retval;"},{"line_number":311,"context_line":""},{"line_number":312,"context_line":"\t/* Wait for busy to be cleared */"},{"line_number":313,"context_line":"\tretval \u003d poll_busy(bank, SPI_PROBE_TIMEOUT);"},{"line_number":314,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":315,"context_line":"\t\tgoto err;"},{"line_number":316,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_5fb84774","line":313,"range":{"start_line":313,"start_character":10,"end_line":313,"end_character":19},"updated":"2019-07-29 19:47:31.000000000","message":"If the previous operation was an indirect read—which could have been another call to read_status_reg (e.g. in wait_till_ready)—then this could hang due to the extra-bytes-in-RXFIFO-after-indirect-read F7 erratum, couldn’t it? Should this function abort before starting the status register read?\n\nThis might also affect e.g. qspi_write_enable, which does a read_status_reg as its last action and then returns, and its callers then do more actions. Also various other callers to read_status_reg.","commit_id":"768638b8c79e0e8fe800a1ab745ba8484a40a6b7"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c27bf2f0d0d93be69f33a9b083b64e5cf245f4ff","unresolved":false,"context_lines":[{"line_number":1825,"context_line":"\t\t}"},{"line_number":1826,"context_line":"\t}"},{"line_number":1827,"context_line":""},{"line_number":1828,"context_line":"\tLOG_DEBUG(\"%s: addr\u003d0x%08\" PRIx32 \" words\u003d0x%08\" PRIx32 \" dummy\u003d%d\","},{"line_number":1829,"context_line":"\t\t__func__, addr, words, *dummy);"},{"line_number":1830,"context_line":""},{"line_number":1831,"context_line":"\t/* Abort any previous operation */"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_bf8b9bc3","line":1828,"range":{"start_line":1828,"start_character":43,"end_line":1828,"end_character":56},"updated":"2019-07-29 19:47:31.000000000","message":"words is an int, not a uint32_t","commit_id":"768638b8c79e0e8fe800a1ab745ba8484a40a6b7"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":115,"context_line":""},{"line_number":116,"context_line":"/* OCTOSPI_CCR for various other commands, these never use alternate bytes\t*"},{"line_number":117,"context_line":" * for READ_STATUS and READ_ID, 4-byte address 0\t\t\t\t\t\t\t*"},{"line_number":118,"context_line":" * 4 bummy cycles must sent in OPI mode when DQS is disabled, however, when\t*"},{"line_number":119,"context_line":" * DQS is enabled, some STM32 devices need at least 6 dummy cycles for\t\t*"},{"line_number":120,"context_line":" * proper operation, but otherwise the actual number has no effect!\t\t\t*"},{"line_number":121,"context_line":" */"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_303ee827","line":118,"range":{"start_line":118,"start_character":5,"end_line":118,"end_character":10},"updated":"2020-10-21 23:03:10.000000000","message":"dummy","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":115,"context_line":""},{"line_number":116,"context_line":"/* OCTOSPI_CCR for various other commands, these never use alternate bytes\t*"},{"line_number":117,"context_line":" * for READ_STATUS and READ_ID, 4-byte address 0\t\t\t\t\t\t\t*"},{"line_number":118,"context_line":" * 4 bummy cycles must sent in OPI mode when DQS is disabled, however, when\t*"},{"line_number":119,"context_line":" * DQS is enabled, some STM32 devices need at least 6 dummy cycles for\t\t*"},{"line_number":120,"context_line":" * proper operation, but otherwise the actual number has no effect!\t\t\t*"},{"line_number":121,"context_line":" */"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_706c7006","line":118,"range":{"start_line":118,"start_character":5,"end_line":118,"end_character":10},"in_reply_to":"ceda9b01_303ee827","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":915,"context_line":"\treturn retval;"},{"line_number":916,"context_line":"}"},{"line_number":917,"context_line":""},{"line_number":918,"context_line":"static int qspi_erase_sector(struct flash_bank *bank, int sector)"},{"line_number":919,"context_line":"{"},{"line_number":920,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":921,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_d042fcb1","line":918,"range":{"start_line":918,"start_character":54,"end_line":918,"end_character":57},"updated":"2020-10-21 23:03:10.000000000","message":"unsigned int","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":915,"context_line":"\treturn retval;"},{"line_number":916,"context_line":"}"},{"line_number":917,"context_line":""},{"line_number":918,"context_line":"static int qspi_erase_sector(struct flash_bank *bank, int sector)"},{"line_number":919,"context_line":"{"},{"line_number":920,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":921,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_107164dd","line":918,"range":{"start_line":918,"start_character":54,"end_line":918,"end_character":57},"in_reply_to":"ceda9b01_d042fcb1","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":1186,"context_line":"\t\tarmv7m_info.common_magic \u003d ARMV7M_COMMON_MAGIC;"},{"line_number":1187,"context_line":"\t\tarmv7m_info.core_mode \u003d ARM_MODE_THREAD;"},{"line_number":1188,"context_line":""},{"line_number":1189,"context_line":"\t\tLOG_DEBUG(\"checking sectors %d to %d\", sector, sector + count - 1);"},{"line_number":1190,"context_line":"\t\t/* check a block of sectors */"},{"line_number":1191,"context_line":"\t\tretval \u003d target_run_algorithm(target,"},{"line_number":1192,"context_line":"\t\t\t0, NULL,"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_f03f001f","line":1189,"range":{"start_line":1189,"start_character":30,"end_line":1189,"end_character":38},"updated":"2020-10-21 23:03:10.000000000","message":"%u to %u","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":1186,"context_line":"\t\tarmv7m_info.common_magic \u003d ARMV7M_COMMON_MAGIC;"},{"line_number":1187,"context_line":"\t\tarmv7m_info.core_mode \u003d ARM_MODE_THREAD;"},{"line_number":1188,"context_line":""},{"line_number":1189,"context_line":"\t\tLOG_DEBUG(\"checking sectors %d to %d\", sector, sector + count - 1);"},{"line_number":1190,"context_line":"\t\t/* check a block of sectors */"},{"line_number":1191,"context_line":"\t\tretval \u003d target_run_algorithm(target,"},{"line_number":1192,"context_line":"\t\t\t0, NULL,"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_3076e8d6","line":1189,"range":{"start_line":1189,"start_character":30,"end_line":1189,"end_character":38},"in_reply_to":"ceda9b01_f03f001f","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":1634,"context_line":"\t\tif ((offset \u003c (bank-\u003esectors[sector].offset + bank-\u003esectors[sector].size))"},{"line_number":1635,"context_line":"\t\t\t\u0026\u0026 ((offset + count - 1) \u003e\u003d bank-\u003esectors[sector].offset)"},{"line_number":1636,"context_line":"\t\t\t\u0026\u0026 bank-\u003esectors[sector].is_protected) {"},{"line_number":1637,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":1638,"context_line":"\t\t\treturn ERROR_FLASH_PROTECTED;"},{"line_number":1639,"context_line":"\t\t}"},{"line_number":1640,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_904c74e6","line":1637,"range":{"start_line":1637,"start_character":27,"end_line":1637,"end_character":29},"updated":"2020-10-21 23:03:10.000000000","message":"%u","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":1634,"context_line":"\t\tif ((offset \u003c (bank-\u003esectors[sector].offset + bank-\u003esectors[sector].size))"},{"line_number":1635,"context_line":"\t\t\t\u0026\u0026 ((offset + count - 1) \u003e\u003d bank-\u003esectors[sector].offset)"},{"line_number":1636,"context_line":"\t\t\t\u0026\u0026 bank-\u003esectors[sector].is_protected) {"},{"line_number":1637,"context_line":"\t\t\tLOG_ERROR(\"Flash sector %d protected\", sector);"},{"line_number":1638,"context_line":"\t\t\treturn ERROR_FLASH_PROTECTED;"},{"line_number":1639,"context_line":"\t\t}"},{"line_number":1640,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_f07700ce","line":1637,"range":{"start_line":1637,"start_character":27,"end_line":1637,"end_character":29},"in_reply_to":"ceda9b01_904c74e6","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":1932,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1933,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1934,"context_line":"\tuint8_t byte;"},{"line_number":1935,"context_line":"\tint type, count, len1, len2, retval;"},{"line_number":1936,"context_line":""},{"line_number":1937,"context_line":"\t/* invalidate both ids */"},{"line_number":1938,"context_line":"\t*id1 \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_b04978d5","line":1935,"updated":"2020-10-21 23:03:10.000000000","message":"All these except retval could be unsigned.","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":1932,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1933,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1934,"context_line":"\tuint8_t byte;"},{"line_number":1935,"context_line":"\tint type, count, len1, len2, retval;"},{"line_number":1936,"context_line":""},{"line_number":1937,"context_line":"\t/* invalidate both ids */"},{"line_number":1938,"context_line":"\t*id1 \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_908474a5","line":1935,"in_reply_to":"ceda9b01_b04978d5","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","unresolved":false,"context_lines":[{"line_number":2064,"context_line":"\tuint32_t id1 \u003d 0, id2 \u003d 0, data \u003d 0;"},{"line_number":2065,"context_line":"\tconst struct flash_device *p;"},{"line_number":2066,"context_line":"\tconst uint32_t magic \u003d 0xAEF1510E;"},{"line_number":2067,"context_line":"\tint dual, fsize, retval;"},{"line_number":2068,"context_line":""},{"line_number":2069,"context_line":"\tif (stmqspi_info-\u003eprobed) {"},{"line_number":2070,"context_line":"\t\tbank-\u003esize \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_50160cae","line":2067,"updated":"2020-10-21 23:03:10.000000000","message":"dual and fsize could be unsigned.","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"f9e01133ad68c98355ddceb605d722eba7461845","unresolved":false,"context_lines":[{"line_number":2064,"context_line":"\tuint32_t id1 \u003d 0, id2 \u003d 0, data \u003d 0;"},{"line_number":2065,"context_line":"\tconst struct flash_device *p;"},{"line_number":2066,"context_line":"\tconst uint32_t magic \u003d 0xAEF1510E;"},{"line_number":2067,"context_line":"\tint dual, fsize, retval;"},{"line_number":2068,"context_line":""},{"line_number":2069,"context_line":"\tif (stmqspi_info-\u003eprobed) {"},{"line_number":2070,"context_line":"\t\tbank-\u003esize \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ceda9b01_d07afcb8","line":2067,"in_reply_to":"ceda9b01_50160cae","updated":"2020-10-23 14:32:10.000000000","message":"Done","commit_id":"88ab17c5f691ee78c8871eb0e669658090005c20"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"f6664f2f486d2f4c026dc8ee732abfa87a54998f","unresolved":false,"context_lines":[{"line_number":1213,"context_line":"\t\t\t/* we need le_32_to_h, but that\u0027s the same as h_to_le_32 */"},{"line_number":1214,"context_line":"\t\t\tresult \u003d h_to_le_32(erase_check_info.result);"},{"line_number":1215,"context_line":"\t\t\tbank-\u003esectors[sector + index].is_erased \u003d ((result \u0026 0xFF) \u003d\u003d 0xFF);"},{"line_number":1216,"context_line":"\t\t\tLOG_DEBUG(\"Flash sector %u checked: %04x\", sector + index, result \u0026 0xFFFF);"},{"line_number":1217,"context_line":"\t\t}"},{"line_number":1218,"context_line":"\t\tkeep_alive();"},{"line_number":1219,"context_line":"\t\tsector +\u003d count;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_d028bc98","line":1216,"updated":"2020-10-23 17:41:17.000000000","message":"%04x wants an unsigned int. If the platform has ints larger than 32 bits, then (result \u0026 0xFFFF) will be promoted to an int, not an unsigned int, and passed as such. Also uint32_t on a 32-bit platform could legally be unsigned long, in which case the value would be passed as that type whereas an unsigned int is expected.\n\nHow about this?\nLOG_DEBUG(\"Flash sector %u checked: %04\" PRIx16, sector + index, (uint16_t) result);","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"5f5f1577a14ec9d9284ba8b802b2d9d997d92906","unresolved":false,"context_lines":[{"line_number":1213,"context_line":"\t\t\t/* we need le_32_to_h, but that\u0027s the same as h_to_le_32 */"},{"line_number":1214,"context_line":"\t\t\tresult \u003d h_to_le_32(erase_check_info.result);"},{"line_number":1215,"context_line":"\t\t\tbank-\u003esectors[sector + index].is_erased \u003d ((result \u0026 0xFF) \u003d\u003d 0xFF);"},{"line_number":1216,"context_line":"\t\t\tLOG_DEBUG(\"Flash sector %u checked: %04x\", sector + index, result \u0026 0xFFFF);"},{"line_number":1217,"context_line":"\t\t}"},{"line_number":1218,"context_line":"\t\tkeep_alive();"},{"line_number":1219,"context_line":"\t\tsector +\u003d count;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_531616ae","line":1216,"in_reply_to":"ceda9b01_d028bc98","updated":"2020-10-28 19:33:27.000000000","message":"Done","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"f6664f2f486d2f4c026dc8ee732abfa87a54998f","unresolved":false,"context_lines":[{"line_number":1608,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1609,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1610,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1611,"context_line":"\tunsigned int dual, octal_dtr, sector;"},{"line_number":1612,"context_line":"\tint retval;"},{"line_number":1613,"context_line":""},{"line_number":1614,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_3044a86e","line":1611,"updated":"2020-10-23 17:41:17.000000000","message":"octal_dtr and dual could be bools. So could dual in a handful of other functions, but doing bitshifts by bools looks funny so while it’s valid code I also think it’s reasonable to not change them. But there are no bitshifts in this function, so dual could be a bool here.","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"5f5f1577a14ec9d9284ba8b802b2d9d997d92906","unresolved":false,"context_lines":[{"line_number":1608,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1609,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1610,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1611,"context_line":"\tunsigned int dual, octal_dtr, sector;"},{"line_number":1612,"context_line":"\tint retval;"},{"line_number":1613,"context_line":""},{"line_number":1614,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_b34982d5","line":1611,"in_reply_to":"ceda9b01_3044a86e","updated":"2020-10-28 19:33:27.000000000","message":"See below.","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"f6664f2f486d2f4c026dc8ee732abfa87a54998f","unresolved":false,"context_lines":[{"line_number":1670,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1671,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1672,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1673,"context_line":"\tunsigned int dual, octal_dtr;"},{"line_number":1674,"context_line":"\tint retval;"},{"line_number":1675,"context_line":""},{"line_number":1676,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_f025c0bd","line":1673,"updated":"2020-10-23 17:41:17.000000000","message":"These could both be bools too.","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"5f5f1577a14ec9d9284ba8b802b2d9d997d92906","unresolved":false,"context_lines":[{"line_number":1670,"context_line":"\tstruct target *target \u003d bank-\u003etarget;"},{"line_number":1671,"context_line":"\tstruct stmqspi_flash_bank *stmqspi_info \u003d bank-\u003edriver_priv;"},{"line_number":1672,"context_line":"\tuint32_t io_base \u003d stmqspi_info-\u003eio_base;"},{"line_number":1673,"context_line":"\tunsigned int dual, octal_dtr;"},{"line_number":1674,"context_line":"\tint retval;"},{"line_number":1675,"context_line":""},{"line_number":1676,"context_line":"\tLOG_DEBUG(\"%s: offset\u003d0x%08\" PRIx32 \" count\u003d0x%08\" PRIx32,"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"ceda9b01_934c7ee6","line":1673,"in_reply_to":"ceda9b01_f025c0bd","updated":"2020-10-28 19:33:27.000000000","message":"Yes, quite right. But having the very same expression with the same name at some places as bool and sometimes as int is rather confusing. Hence I\u0027d prefer to leave dual as it is.\nFor octal_dtr it\u0027s different, changed.","commit_id":"fe85c0165d8111539f0929871c9ee207afd686ca"}],"src/flash/nor/stmqspi.h":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"/* deprecated */"},{"line_number":25,"context_line":"#undef SPIFLASH_READ"},{"line_number":26,"context_line":"#undef SPIFLASH_PAGE_PROGRAM"},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"/* QSPI register offsets */"},{"line_number":29,"context_line":"#define QSPI_CR\t\t\t(0x00)\t/* Control register */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_7cd99182","line":26,"updated":"2019-06-26 05:41:10.000000000","message":"This looks pretty weird to me: if someone includes spi.h then these are defined, but if they include spi.h and then include stmqspi.h afterwards then they are not defined. What’s wrong with leaving these alone?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"/* deprecated */"},{"line_number":25,"context_line":"#undef SPIFLASH_READ"},{"line_number":26,"context_line":"#undef SPIFLASH_PAGE_PROGRAM"},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"/* QSPI register offsets */"},{"line_number":29,"context_line":"#define QSPI_CR\t\t\t(0x00)\t/* Control register */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_9cbfcda7","line":26,"in_reply_to":"8e7fc396_7cd99182","updated":"2019-07-23 20:46:58.000000000","message":"The best solution would be to drop SPIFLASH_READ and SPIFLASH_PAGE_PROGRAM in spi.h in favour of read_cmd and pprog_cmd in struct flash_device. But this would require a lot of changes in other drivers. The #undef should only make sure these \u0027old\u0027 defines are never accidentally used here.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"/* deprecated */"},{"line_number":25,"context_line":"#undef SPIFLASH_READ"},{"line_number":26,"context_line":"#undef SPIFLASH_PAGE_PROGRAM"},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"/* QSPI register offsets */"},{"line_number":29,"context_line":"#define QSPI_CR\t\t\t(0x00)\t/* Control register */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1f9baf1c","line":26,"in_reply_to":"8e7fc396_9cbfcda7","updated":"2019-07-29 19:35:48.000000000","message":"I’m totally on board with the #undef in stmqspi.c as an error check to make sure nobody accidentally uses it in that implementation, it just seems wrong to do it in stmqspi.h, because that means other code, which is totally unrelated to QSPI (other than as an ordinary consumer, using it), would be affected.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"src/flash/nor/tcl.c":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":944,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":945,"context_line":"\t}"},{"line_number":946,"context_line":""},{"line_number":947,"context_line":"\tretval \u003d flash_driver_read(p, buffer_flash, offset, length);"},{"line_number":948,"context_line":"\tif (retval !\u003d ERROR_OK) {"},{"line_number":949,"context_line":"\t\tLOG_ERROR(\"Flash read error\");"},{"line_number":950,"context_line":"\t\tfree(buffer_flash);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_3cb479e4","line":947,"updated":"2019-06-26 05:41:10.000000000","message":"How about using flash_driver_verify here, so that the verify_bank command can also benefit from verify algorithms when the target Flash driver provides them?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":944,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":945,"context_line":"\t}"},{"line_number":946,"context_line":""},{"line_number":947,"context_line":"\tretval \u003d flash_driver_read(p, buffer_flash, offset, length);"},{"line_number":948,"context_line":"\tif (retval !\u003d ERROR_OK) {"},{"line_number":949,"context_line":"\t\tLOG_ERROR(\"Flash read error\");"},{"line_number":950,"context_line":"\t\tfree(buffer_flash);"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_fcf04190","line":947,"in_reply_to":"8e7fc396_3cb479e4","updated":"2019-07-23 20:46:58.000000000","message":"That\u0027s better done in a separate patch. I don\u0027t want to change functionality without a very strong reason. Despite the fact that in this case, it\u0027s probably not intrusive.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"src/target/target.c":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":1013,"context_line":"\t\t\t * programming. The exact delay shouldn\u0027t matter as long as it\u0027s"},{"line_number":1014,"context_line":"\t\t\t * less than buffer size / flash speed. This is very unlikely to"},{"line_number":1015,"context_line":"\t\t\t * run when using high latency connections such as USB. */"},{"line_number":1016,"context_line":"\t\t\talive_sleep(4);"},{"line_number":1017,"context_line":""},{"line_number":1018,"context_line":"\t\t\t/* to stop an infinite loop on some targets check and increment a timeout"},{"line_number":1019,"context_line":"\t\t\t * this issue was observed on a stellaris using the new ICDI interface */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_dc98e57e","line":1016,"updated":"2019-06-26 05:41:10.000000000","message":"Some reason for this change?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":1013,"context_line":"\t\t\t * programming. The exact delay shouldn\u0027t matter as long as it\u0027s"},{"line_number":1014,"context_line":"\t\t\t * less than buffer size / flash speed. This is very unlikely to"},{"line_number":1015,"context_line":"\t\t\t * run when using high latency connections such as USB. */"},{"line_number":1016,"context_line":"\t\t\talive_sleep(4);"},{"line_number":1017,"context_line":""},{"line_number":1018,"context_line":"\t\t\t/* to stop an infinite loop on some targets check and increment a timeout"},{"line_number":1019,"context_line":"\t\t\t * this issue was observed on a stellaris using the new ICDI interface */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8e7fc396_1ce3bdd5","line":1016,"in_reply_to":"8e7fc396_dc98e57e","updated":"2019-07-23 20:46:58.000000000","message":"Don\u0027t remember the figures, but with 24 MHz SWD clock there was some increase in programming speed from 10ms to 4ms. Below 4ms no further significant benefit.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"tcl/board/b-l475e-iot01a.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# QUADSPI initialization"},{"line_number":18,"context_line":"proc qspi_init { } {"},{"line_number":19,"context_line":"\tglobal a"},{"line_number":20,"context_line":"\tmmw 0x4002104C 0x000001FF 0\t\t\t\t;# RCC_AHB2ENR |\u003d GPIOA-GPIOI (enable clocks)"},{"line_number":21,"context_line":"\tmmw 0x40021050 0x00000100 0\t\t\t\t;# RCC_AHB3ENR |\u003d QSPIEN (enable clock)"},{"line_number":22,"context_line":"\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_9ca26da3","line":19,"updated":"2019-06-26 05:41:10.000000000","message":"You don’t seem to use this variable anywhere, yet you declare it in all the board files. On some of the board files you mention it in some comments, but I don’t see where it gets set, so I don’t see how those comments could work either. Same applies for the “b” variable in some board files.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# QUADSPI initialization"},{"line_number":18,"context_line":"proc qspi_init { } {"},{"line_number":19,"context_line":"\tglobal a"},{"line_number":20,"context_line":"\tmmw 0x4002104C 0x000001FF 0\t\t\t\t;# RCC_AHB2ENR |\u003d GPIOA-GPIOI (enable clocks)"},{"line_number":21,"context_line":"\tmmw 0x40021050 0x00000100 0\t\t\t\t;# RCC_AHB3ENR |\u003d QSPIEN (enable clock)"},{"line_number":22,"context_line":"\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_5cd9352b","line":19,"in_reply_to":"8e7fc396_9ca26da3","updated":"2019-07-23 20:46:58.000000000","message":"Not in this file, yes. Point is, for (manual) configuration of the flash chips and inspection of the config registers via \u0027stmqspi cmd\u0027, the bank number is needed over and over again. In case of the F7, the recently added itcm and otp banks caused the bank numbers to change. To have a really short and stable shorthand for the bank numbers turned out to be very convenient. So $a -\u003e first QPSI flash bank, $b -\u003e second, ...\n\nThey\u0027re set in the target cfg files right before the corresponding \u0027flash bank\u0027.","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"tcl/board/nucleo-f767zi.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4e50c53ea665c75dfeab266362f9cb8f7a1f53a8","unresolved":false,"context_lines":[{"line_number":13,"context_line":"set WORKAREASIZE 0x10000"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# enable stmqspi"},{"line_number":16,"context_line":"set QUADSPI 1"},{"line_number":17,"context_line":""},{"line_number":18,"context_line":"source [find target/stm32f7x.cfg]"},{"line_number":19,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"0e83d3c5_4515dc9b","line":16,"range":{"start_line":16,"start_character":0,"end_line":16,"end_character":13},"updated":"2018-02-03 15:42:22.000000000","message":"Still pushing the user too hard to use QSPI.\nWould not be better to give the user a chance to redefine w/o writing to this cfg?\nif {![info exists QUADSPI]} { set QUADSPI 1 }","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4e50c53ea665c75dfeab266362f9cb8f7a1f53a8","unresolved":false,"context_lines":[{"line_number":124,"context_line":"\tsleep 1"},{"line_number":125,"context_line":""},{"line_number":126,"context_line":"\tadapter_khz 4000"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tqspi_init 0 1"},{"line_number":129,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"0e83d3c5_e52990e3","line":127,"updated":"2018-02-03 15:42:22.000000000","message":"if { $QUADSPI }","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"70cc507dca73e130c83330a5c2dbb6c0855bc95e","unresolved":false,"context_lines":[{"line_number":124,"context_line":"\tsleep 1"},{"line_number":125,"context_line":""},{"line_number":126,"context_line":"\tadapter_khz 4000"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tqspi_init 0 1"},{"line_number":129,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"0e83d3c5_858204cc","line":127,"in_reply_to":"0e83d3c5_e52990e3","updated":"2018-02-03 16:15:54.000000000","message":"It also needs \u0027global\u0027 declaration","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"}],"tcl/board/stm32f746g-disco.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","unresolved":false,"context_lines":[{"line_number":39,"context_line":"\tmmw 0x40021008 0x00000030 0x00000000\t;# OSPEEDR"},{"line_number":40,"context_line":"\tmmw 0x40021020 0x00000900 0x00000600\t;# AFRL"},{"line_number":41,"context_line":""},{"line_number":42,"context_line":"\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER\u003d3, APMS\u003d1, FTHRES\u003d0, FSEL\u003d0, DFM\u003d0, SSHIFT\u003d0, TCEN\u003d1"},{"line_number":43,"context_line":"\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE\u003d0x17, CSHT\u003d0x01, CKMODE\u003d0"},{"line_number":44,"context_line":"\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN\u003d1"},{"line_number":45,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"6e936f18_d743e441","line":42,"updated":"2018-10-14 22:56:00.000000000","message":"According to errata sheet ES0290 revision 6 section 2.4.4, do not use the timeout counter with memory mapped mode on the F74/F75 series. Maybe others, too.","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"}],"tcl/board/stm32h750b-disco.cfg":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"564c7fa39c2431b3efa6124d64e6b6befea1c903","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# This is a stm32h745i-disco with a single STM32H745XIH6 chip."},{"line_number":2,"context_line":"# www.st.com/en/product/stm32h745i-disco.html"},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# stm32h750b-dk is the same board but with different mcu,"},{"line_number":5,"context_line":"# but this file can be used for that board, too"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_df43ee41","line":2,"updated":"2020-03-11 09:54:22.000000000","message":"Wrong board/chip","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"2c50a639b367596f99b9e8e4cd210d8f804e3431","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# This is a stm32h745i-disco with a single STM32H745XIH6 chip."},{"line_number":2,"context_line":"# www.st.com/en/product/stm32h745i-disco.html"},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# stm32h750b-dk is the same board but with different mcu,"},{"line_number":5,"context_line":"# but this file can be used for that board, too"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_dfbe8efa","line":2,"in_reply_to":"2e76d7c5_df43ee41","updated":"2020-03-12 09:01:56.000000000","message":"Yes, that\u0027s an artifact of git not beeing able to deal with hardlinks, see comment below. This was intentional simply a hardlink to stm32h745i-disco.cfg, see comment below, but it seems this is misleading. So I\u0027ll make real copy and adjust the naming etc.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# This is a stm32h745i-disco with a single STM32H745XIH6 chip."},{"line_number":2,"context_line":"# www.st.com/en/product/stm32h745i-disco.html"},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# stm32h750b-dk is the same board but with different mcu,"},{"line_number":5,"context_line":"# but this file can be used for that board, too"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_ff1b4a1f","line":2,"in_reply_to":"2e76d7c5_dfbe8efa","updated":"2020-03-12 12:10:51.000000000","message":"If the files really can be the same, including a common file from both would be a better solution than hard- or symlinks which doesn\u0027t work everywhere. Straight copies are not perfect from a maintainability perspective either.\n\nAnyway, perhaps the files can\u0027t be identical, see for example my comments below.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"564c7fa39c2431b3efa6124d64e6b6befea1c903","unresolved":false,"context_lines":[{"line_number":10,"context_line":""},{"line_number":11,"context_line":"transport select hla_swd"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set CHIPNAME stm32h745xih6"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# enable stmqspi"},{"line_number":16,"context_line":"if {![info exists QUADSPI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_1f3ac6c0","line":13,"range":{"start_line":13,"start_character":13,"end_line":13,"end_character":26},"updated":"2020-03-11 09:54:22.000000000","message":"stm32h750xbh6","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"564c7fa39c2431b3efa6124d64e6b6befea1c903","unresolved":false,"context_lines":[{"line_number":17,"context_line":"\tset QUADSPI 1"},{"line_number":18,"context_line":"}"},{"line_number":19,"context_line":""},{"line_number":20,"context_line":"source [find target/stm32h7x_dual_bank.cfg]"},{"line_number":21,"context_line":""},{"line_number":22,"context_line":"# QUADSPI initialization"},{"line_number":23,"context_line":"# qpi: 4-line mode"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_bf463253","line":20,"range":{"start_line":20,"start_character":20,"end_line":20,"end_character":42},"updated":"2020-03-11 09:54:22.000000000","message":"stm32h7x.cfg\nOnly a single bank on h750","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","unresolved":false,"context_lines":[{"line_number":106,"context_line":"\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT\u003d1"},{"line_number":107,"context_line":"\t\tmww 0x52005014 0x0D003513\t\t\t;# QUADSPI_CCR: FMODE\u003d0x3, DMODE\u003d0x1, DCYC\u003d0x0, ADSIZE\u003d0x3, ADMODE\u003d0x1, IMODE\u003d0x1, INSTR\u003dREAD"},{"line_number":108,"context_line":"\t}"},{"line_number":109,"context_line":"}"},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"$_CHIPNAME.cpu0 configure -event reset-init {"},{"line_number":112,"context_line":"\tglobal QUADSPI"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_1f196627","line":109,"updated":"2020-03-12 12:10:51.000000000","message":"Maybe at least this proc can be generalized and put in a common file to be sourced in many board files. GPIO setup may need to be broken out.","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7a86adf488a0e557d47f01345f2c0f23642821b1","unresolved":false,"context_lines":[{"line_number":106,"context_line":"\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT\u003d1"},{"line_number":107,"context_line":"\t\tmww 0x52005014 0x0D003513\t\t\t;# QUADSPI_CCR: FMODE\u003d0x3, DMODE\u003d0x1, DCYC\u003d0x0, ADSIZE\u003d0x3, ADMODE\u003d0x1, IMODE\u003d0x1, INSTR\u003dREAD"},{"line_number":108,"context_line":"\t}"},{"line_number":109,"context_line":"}"},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"$_CHIPNAME.cpu0 configure -event reset-init {"},{"line_number":112,"context_line":"\tglobal QUADSPI"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"0ed113e2_384d719c","line":109,"in_reply_to":"2e76d7c5_1f196627","updated":"2020-05-24 14:00:44.000000000","message":"Ok, moved into include file","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"}],"tcl/target/stm32f4x.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d95d2493b3e899d8e3393f40eb44d7e4e723f51a","unresolved":false,"context_lines":[{"line_number":49,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":50,"context_line":"flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME"},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if { [info exists QUADSPI ] } {"},{"line_number":53,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":54,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"},{"line_number":55,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"0e83d3c5_c5200cf5","line":52,"range":{"start_line":52,"start_character":27,"end_line":52,"end_character":28},"updated":"2018-02-03 16:02:53.000000000","message":"\u0026\u0026 QUADSPI","commit_id":"fc2fe67e631d29dc59794717d8faf887623437f3"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":52,"context_line":""},{"line_number":53,"context_line":"flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME"},{"line_number":54,"context_line":""},{"line_number":55,"context_line":"if { [info exists QUADSPI] \u0026\u0026 QUADSPI } {"},{"line_number":56,"context_line":"   set a [llength [flash list]]"},{"line_number":57,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":58,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_1c1c1d6a","line":55,"updated":"2019-06-26 05:41:10.000000000","message":"Does QUADSPI work here (in the second occurrence, not the first), or do you need $QUADSPI?","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":52,"context_line":""},{"line_number":53,"context_line":"flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME"},{"line_number":54,"context_line":""},{"line_number":55,"context_line":"if { [info exists QUADSPI] \u0026\u0026 QUADSPI } {"},{"line_number":56,"context_line":"   set a [llength [flash list]]"},{"line_number":57,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":58,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_dccc6569","line":55,"in_reply_to":"8e7fc396_1c1c1d6a","updated":"2019-07-23 20:46:58.000000000","message":"Right, \u0027$\u0027 is missing","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"tcl/target/stm32f7x.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":64,"context_line":"#     the Flash via ITCM alias as virtual"},{"line_number":65,"context_line":"flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME"},{"line_number":66,"context_line":""},{"line_number":67,"context_line":"if { [info exists QUADSPI ] } {"},{"line_number":68,"context_line":"   set a [llength [flash list]]"},{"line_number":69,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":70,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_7c2751b2","line":67,"updated":"2019-06-26 05:41:10.000000000","message":"\u0026\u0026 $QUADSPI","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":64,"context_line":"#     the Flash via ITCM alias as virtual"},{"line_number":65,"context_line":"flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME"},{"line_number":66,"context_line":""},{"line_number":67,"context_line":"if { [info exists QUADSPI ] } {"},{"line_number":68,"context_line":"   set a [llength [flash list]]"},{"line_number":69,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":70,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_fcc92156","line":67,"in_reply_to":"8e7fc396_7c2751b2","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"tcl/target/stm32l4x.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"if { [info exists QUADSPI ] } {"},{"line_number":54,"context_line":"   set a [llength [flash list]]"},{"line_number":55,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":56,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_3c21d99a","line":53,"updated":"2019-06-26 05:41:10.000000000","message":"\u0026\u0026 $QUADSPI","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"if { [info exists QUADSPI ] } {"},{"line_number":54,"context_line":"   set a [llength [flash list]]"},{"line_number":55,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":56,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_9cd6edf5","line":53,"in_reply_to":"8e7fc396_3c21d99a","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":55,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":56,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"},{"line_number":57,"context_line":"} else {"},{"line_number":58,"context_line":"   if { [info exists OCTOSPI1 ] } {"},{"line_number":59,"context_line":"      set a [llength [flash list]]"},{"line_number":60,"context_line":"      set _OCTOSPINAME1 $_CHIPNAME.octospi1"},{"line_number":61,"context_line":"      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_dc3545d9","line":58,"updated":"2019-06-26 05:41:10.000000000","message":"\u0026\u0026 $OCTOSPI1","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":55,"context_line":"   set _QSPINAME $_CHIPNAME.qspi"},{"line_number":56,"context_line":"   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"},{"line_number":57,"context_line":"} else {"},{"line_number":58,"context_line":"   if { [info exists OCTOSPI1 ] } {"},{"line_number":59,"context_line":"      set a [llength [flash list]]"},{"line_number":60,"context_line":"      set _OCTOSPINAME1 $_CHIPNAME.octospi1"},{"line_number":61,"context_line":"      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_bcd3a904","line":58,"in_reply_to":"8e7fc396_dc3545d9","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","unresolved":false,"context_lines":[{"line_number":60,"context_line":"      set _OCTOSPINAME1 $_CHIPNAME.octospi1"},{"line_number":61,"context_line":"      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"},{"line_number":62,"context_line":"   }"},{"line_number":63,"context_line":"   if { [info exists OCTOSPI2 ] } {"},{"line_number":64,"context_line":"      set b [llength [flash list]]"},{"line_number":65,"context_line":"      set _OCTOSPINAME2 $_CHIPNAME.octospi2"},{"line_number":66,"context_line":"      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_fc3281ee","line":63,"updated":"2019-06-26 05:41:10.000000000","message":"\u0026\u0026 $OCTOSPI2","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","unresolved":false,"context_lines":[{"line_number":60,"context_line":"      set _OCTOSPINAME1 $_CHIPNAME.octospi1"},{"line_number":61,"context_line":"      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000"},{"line_number":62,"context_line":"   }"},{"line_number":63,"context_line":"   if { [info exists OCTOSPI2 ] } {"},{"line_number":64,"context_line":"      set b [llength [flash list]]"},{"line_number":65,"context_line":"      set _OCTOSPINAME2 $_CHIPNAME.octospi2"},{"line_number":66,"context_line":"      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"8e7fc396_5c00556d","line":63,"in_reply_to":"8e7fc396_fc3281ee","updated":"2019-07-23 20:46:58.000000000","message":"Ok","commit_id":"4909b1f80721ff8630bbdbdcd2f63c9eaecee796"}],"tcl/target/stm32l5x.cfg":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# script for stm32l5x family"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# stm32l5 devices support both JTAG and SWD transports."},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"source [find target/swj-dp.tcl]"},{"line_number":7,"context_line":"source [find mem_helper.tcl]"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"if { [info exists CHIPNAME] } {"},{"line_number":10,"context_line":"   set _CHIPNAME $CHIPNAME"},{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32l5x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Work-area is a space in RAM used for flash programming"},{"line_number":18,"context_line":"# Smallest current target has 64kB ram, use 32kB by default to avoid surprises"},{"line_number":19,"context_line":"if { [info exists WORKAREASIZE] } {"},{"line_number":20,"context_line":"   set _WORKAREASIZE $WORKAREASIZE"},{"line_number":21,"context_line":"} else {"},{"line_number":22,"context_line":"   set _WORKAREASIZE 0x8000"},{"line_number":23,"context_line":"}"},{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#jtag scan chain"},{"line_number":26,"context_line":"if { [info exists CPUTAPID] } {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_dfe76e3a","line":23,"range":{"start_line":1,"start_character":0,"end_line":23,"end_character":1},"updated":"2020-03-11 13:49:29.000000000","message":"i guess this is the same as in #5344\nfor reference please see this one : http://openocd.zylin.com/#/c/5510/3/tcl/target/stm32l5x.cfg","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"2c50a639b367596f99b9e8e4cd210d8f804e3431","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# script for stm32l5x family"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# stm32l5 devices support both JTAG and SWD transports."},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"source [find target/swj-dp.tcl]"},{"line_number":7,"context_line":"source [find mem_helper.tcl]"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"if { [info exists CHIPNAME] } {"},{"line_number":10,"context_line":"   set _CHIPNAME $CHIPNAME"},{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32l5x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Work-area is a space in RAM used for flash programming"},{"line_number":18,"context_line":"# Smallest current target has 64kB ram, use 32kB by default to avoid surprises"},{"line_number":19,"context_line":"if { [info exists WORKAREASIZE] } {"},{"line_number":20,"context_line":"   set _WORKAREASIZE $WORKAREASIZE"},{"line_number":21,"context_line":"} else {"},{"line_number":22,"context_line":"   set _WORKAREASIZE 0x8000"},{"line_number":23,"context_line":"}"},{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#jtag scan chain"},{"line_number":26,"context_line":"if { [info exists CPUTAPID] } {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_7f33bac0","line":23,"range":{"start_line":1,"start_character":0,"end_line":23,"end_character":1},"in_reply_to":"2e76d7c5_dfe76e3a","updated":"2020-03-12 09:01:56.000000000","message":"Right, this file shouldn\u0027t go into this patch at all, but for testing with the L5 it was necessary. Sort of chicken and egg problem ...","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","unresolved":false,"context_lines":[{"line_number":27,"context_line":"   set _CPUTAPID $CPUTAPID"},{"line_number":28,"context_line":"} else {"},{"line_number":29,"context_line":"   if { [using_jtag] } {"},{"line_number":30,"context_line":"      # See STM Document RM0438"},{"line_number":31,"context_line":"      # Section 51.2.10 - corresponds to Cortex-M33 r0p0"},{"line_number":32,"context_line":"      set _CPUTAPID 0x0be11477"},{"line_number":33,"context_line":"   } {"},{"line_number":34,"context_line":"      set _CPUTAPID 0x0be12477"},{"line_number":35,"context_line":"   }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_bfeab203","line":32,"range":{"start_line":30,"start_character":6,"end_line":32,"end_character":30},"updated":"2020-03-11 13:49:29.000000000","message":"RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers, Corresponds to Cortex®-M33 JTAG debug port ID code (0x0ba04477)","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","unresolved":false,"context_lines":[{"line_number":94,"context_line":""},{"line_number":95,"context_line":"$_TARGETNAME configure -event examine-end {"},{"line_number":96,"context_line":"\t# DBGMCU_CR |\u003d DBG_STANDBY | DBG_STOP | DBG_SLEEP"},{"line_number":97,"context_line":"\tmmw 0xE0042004 0x00000007 0"},{"line_number":98,"context_line":""},{"line_number":99,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":100,"context_line":"\t# DBGMCU_APB1_FZ |\u003d DBG_IWDG_STOP | DBG_WWDG_STOP"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_5ffcbed5","line":97,"range":{"start_line":97,"start_character":5,"end_line":97,"end_character":15},"updated":"2020-03-11 13:49:29.000000000","message":"DBGMCU base is 0xE0044004","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","unresolved":false,"context_lines":[{"line_number":98,"context_line":""},{"line_number":99,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":100,"context_line":"\t# DBGMCU_APB1_FZ |\u003d DBG_IWDG_STOP | DBG_WWDG_STOP"},{"line_number":101,"context_line":"\tmmw 0xE0042008 0x00001800 0"},{"line_number":102,"context_line":"}"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"$_TARGETNAME configure -event trace-config {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_ffe02a27","line":101,"range":{"start_line":101,"start_character":5,"end_line":101,"end_character":15},"updated":"2020-03-11 13:49:29.000000000","message":"idem","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","unresolved":false,"context_lines":[{"line_number":105,"context_line":"\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync"},{"line_number":106,"context_line":"\t# change this value accordingly to configure trace pins"},{"line_number":107,"context_line":"\t# assignment"},{"line_number":108,"context_line":"\tmmw 0xE0042004 0x00000020 0"},{"line_number":109,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":8,"id":"2e76d7c5_1fde4671","line":108,"range":{"start_line":108,"start_character":15,"end_line":108,"end_character":16},"updated":"2020-03-11 13:49:29.000000000","message":"idem","commit_id":"c02867197d088fac376476393ca7a5dbd37950fc"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"78ef6cb4a476472a1bfb11cb669f686b7181dccf","unresolved":false,"context_lines":[{"line_number":51,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# declare non-secure flash"},{"line_number":54,"context_line":"flash bank $_CHIPNAME.flash_ns stm32l5x 0 0 0 0 $_TARGETNAME"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"if { [info exists OCTOSPI1] \u0026\u0026 $OCTOSPI1 } {"},{"line_number":57,"context_line":"\tset a [llength [flash list]]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":13,"id":"ceda9b01_56fb6411","line":54,"in_reply_to":"","updated":"2020-10-31 09:23:51.000000000","message":"here, the flash driver should be stm32l4x\n\nI prefer to remove that line since the actual l4 driver does not support l5 (waiting for #5509, I can propose another PS applying Antonio\u0027s proposal tomorrow)","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"abfd260a5bcb50ec68aa07537a9971dd14711602","unresolved":false,"context_lines":[{"line_number":51,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# declare non-secure flash"},{"line_number":54,"context_line":"flash bank $_CHIPNAME.flash_ns stm32l5x 0 0 0 0 $_TARGETNAME"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"if { [info exists OCTOSPI1] \u0026\u0026 $OCTOSPI1 } {"},{"line_number":57,"context_line":"\tset a [llength [flash list]]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":13,"id":"ceda9b01_f66058ce","line":54,"in_reply_to":"ceda9b01_56fb6411","updated":"2020-11-01 16:16:13.000000000","message":"Well, yes, that is a problem. But replacing this with l4 doesn\u0027t help, as it won\u0027t work either. To me the only clean solution is to remove both \u0027stm32l5x.cfg\u0027 and \u0027stm32l562e-disco.cfg\u0027 entirely and move this to a different patch.\n\nOr maybe, you could move these to your l5 patchset?","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"b4c4901165fcfdb2a576598d82873dcfe26bafd4","unresolved":false,"context_lines":[{"line_number":51,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# declare non-secure flash"},{"line_number":54,"context_line":"flash bank $_CHIPNAME.flash_ns stm32l5x 0 0 0 0 $_TARGETNAME"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"if { [info exists OCTOSPI1] \u0026\u0026 $OCTOSPI1 } {"},{"line_number":57,"context_line":"\tset a [llength [flash list]]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":13,"id":"ceda9b01_36fca0d5","line":54,"in_reply_to":"ceda9b01_f66058ce","updated":"2020-11-01 18:55:06.000000000","message":"just removing this line would solve the issue.\nwe will be able to program only the external memory.\n\nthe internal flash support will come later.","commit_id":"6f0bdace215fedbed1f80ef56b7b65fb3ece5703"}]}