)]}'
{"id":"openocd~master~I54858fbbe8758c3a5fe58812e93f5f39514704f8","project":"openocd","branch":"master","hashtags":[],"change_id":"I54858fbbe8758c3a5fe58812e93f5f39514704f8","subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","status":"MERGED","created":"2018-01-02 15:12:03.000000000","updated":"2020-11-08 22:46:00.000000000","submitted":"2020-11-08 22:46:00.000000000","submitter":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"total_comment_count":303,"unresolved_comment_count":0,"has_review_started":true,"submission_id":"4321-1604875560050-64347c82","meta_rev_id":"a88b7cc2d3c6240b1dcbae960da7606a3cd0cd82","_number":4321,"owner":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"actions":{},"labels":{"Verified":{"approved":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"value":0,"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},{"value":0,"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},{"value":0,"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},{"value":0,"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},{"value":0,"_account_id":1001673,"name":"Claudio Lanconelli"},{"value":0,"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},{"value":0,"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"value":1,"date":"2020-11-08 22:46:00.000000000","permitted_voting_range":{"min":1,"max":1},"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"value":0,"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},{"value":0,"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"}],"values":{"-1":"Fails"," 0":"No score","+1":"Verified"},"description":"","default_value":0},"Code-Review":{"approved":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"all":[{"value":0,"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},{"value":0,"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},{"value":0,"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},{"value":0,"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},{"value":0,"_account_id":1001673,"name":"Claudio Lanconelli"},{"value":1,"date":"2020-11-08 22:46:00.000000000","permitted_voting_range":{"min":1,"max":1},"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},{"value":2,"date":"2020-11-08 22:46:00.000000000","permitted_voting_range":{"min":2,"max":2},"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"value":0,"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"value":2,"date":"2020-11-08 22:46:00.000000000","permitted_voting_range":{"min":2,"max":2},"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},{"value":0,"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"}],"values":{"-2":"This shall not be merged","-1":"I would prefer this is not merged as is"," 0":"No score","+1":"Looks good to me, but someone else must approve","+2":"Looks good to me, approved"},"description":"","default_value":0}},"removable_reviewers":[],"reviewers":{"REVIEWER":[{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},{"_account_id":1001673,"name":"Claudio Lanconelli"},{"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"}]},"pending_reviewers":{},"reviewer_updates":[{"updated":"2018-01-21 07:02:38.000000000","updated_by":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"reviewer":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"state":"REVIEWER"},{"updated":"2019-04-29 07:03:59.000000000","updated_by":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"reviewer":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"state":"REVIEWER"},{"updated":"2019-05-15 12:40:33.000000000","updated_by":{"_account_id":1001673,"name":"Claudio Lanconelli"},"reviewer":{"_account_id":1001673,"name":"Claudio Lanconelli"},"state":"REVIEWER"},{"updated":"2020-03-12 12:10:51.000000000","updated_by":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"reviewer":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"state":"REVIEWER"},{"updated":"2020-07-03 09:18:10.000000000","updated_by":{"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},"reviewer":{"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},"state":"REVIEWER"},{"updated":"2020-11-01 17:27:33.000000000","updated_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"reviewer":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"state":"REVIEWER"},{"updated":"2020-11-01 18:55:06.000000000","updated_by":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"reviewer":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"state":"REVIEWER"},{"updated":"2020-11-02 18:54:03.000000000","updated_by":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"reviewer":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"state":"REVIEWER"},{"updated":"2020-11-08 22:46:00.000000000","updated_by":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"reviewer":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"state":"REVIEWER"}],"messages":[{"id":"a7d8921ce22db8f23e3c8b5a62f967a5efadb603","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-01-02 15:12:03.000000000","message":"Uploaded patch set 1.","accounts_in_message":[],"_revision_number":1},{"id":"ca7cffe302615f8c7f080b1e345e43da549a4f19","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-01-02 15:29:59.000000000","message":"Patch Set 1: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/8896/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/9523/ : SUCCESS","accounts_in_message":[],"_revision_number":1},{"id":"ac5705ba1903ea5a1b3ed099ecdf9ba71f90f0f3","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-01-02 15:40:19.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"bd2994d2b6a1ef7c86fbbf096ab0679d4fc23725","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-01-02 15:59:08.000000000","message":"Patch Set 2: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/8897/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/9524/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"8a7f3ac66c966397dfb692f726a534ad492fae60","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-01-02 16:01:39.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"28bcd101534f7b60ef772521ac1b9e0d71272f98","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-01-02 16:20:31.000000000","message":"Patch Set 3: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/9525/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/8898/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"6fedbf28dd85434e4487dae07ef58cb82a00b5f7","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-01-16 14:47:46.000000000","message":"Patch Set 3:\n\nAndreas, thanks for a HUGE work.\nI tested it with STM32F723E-disco. No functional problems spotted and flashing is really fast. The only problem was failing verify_image perhaps unrelated to your driver.\n\nWhat I do not like is the qspi configuration embedded unconditionally to board and even worse to target configs. Any MCU target cfg should not configure a QSPI flash bank as it depends on particular board. I know your driver copes with non detected memory by setting zero sized flash bank and no error is returned.\n\nConsider setting some tcl variables for qspi mapping and peripheral base in target cfg. They get used in turn in a boad cfg.\n\nAlso \u0027reset init\u0027 handler with qspi init is quite long. I\u0027d recommend to move qspi related part to an extra tcl proc qspi_init and call it optionally if a tcl variable like USE_QSPI is set or let the user call it manually.","accounts_in_message":[],"_revision_number":3},{"id":"9db8a79b52b38c5e6ca4ae4f4bfdaba913803bb3","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-01-16 15:35:11.000000000","message":"Patch Set 3:\n\n(4 comments)","accounts_in_message":[],"_revision_number":3},{"id":"6e4bd383acec2d38cc13643adf2f8fcac817911e","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-01-20 18:36:26.000000000","message":"Patch Set 3:\n\n(4 comments)\n\nF723 verify issue: Reproducible or spurious? Details? So far I\u0027ve encountered only read/verify problems, and only for H743 and L4R5/9 for the very last word at end of bank. Disappears when register setting of memory size is bigger than real size (i. e. bank mirrored twice). Maybe silicon bug, or problem in openocd\u0027s read accesses, prefetch or ACK/WAIT related. \n\nRegarding the target cfgs: all current derivatives of L4/L4+,F7,H7 have qspi. Memory and peripheral address spaces are fixed und not usable in any other way, so \"cut\" into silicon. That\u0027s an intrinsinc target property, and only this is in the *target* cfgs.\n\nOnly F4 is different, some derivatives don\u0027t include qspi, and indeed  there are some older variants with conflicting addresses (FSMC). That has to be resolved. \n\nExtra cfgs would clutter the package with a bunch of additional files and (maybe) an additional include level. But where would be an advantage (except for F4, of course)?\n\nRegardings board cfgs: For the discos everything is fixed, too, so no obious reason not to include the innitialization. For the nucleos you\u0027re quite right, although they\u0027re intended to be samples only, not for real usage. So move to contrib?\n\nRegarding the init stuff you\u0027ve a good point. I\u0027ll move this into separate proc.","accounts_in_message":[],"_revision_number":3},{"id":"d0ddb67a622c81a26533e4b705e8cc603c23d69c","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-01-21 08:01:41.000000000","message":"Patch Set 3:\n\n\u003e Regarding the target cfgs: all current derivatives of L4/L4+,F7,H7\n \u003e have qspi. Memory and peripheral address spaces are fixed und not\n \u003e usable in any other way, so \"cut\" into silicon. That\u0027s an\n \u003e intrinsinc target property, and only this is in the *target* cfgs.\n\nYes, interface is there. But anyway the rule of thumb is:\nno flash, no bank definition.\n\n- an inexperienced user may report the visible zero sized bank as a bug\n- in theory there might be other device than QSPI flash (e.g. FPGA) connected to QSPI interface. This device may not implement SPIFLASH_READ_ID command and gets upset by the probe.","accounts_in_message":[],"_revision_number":3},{"id":"456b4d8b10d11c78b647dd2a1a01cb2932007e28","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-01-21 20:36:38.000000000","message":"Patch Set 3:\n\n\u003e F723 verify issue: Reproducible or spurious? Details?\n\nI was not able to replicate the issue after OpenOCD rebuild. So don\u0027t bother with it.","accounts_in_message":[],"_revision_number":3},{"id":"071349753a29642503201d0fabcab5d076a641ef","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-02-03 13:44:14.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"c56dd2f9f8a9710a8717696a245e0365c813f483","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-02-03 14:02:05.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/9689/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/9059/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"4e50c53ea665c75dfeab266362f9cb8f7a1f53a8","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-02-03 15:42:22.000000000","message":"Patch Set 4:\n\n(3 comments)","accounts_in_message":[],"_revision_number":4},{"id":"d95d2493b3e899d8e3393f40eb44d7e4e723f51a","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-02-03 16:02:53.000000000","message":"Patch Set 4:\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"70cc507dca73e130c83330a5c2dbb6c0855bc95e","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-02-03 16:15:54.000000000","message":"Patch Set 4:\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"289070b71491ed0e8c72cdb70d9c4251e8c3ae53","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-02-19 12:18:54.000000000","message":"Patch Set 4:\n\nI tested with stm32l476g-disco and found write alignment problem: If write starts unaligned to page and crosses the end of page, algo hangs. I rechecked on stm32f723e-disco and it has same problem.\nIf it\u0027s not an error in the flash write algo and write should be really aligned, check http://openocd.zylin.com/4399","accounts_in_message":[],"_revision_number":4},{"id":"097380e065e38dabd2112a9ebedc6dbfc1e51973","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2018-10-14 22:56:00.000000000","message":"Patch Set 4: Code-Review-1\n\n(52 comments)\n\nLots of comments on the code. Also, could you change tcl/target/stm32h7x.cfg the same way you changed stm32f7x.cfg? Although note that the H7s have the control registers at 0x52005000 instead of 0xA0001000. Thanks! I like the look of this in general, just details to sort out.","accounts_in_message":[],"_revision_number":4},{"id":"81c638558f35a9658d975ace764318b63c412d79","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-11-02 10:38:36.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"376eff230cd9be9706a380725b871a3f68a4d3b4","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-11-02 10:56:50.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/10781/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10133/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"1d2413116524de4c8fa156e74ccea7174430d450","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-11-02 19:20:01.000000000","message":"Patch Set 4:\n\n(48 comments)\n\nThanks for the comments. I\u0027ve reviewed most of them, regarding the others I\u0027ll need some more time.\n\nPatch set 5 does *NOT* include these changes, but only the aligment fix and various small updates for FRAMs. \n\nAdapting stm32h7x.cfg in a similar way as for f7 will be a bit tricky as single/double bank handling is different.","accounts_in_message":[],"_revision_number":4},{"id":"37e8dc0a8b0b919753c07ae63a2d1ec640f0bf6d","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2018-11-14 20:56:01.000000000","message":"Patch Set 4:\n\n(3 comments)","accounts_in_message":[],"_revision_number":4},{"id":"f7161441868c89dca5e6bdff23cc7e2f9ef93bb8","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-15 09:19:24.000000000","message":"Patch Set 4:\n\n\u003e I’m still mildly opposed to having the protect command set implemented \n\u003e but not actually do anything (at the hardware level); to me it seems\n\u003e misleading (“But I ran the protect command and it worked!\n\u003e Why isn’t my chip write protected‽”) ...\n\nYes, this is close to my opinion. On the other hand there are some other drivers with the same soft-protect functionality (mostly SPI flash related). And some user might benefit from using soft-protection to secure some part of flash during writing of a weird multi-segment hex or elf... who knows.\nI\u0027m not going to block any variant. My recommendation is:\na) don\u0027t implement protection in software only\nb) if you do, start in unlocked state and warn the user if protect command is used","accounts_in_message":[],"_revision_number":4},{"id":"a988adcf2145121acb28391e9ca20c7faf24c7b3","author":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"real_author":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"date":"2019-04-26 11:06:33.000000000","message":"Patch Set 5:\n\nHi,\n\nI just tried out the latest version of this patch (i.e. directly checked out original commit \na20cc9de2c63d7211a49cbe1231a06808ab89415) and compiled on Ubuntu 18.10.\n\n\nOn the STM32F746G-DISCO board (using  board/stm32f746g-disco.cfg)\nthe flashing of the external QSPI flash works correctly, however during the \u0027verify\u0027 step hardware seems to crash:\n\n\n** Programming Started **\nauto erase enabled\nInfo : device id \u003d 0x10016449\nInfo : flash size \u003d 1024kbytes\ntarget halted due to breakpoint, current mode: Thread \nxPSR: 0x61000000 pc: 0x20000044 msp: 0x20040000\nInfo : flash1 \u0027micron n25q128\u0027 id \u003d 0x18ba20 size \u003d 16384kbytes\ntarget halted due to breakpoint, current mode: Thread \nxPSR: 0x21000000 pc: 0x200000d8 msp: 0x20040000\nwrote 5373952 bytes from file firmware.elf in 94.322731s (55.639 KiB/s)\n** Programming Finished **\n** Verify Started **\ntarget halted due to breakpoint, current mode: Thread \nxPSR: 0x61000000 pc: 0x2000002e msp: 0x20040000\ntarget halted due to breakpoint, current mode: Thread \nxPSR: 0x61000000 pc: 0x2000002e msp: 0x20040000\nError: timed out while waiting for target halted\nError: timed out while waiting for target halted\nError: error executing cortex_m crc algorithm\nError: jtag status contains invalid mode value - communication failure\nPolling target stm32f7x.cpu failed, trying to reexamine\nExamination failed, GDB will be halted. Polling again in 100ms\n** Verify Failed **\nshutdown command invoked\n\n\nIf I reboot the board after the failed \u0027verify\u0027 step everything is all right and the QSPI flash shows the correct content.","accounts_in_message":[],"_revision_number":5},{"id":"176d301388f9bcc0c304ac67220ae26560b358a7","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-04-26 15:01:59.000000000","message":"Patch Set 5:\n\nCould you please supply:\n- exact command line arguments \n- value of all option bytes \n- debug log (start openocd with additional \u0027-d3\u0027)\n\nDoes this problem occur every time or occasionally?\nDoes a prior mass erase of F746 and SPI flash (instead of auto-erase) affect whether this occurs?\n\nBTW I\u0027m wondering about the speed, just 55 kB/s. On a similar sized image I get about 85 kB/s with auto erase and 150 kB/s without erase. If you get a much lower rate when not using auto erase but prior mass erase, there must be something wrong with the configuration. The programming speed is more or less only governed by SWD clock, and that\u0027s set to 4 MHz in the cfg.\n\nIt might be better to open a ticket and post the info there.","accounts_in_message":[],"_revision_number":5},{"id":"cd04f749b741ded1f1c1a44d6c51d7147cfb4d4e","author":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"real_author":{"_account_id":1001666,"name":"David Kühling","username":"dvdkhlng"},"date":"2019-04-29 07:03:59.000000000","message":"Patch Set 5:\n\n[..]\n\u003e It might be better to open a ticket and post the info there.\n\nOpened issue #234 on openocd sourceforge and will post my reply there.\n\n[1] https://sourceforge.net/p/openocd/tickets/234/","accounts_in_message":[],"_revision_number":5},{"id":"546c7dfb6804da1901db36a26283455964e054da","author":{"_account_id":1001673,"name":"Claudio Lanconelli"},"real_author":{"_account_id":1001673,"name":"Claudio Lanconelli"},"date":"2019-05-15 12:40:33.000000000","message":"Patch Set 5: Code-Review+1\n\nTested OK on STM32F746","accounts_in_message":[],"_revision_number":5},{"id":"a18c80a384b19b1c944a13d6d512656f818a0193","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2019-05-22 00:15:27.000000000","message":"Patch Set 5: Code-Review-1\n\nBefore merging, could you take a quick look at my comment here \u003chttp://openocd.zylin.com/#/c/4321/4/src/flash/nor/stmqspi.c@691\u003e and see if what I’m saying makes sense or if I’m mistaken somehow?","accounts_in_message":[],"_revision_number":5},{"id":"f1ea7c0e27390b4d269b39c953becd46b7168f96","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-05-22 06:32:08.000000000","message":"Patch Set 4:\n\n(1 comment)\n\nApart from addressing the comments, some changes to follow shortly:\n- don\u0027t use memory-mapped read (silicon bug in L4+, H7, MP1)\n- \u0027flash verify_image\u0027 as normal \u0027verify_image\u0027 uses memory-mapped read\n- basic SFDP support","accounts_in_message":[],"_revision_number":4},{"id":"bb1379b4ee864f8bdc7d8e1419272fe84663f9ad","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2019-05-22 16:59:19.000000000","message":"Patch Set 4:\n\n\u003e Apart from addressing the comments, some changes to follow shortly:\n \u003e - don\u0027t use memory-mapped read (silicon bug in L4+, H7, MP1)\n\nYou mean F7, not H7, right? That erratum appears in the F7 sheet but not H7. Which doesn’t mean it isn’t there in the H7 as well…","accounts_in_message":[],"_revision_number":4},{"id":"a3b60e91ce6f145d730aba8ee9075ef4f8299d6f","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-06-25 16:29:28.000000000","message":"Uploaded patch set 6.","accounts_in_message":[],"_revision_number":6},{"id":"d6e0e2d4bda8ce3c0ef5039fda12f67ad6372b9b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-06-25 16:51:09.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11929/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11240/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"0f33f9ec37bd574c58f1e30f88d2d8e28e597630","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2019-06-26 05:41:10.000000000","message":"Patch Set 6: Code-Review-1\n\n(64 comments)\n\nLots of comments here. I didn’t bother looking in any detail at the OCTOSPI parts as I don’t know that peripheral nor have any hardware equipped with it. Some of the comments I made regarding QUADSPI stuff might also apply to OCTOSPI code.","accounts_in_message":[],"_revision_number":6},{"id":"6d063fdec0c60800a882e8c29062c0ccc4810f52","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-07-23 20:46:58.000000000","message":"Patch Set 6:\n\n(64 comments)\n\nThanks for the comments. Hopefully I didn\u0027t miss any ...","accounts_in_message":[],"_revision_number":6},{"id":"834f90b0b75a4e473086e6a7a99aa4e860d2b0bb","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-07-23 20:47:16.000000000","message":"Uploaded patch set 7.","accounts_in_message":[],"_revision_number":7},{"id":"d16a70fc9826a009aad13feeca95ccb3ea58183d","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-07-23 21:08:36.000000000","message":"Patch Set 7: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11989/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11298/ : SUCCESS","accounts_in_message":[],"_revision_number":7},{"id":"eddd4135e2abb4a00b2e5501d3e4f07171967e7e","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2019-07-29 19:35:48.000000000","message":"Patch Set 6:\n\n(6 comments)\n\nJust a few things remaining (I commented on patch set 6 after looking at the diff between the two sets; I’m not too comfortable with Gerrit so not sure if it would have shown me all my comments against patch set 7).","accounts_in_message":[],"_revision_number":6},{"id":"c27bf2f0d0d93be69f33a9b083b64e5cf245f4ff","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2019-07-29 19:47:31.000000000","message":"Patch Set 7: Code-Review-1\n\n(2 comments)\n\nThese two items, plus the ones from my previous comment.","accounts_in_message":[],"_revision_number":7},{"id":"c6e5f5a6f7353a511bcb886edf59669d3d5aee2e","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-01-07 20:00:11.000000000","message":"Patch Set 7:\n\nJust checking if this is still being worked on?","accounts_in_message":[],"_revision_number":7},{"id":"a5ce4d995ddf78e9e8454181cd3233b04610bd56","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-01-07 20:18:12.000000000","message":"Patch Set 7:\n\nWell , of course ;-) There is H7A3/H7B3 with OctoSPI knocking on the door. Hopefully I\u0027ll get hands on them by end of this month ...","accounts_in_message":[],"_revision_number":7},{"id":"faab3029b67ee0f1ad455c5570e2403f0de59275","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-01-07 20:34:26.000000000","message":"Patch Set 7:\n\nAwesome! Let me know if you’d like me to help addressing any of the review comments (I *did* make quite a lot, so I think it’s fair to offer some time to help work on them too).","accounts_in_message":[],"_revision_number":7},{"id":"e82ac73711ecf2f5bb22942a90fb3d0afb0ba59b","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-01-23 07:47:35.000000000","message":"Patch Set 7:\n\nContrary to my plan, there will be no further update on topic:\nIt seems to be impossible to get samples of new hardware (H7B3) due to US export control.","accounts_in_message":[],"_revision_number":7},{"id":"494a2a3909989d88524d0c2071295629c03d4d99","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-01-23 07:47:43.000000000","message":"Abandoned","accounts_in_message":[],"_revision_number":7},{"id":"7be62da86495602424d03a1259f817781c496723","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-01-29 10:18:45.000000000","message":"Patch Set 7:\n\nAndreas,\n\nfirst http://openocd.zylin.com/#/c/3162/ was abandoned \nthen http://openocd.zylin.com/#/c/3918/ is abandoned\nand now I surprised this change is abandoned too.\n\nI was desperately hoping to have this great feature merged into mainline.\nI hope you can consider ignoring he STM32H7A/B and continue working this change.\nAnd then you can add other boards (including the H7B3-DK) in separated patches.\n\nPlease keep up the good work ;)","accounts_in_message":[],"_revision_number":7},{"id":"b6f5375043c6fe835da3e0ccff59638dfc98abbc","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-01-29 10:53:18.000000000","message":"Patch Set 7:\n\nUnfortunately it\u0027s not only the H7B3-DK. The very same applies\nto H750-DK (although that\u0027s more or less identical to the H745-DK) and L562-DK. In particular, the H7B3 and L562 feature an OctoSPI chip, which is rather difficult to get. Alternatives like the MT35xxxx are no option either, as I can\u0027t get a datasheet without NDA. So using a Nucleo-H7A3 and -L552 (both of which I already got) with a suitable prototype board doesn\u0027t work either.\n\nI\u0027m still hoping ST will manage to complete the paperwork with BSI, but otherwise ... Simply ridiculous: The H750-DK is export restricted, whereas the H745-DK and the bare H750 chips are not, both I got without trouble and even without signing an end user certificate.\n\nFlooding this repository with one tiny little drop onto another isn\u0027t very useful I guess, so I\u0027ll wait for some time and see ...","accounts_in_message":[],"_revision_number":7},{"id":"850569632f09edddbd3eeb5cf31d87eb407ef10a","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-01-29 18:38:31.000000000","message":"Patch Set 7:\n\nPersonally, I was planning to take this patch over and finish it. I don’t have an OCTOSPI-equipped part, nor really care about it, but I want the QUADSPI part.","accounts_in_message":[],"_revision_number":7},{"id":"8f140d5a2af0d0a3b5eaa1284a5c32faff5b9a1a","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-02-04 10:08:42.000000000","message":"Patch Set 7:\n\nAndreas, I got one H7B3-DK, If you can provide a blind implementation then I can validate it :)","accounts_in_message":[],"_revision_number":7},{"id":"87c3a06aad7c74efe10300998226a645c730cb4d","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-02-04 12:44:24.000000000","message":"Patch Set 7:\n\nTarek, thanks for your offer. This would be indeed very helpful. As the RM is available now, I\u0027ll start as soon as possible, probably next week.","accounts_in_message":[],"_revision_number":7},{"id":"6d986afebefe541aeac76e30cfdca0f16df4d931","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-02-04 13:31:24.000000000","message":"Patch Set 7:\n\n\u003e Tarek, thanks for your offer. This would be indeed very helpful. As\n \u003e the RM is available now, I\u0027ll start as soon as possible, probably\n \u003e next week.\n\ngood, I\u0027m preparing the STM32H7A/B support for upstream too.\nlike I did here: https://github.com/STMicroelectronics/OpenOCD","accounts_in_message":[],"_revision_number":7},{"id":"02c737888f305713e44a4b2d55f4c7fdbb08586c","author":{"_account_id":1001748,"name":"Alistair Buxton","email":"a.j.buxton@gmail.com","username":"ali1234"},"real_author":{"_account_id":1001748,"name":"Alistair Buxton","email":"a.j.buxton@gmail.com","username":"ali1234"},"date":"2020-02-08 14:07:14.000000000","message":"Patch Set 7:\n\nI\u0027m using this patch set with 32blit, which is a board based on STM32H750. I needed a custom config and while hunting for that I found some other repositories where the config initializes QSPI from `reset-end` instead of `reset-init`. I found that this causes a race condition when you issue a `reset run`: the CPU is not halted and then the script will write registers at the same time as user code is writing them. This seems to cause register corruption and prevents the device from jumping into external flash code.\n\nThe earliest I can find is here: https://github.com/sysprogs/openocd/blob/63f1d12608295e04f915ea5b07c4b80315c262ac/tcl/target/stm32h7x_dual_core.cfg#L258\n\nSysprogs is part of VisualGDB. The commit claims to be ported from the AC6 (System Workbench repository) but after grepping every commit in that repository I cannot find that config file.\n\nThe usage of reset-end has propagated into this repository:\n\nhttps://github.com/AndrewCapon/32BlitMacOpenOCD/blob/master/32blitdap.cfg#L212\n\nI have reported the problem to both repositories:\n\nhttps://github.com/AndrewCapon/32BlitMacOpenOCD/issues/1\n\nhttps://github.com/sysprogs/openocd/issues/5\n\nI don\u0027t expect you to do anything abut this, I am just adding this as a note for the next person who hits this problem.\n\nAfter I changed the config to use reset-init, the patch set itself works fine.","accounts_in_message":[],"_revision_number":7},{"id":"2ae2f32b78d6735e787dc5263d0e07add5a066ed","author":{"_account_id":1001673,"name":"Claudio Lanconelli"},"real_author":{"_account_id":1001673,"name":"Claudio Lanconelli"},"date":"2020-02-13 17:09:11.000000000","message":"Patch Set 7:\n\n\u003e Christopher Head\n\u003e\n\u003e Patch Set 7:\n\u003e\n\u003e Personally, I was planning to take this patch over and finish it. I \u003e don’t have an OCTOSPI-equipped part, nor really care about it, but I \u003e want the QUADSPI part.\n\nYes, please. Take it and finish the QUADSPI part, there are parts like F746 that are several years old and still have no QUADSPI support merged. This patch risk to be a \u0027never ending story\u0027 because ST releases new stm32 parts every month! A single patch can\u0027t support all of them","accounts_in_message":[],"_revision_number":7},{"id":"02ed6dcb7124eae5aa2309383b9f8f4fcaf8f12e","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-02-13 18:34:54.000000000","message":"Patch Set 7:\n\n\u003e Yes, please. Take it and finish the QUADSPI part, there are parts\n \u003e like F746 that are several years old and still have no QUADSPI\n \u003e support merged. This patch risk to be a \u0027never ending story\u0027\n \u003e because ST releases new stm32 parts every month! A single patch\n \u003e can\u0027t support all of them\n\nFrom the message two above yours, it looks like Andreas is back on the job—doesn’t make sense IMO for two people to work on the same patch at the same time. Andreas, is that right?","accounts_in_message":[],"_revision_number":7},{"id":"d78e2a77351791b7a9b1f87adb132984c49719aa","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-02-17 18:58:52.000000000","message":"Restored","accounts_in_message":[],"_revision_number":7},{"id":"7eecc688ddfac951d18513da7c8e8584c352e17e","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-02-17 18:59:23.000000000","message":"Uploaded patch set 8.","accounts_in_message":[],"_revision_number":8},{"id":"6f844cf8c60401cc6665f260f8c1416ddc1baebb","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-02-17 19:30:40.000000000","message":"Patch Set 8: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/12558/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11855/ : SUCCESS","accounts_in_message":[],"_revision_number":8},{"id":"8ec648f30db9fb296652d62aa55f16d77c2f5e9b","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-02-17 19:40:13.000000000","message":"Patch Set 8:\n\nTarek, could you please check with stm32h7b3i-dk? And maybe you can get a stm32l562e-dk, too? With the former, I don\u0027t expect any issues, as the h7a worked \"out of the box\" in dual quad mode.\nBut the l552 was quite reluctant, apparently there are more silicon bugs than listed in the errata sheet (which is already incredibly long): Occasionally, an indirect read/write with instruction phase  only does start only when \"kicked\" by a dummy write to the address register. I hope that\u0027s a reliable workaround ...","accounts_in_message":[],"_revision_number":8},{"id":"1007320950cbc9c668fb9be9e07ff42d2efa55cc","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-02-17 20:01:10.000000000","message":"Patch Set 8:\n\n\u003e Tarek, could you please check with stm32h7b3i-dk? And maybe you can\n \u003e get a stm32l562e-dk, too? With the former, I don\u0027t expect any\n \u003e issues, as the h7a worked \"out of the box\" in dual quad mode.\n \u003e But the l552 was quite reluctant, apparently there are more silicon\n \u003e bugs than listed in the errata sheet (which is already incredibly\n \u003e long): Occasionally, an indirect read/write with instruction phase \n \u003e only does start only when \"kicked\" by a dummy write to the address\n \u003e register. I hope that\u0027s a reliable workaround ...\n\nHi Andreas, I have both boards in my desk, now it\u0027s 9 PM, will check tomorrow and let you with my findings.\nI will check also with STM32L5 experts about the behavior you described.\nWill be back to you ASAP.","accounts_in_message":[],"_revision_number":8},{"id":"564c7fa39c2431b3efa6124d64e6b6befea1c903","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2020-03-11 09:54:22.000000000","message":"Patch Set 8:\n\n(3 comments)","accounts_in_message":[],"_revision_number":8},{"id":"04cfa8c324d81c7224ab3eadcd9f5a4a2ca82d96","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-03-11 13:49:29.000000000","message":"Patch Set 8:\n\n(5 comments)\n\nAFAIK nucleo board, does not include external memories\nIMO personal setups should not be upstreamed","accounts_in_message":[],"_revision_number":8},{"id":"2c50a639b367596f99b9e8e4cd210d8f804e3431","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-03-12 09:01:56.000000000","message":"Patch Set 8:\n\n(2 comments)\n\nTarek, you\u0027re right, the nucleo cfg-files were never intended for general use, but only for testing. But I don\u0027t know a good place where they should go instead: \n./testing/examples/stmqspi or ./contrib/loaders/flash/stmqspi ?\nAs I need them frequently I don\u0027t want to keep them outside git.","accounts_in_message":[],"_revision_number":8},{"id":"c00e2f798c3475c716e4d37983b5e985dc8c7146","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2020-03-12 12:10:51.000000000","message":"Patch Set 8:\n\n(7 comments)","accounts_in_message":[],"_revision_number":8},{"id":"7a86adf488a0e557d47f01345f2c0f23642821b1","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-05-24 14:00:44.000000000","message":"Patch Set 8:\n\n(6 comments)\n\nSorry for the delay ... but didn\u0027t look after comments before sorting out a problem in DTR mode with the new octo-interfaces in L4P5, H7A/B.","accounts_in_message":[],"_revision_number":8},{"id":"dd0ca5243ebccbeeac7774ad140e7e5773fdd9a3","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-05-24 14:01:31.000000000","message":"Uploaded patch set 9.","accounts_in_message":[],"_revision_number":9},{"id":"f8eff951d13af8a4f6c6d29d885f5a9e914ae59f","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-05-24 14:37:34.000000000","message":"Patch Set 9: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13074/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12358/ : SUCCESS","accounts_in_message":[],"_revision_number":9},{"id":"7c285db3b2933d05a83332d3b0bc8de9e4ff2ef1","author":{"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},"real_author":{"_account_id":1001795,"name":"Jan Pohanka","email":"xhpohanka@gmail.com","username":"xhpohanka"},"date":"2020-07-03 09:18:10.000000000","message":"Patch Set 9:\n\nHello Andreas,\nthank you for this patch. I needed to program quadspi flash on stm32h7xx platform and this helped me. Just a note. We are using Winbond flash that cannot be switched into 4 line mode for whole time but uses 4 line read/write instructions while the other instructions are still 1 line.\nIn this patchset this is not configurable but hardcoded in \n#define QSPI_MODE\nmacro in stmqspi.c\n\nIt would be nice to have it configurable.","accounts_in_message":[],"_revision_number":9},{"id":"65c831d6adfe810bff92bb9194c103b4cf3d69b6","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-07-03 11:49:02.000000000","message":"Patch Set 9:\n\n- The idea was to keep configuration as simple as possible, so the settings are inferred from the current register constents (which one would set to memory mapped mode for the particular flash anyway for easy debugging and memory inspection). \n- Flash manufacturers are very \"creative\" in inventing obscure combinations of modes, e.g. one line for instruction, one for addresses and four line mode for data etc., even different for the various instructions.\nCombining this with other other varying attributes (e.g. 3-byte vs. 4-byte addresses) would require an unmanageable (for me ;-)) amount of tests\nto support all these possible configurations.\n- Therefore the decision was to support only three modes all: either always one line (SPI), always two lines (DPI) or always four lines (QPI), but no \"mixed\" modes. Most newer (high capacity) flash devices support both SPI and QPI line modes throughout, the \"problematic\" devices are mostly older, slower and small capacity. For these devices, there is no large performance penalty in using only one line mode (even if four line read is availble). Even for high capacity devices, the read/write speed is mainly governed by SWD/JTAG-clock, which could be hardly more than 30 MHz, say, so 2 or 3 MBytes per second is the top limit. That\u0027s not difficult to achieve even in one line mode, given a suitably chosen QSPI clock.\n- So, even SPI mode would be fairly sufficient for *ALL* devices, except that certain devices could have been set (non-volatile!) to QPI mode, so it must be at least possible to reconfigure them. This leads to at least\npartial and consequential to full QPI support.","accounts_in_message":[],"_revision_number":9},{"id":"0ed5fe3ff375d43944f4077faf52b8610470ba6f","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-09-30 14:55:47.000000000","message":"Uploaded patch set 10.","accounts_in_message":[],"_revision_number":10},{"id":"b94228fdda9b14f33219f4d4b03b1d5ba2fea8e4","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-09-30 15:34:25.000000000","message":"Patch Set 10: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13411/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12686/ : SUCCESS","accounts_in_message":[],"_revision_number":10},{"id":"3b90e3478012098f4b44ceda06ff401278278b00","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-09-30 16:00:17.000000000","message":"Patch Set 10:\n\nAt last, this ridiculous export control problem with STM32L562E-DK is settled. Surprisingly no problem with new STM32H735G-DK ...","accounts_in_message":[],"_revision_number":10},{"id":"bd5723b5d266d9ebd7b35cd756e8d98bdc2b9142","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-10-01 09:17:29.000000000","message":"Patch Set 10:\n\n\u003e At last, this ridiculous export control problem with STM32L562E-DK\n \u003e is settled. Surprisingly no problem with new STM32H735G-DK ...\n\nGread ! I strongly want this to be part of v0.11.0, if you plan to add another patch set, I can contribute on testing","accounts_in_message":[],"_revision_number":10},{"id":"c6928078bbf1f49eb69b57b532c8107e86ac170f","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-10-21 23:03:10.000000000","message":"Patch Set 10: Code-Review-1\n\n(6 comments)\n\nFunctionally this seems to work; I’ve tried reading, writing, and erasing an ordinary 8 MiB SPI Flash attached to an STM32H743 and not noticed anything broken (though that’s hardly an exhaustive test). Just a few minor stylistic and tidying comments on the code. Very excited to hopefully see this merged soon!","accounts_in_message":[],"_revision_number":10},{"id":"f9e01133ad68c98355ddceb605d722eba7461845","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-10-23 14:32:10.000000000","message":"Patch Set 10:\n\n(6 comments)\n\nThanks for the comments. Actually there were some more format strings with signed/unsigned mismatch left over.","accounts_in_message":[],"_revision_number":10},{"id":"c8aa5e3a71745227ef7ae6651c89e0310bb6ceea","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-10-23 14:32:50.000000000","message":"Uploaded patch set 11.","accounts_in_message":[],"_revision_number":11},{"id":"9248460050c539befec07dea2f6102f8a83a9f8a","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-10-23 14:38:01.000000000","message":"Patch Set 11: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/13480/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12755/ : FAILURE","accounts_in_message":[],"_revision_number":11},{"id":"e74450f2da284ba354cab62f22b92671cfd674a7","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-10-23 15:45:29.000000000","message":"Uploaded patch set 12.","accounts_in_message":[],"_revision_number":12},{"id":"77509e1052e70bf0e0ce14b197b08c5bad9ab597","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-10-23 16:22:38.000000000","message":"Patch Set 12: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13483/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12758/ : SUCCESS","accounts_in_message":[],"_revision_number":12},{"id":"f6664f2f486d2f4c026dc8ee732abfa87a54998f","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-10-23 17:41:17.000000000","message":"Patch Set 12: Code-Review+1\n\n(3 comments)\n\nA few more comments, but I’ll +1 this anyway; I’d rather see this go in without those changes if there isn’t time or you prefer not to change them, as they’re very minor.","accounts_in_message":[],"_revision_number":12},{"id":"5f5f1577a14ec9d9284ba8b802b2d9d997d92906","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-10-28 19:33:27.000000000","message":"Patch Set 12:\n\n(3 comments)\n\nApart from these changes, 2-byte alignment in dual and octal dtr modes added. More comfortable than to reject a write command.","accounts_in_message":[],"_revision_number":12},{"id":"b92e564f64d68bac3f369cfa9155dcd63ddeddbf","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-10-28 19:33:35.000000000","message":"Uploaded patch set 13.","accounts_in_message":[],"_revision_number":13},{"id":"cc21e92d10f11659c6a46c107f5e6838f788b123","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-10-28 20:08:42.000000000","message":"Patch Set 13: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13525/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12799/ : SUCCESS","accounts_in_message":[],"_revision_number":13},{"id":"b74e38eee48f7acd9a11877d027df31dcecfe57a","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-10-30 18:50:34.000000000","message":"Patch Set 13: Code-Review+1","accounts_in_message":[],"_revision_number":13},{"id":"54721541156e680eb302c92dd2d81df79fefb5d3","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2020-10-30 21:36:05.000000000","message":"Patch Set 13:\n\n(3 comments)\n\nTarek, are you ok with introduced configs? If so I\u0027d like to merge the change finally...\n\nAndreas, some last nits:","accounts_in_message":[],"_revision_number":13},{"id":"78ef6cb4a476472a1bfb11cb669f686b7181dccf","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-10-31 09:23:51.000000000","message":"Patch Set 13:\n\n(1 comment)\n\nTomas, \none issue is with stm32l5x.cfg","accounts_in_message":[],"_revision_number":13},{"id":"afc1f5e9e2fe8dbeb18f17352966cb36cee6f081","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2020-10-31 10:06:46.000000000","message":"Patch Set 13:\n\n\u003e one issue is with stm32l5x.cfg ...\n\nYes, it\u0027s reasonable.\nAndreas, please remove the reference to not yet merged driver.\nThanks!","accounts_in_message":[],"_revision_number":13},{"id":"abfd260a5bcb50ec68aa07537a9971dd14711602","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-11-01 16:16:13.000000000","message":"Patch Set 13:\n\n(4 comments)\n\nOk, everything related to STM32L5 removed.","accounts_in_message":[],"_revision_number":13},{"id":"941c7d0636ccb79446487e58869efce108de7719","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-11-01 16:17:55.000000000","message":"Uploaded patch set 14.","accounts_in_message":[],"_revision_number":14},{"id":"56eae63f4b4c9c7ec942df59593231fbc4686006","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-11-01 17:27:33.000000000","message":"Patch Set 14: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13549/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/12822/ : SUCCESS","accounts_in_message":[],"_revision_number":14},{"id":"b4c4901165fcfdb2a576598d82873dcfe26bafd4","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2020-11-01 18:55:06.000000000","message":"Patch Set 14: Code-Review+1\n\n(1 comment)\n\n\u003e Ok, everything related to STM32L5 removed.\n\nboth options are OK:\nyou can push the STM32L5 external flash support in another change.\nor just remove the line 54 of target/stm32l5x.cfg.\n\nyesterday, I have tested PS13:\nSTM32L4R9I-Disco, STM32L562E-DK, STM32H747I-Disco and STM32H7B3I-DK","accounts_in_message":[],"_revision_number":14},{"id":"f49c09907c564e8066f11439a25f842e4c809dba","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2020-11-01 19:17:47.000000000","message":"Patch Set 14: Code-Review+2\n\nThanks Andreas!","accounts_in_message":[],"_revision_number":14},{"id":"e646991bcc18183df0e64684576ea52305851839","author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"real_author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"date":"2020-11-02 18:54:03.000000000","message":"Patch Set 14: Code-Review+2","accounts_in_message":[],"_revision_number":14},{"id":"a88b7cc2d3c6240b1dcbae960da7606a3cd0cd82","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2020-11-08 22:46:00.000000000","message":"Change has been successfully cherry-picked as e44539d66c8929679321704768125df9ba7d5f67 by Tomas Vanek","accounts_in_message":[],"_revision_number":15}],"current_revision":"e44539d66c8929679321704768125df9ba7d5f67","revisions":{"412226d9b430ab7723edd6bab69d554b7b07cb0b":{"kind":"REWORK","_number":14,"created":"2020-11-01 16:17:55.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/14","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/14","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/14 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/14 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/14 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/14 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/14","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/14 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"91c4c83f44760f323f3bcab44c89ac59b4ed74c7","subject":"tcl/board: fix changed target config filenames"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-11-01 16:16:34.000000000","tz":60},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMs)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"e44539d66c8929679321704768125df9ba7d5f67":{"kind":"REWORK","_number":15,"created":"2020-11-08 22:46:00.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/21/4321/15","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/15","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/15 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/15 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/15 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/15 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/15","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/15 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"475f42051e13d64bc4d1960306ad1d2ea3c7962a","subject":"stlink: fix computation of trace prescaler"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2020-11-08 22:46:00.000000000","tz":0},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMs)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\nReviewed-on: http://openocd.zylin.com/4321\nTested-by: jenkins\nReviewed-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\nReviewed-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\nReviewed-by: Christopher Head \u003cchead@zaber.com\u003e\n"}},"fe85c0165d8111539f0929871c9ee207afd686ca":{"kind":"REWORK","_number":12,"created":"2020-10-23 15:45:29.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/12","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/12","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/12 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/12 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/12 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/12 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/12","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/12 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"5829646343d78a6779794f67cde2f7c779969afc","subject":"flash/stm32l4: add support of STM32G4 category 4 devices (G491/G4A1)"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-10-23 15:43:28.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco, STM32L562E-Disco\n  (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMs)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"6f0bdace215fedbed1f80ef56b7b65fb3ece5703":{"kind":"REWORK","_number":13,"created":"2020-10-28 19:33:35.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/13","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/13","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/13 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/13 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/13 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/13 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/13","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/13 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"c1f4d9e6e8f9cdab122db36299e039a73151ffe4","subject":"flash/nor/nrf5: unify size of HWID"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-10-28 19:29:48.000000000","tz":60},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco, STM32L562E-Disco\n  (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMs)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"88ab17c5f691ee78c8871eb0e669658090005c20":{"kind":"REWORK","_number":10,"created":"2020-09-30 14:55:47.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/10","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/10","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/10 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/10 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/10 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/10 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/10","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/10 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"051e80812b1b3bb4deabef272c12bb95f10748da","subject":"drivers/jlink: fix calculate_swo_prescaler formula"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-09-30 14:54:13.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco, STM32L562E-Disco\n  (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"6adbddd5a2f79f5075546ae68101fdc95cfee4b1":{"kind":"REWORK","_number":11,"created":"2020-10-23 14:32:50.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/11","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/11","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/11 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/11 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/11 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/11 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/11","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/11 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"5829646343d78a6779794f67cde2f7c779969afc","subject":"flash/stm32l4: add support of STM32G4 category 4 devices (G491/G4A1)"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-10-23 13:50:18.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco, STM32H735G-Disco, STM32L562E-Disco\n  (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"c02867197d088fac376476393ca7a5dbd37950fc":{"kind":"REWORK","_number":8,"created":"2020-02-17 18:59:23.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/8 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"ee56c502607760deb1b44b4ab06b1cb3a59029fe","subject":"stlink: add trace support in DAP direct mode"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-02-17 15:13:40.000000000","tz":60},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-Disco (512MBit octo-flash, 4-byte addresses)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addresses)\n- suitable cfg for Discovery boards included\n- cfg for STM32H7B3I-Disco, STM32L562E-Disco (untested due to lack of hardware)\n- limited parsing of SFDP data if flash device not hardcoded\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for sending arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"a5fc3162fbca52c5a6c092f2c85905d1c33da272":{"kind":"REWORK","_number":9,"created":"2020-05-24 14:01:31.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/9","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/9","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/9 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/9 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/9 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/9 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/9","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/9 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e41c0f4906e46d1076ce62a0da5518aa1ca280b8","subject":"flash: nor: jtagspi: make read_status report errors"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-05-24 13:51:58.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in\n  dual 4-line mode or STM32H73BI-Disco in octal mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addr),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)\n  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)\n  STM32H73BI-Disco (512MBit octo-flash, DTR, 4-byte addr)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n  (tested only in single/quad mode as most devices either don\u0027t\n  support SFDP at all or have empty(!) SFDP memory)\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q\n  with two W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI and Nucleo-L552ZE-P\n  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,\n  STM32H747I-Disco, STM32H750B-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last\n  bytes causes debug interface to hang)\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n- STM32L562E-Disco untested (unavailable due to export restrictions)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"4909b1f80721ff8630bbdbdcd2f63c9eaecee796":{"kind":"REWORK","_number":6,"created":"2019-06-25 16:29:28.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/6 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6ea43726a801baa718fd08dcdb8ae5835b8a2385","subject":"cortex_m: set C_DEBUGEN in soft_reset_halt"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-06-25 16:25:46.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE and two W25Q256FV in\n  dual 4-line mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- limited parsing of SFDP data if flash device not hardcoded\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for sending arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI with two\n  W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI with two W25Q128FV,\n  sample cfg files included\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last byte not readable, accessing last byte\n  causes debug interface to hang\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"768638b8c79e0e8fe800a1ab745ba8484a40a6b7":{"kind":"REWORK","_number":7,"created":"2019-07-23 20:47:16.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/7 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"263deb3802a515ba8155b6c59146f0f539de4e43","subject":"configure.ac: Fix ST-Link adapter description"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-07-23 12:06:18.000000000","tz":120},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (due to\n  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI\n  with external STLink-V3 or Nucleo-G474RE and two W25Q256FV in\n  dual 4-line mode\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and\n  STM32L476G-Disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-Disco (512MBit octo-flash, 4-byte addresses)\n  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addresses)\n- suitable cfg for Discovery boards included\n- limited parsing of SFDP data if flash device not hardcoded\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for sending arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI with two\n  W25Q256FV, and on Nucleo-L496ZP-P, Nucleo-L4R5ZI with two W25Q128FV,\n  sample cfg files included and on STM32H745I-Disco, STM32H747I-Disco\n- read/verify/erase_check uses indirect read mode to work around silicon bug in\n  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last bytes\n  causes debug interface to hang\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"fc2fe67e631d29dc59794717d8faf887623437f3":{"kind":"REWORK","_number":4,"created":"2018-02-03 13:44:14.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/4 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"c2b2a7a3b84913465420ae7fa0394304943cf035","subject":"Kinetis_ke: add KEAx family to texi and cfg comment"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-02-03 13:38:04.000000000","tz":60},"subject":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (probably due to\n  SWD clock and USB connection)\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- \u0027setparms\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027spicmd\u0027 command for reconfiguration, testing etc.\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on nucleo-f767zi, nucleo-h743zi with two\n  w25q256fv, and on nucleo-l496zg-p, nucleo-l4r5zi with two w25q128fv,\n  sample cfg files included\n- read/verify works only partially on h743 (last word unreadable in\n  memory mapped mode, silicon bug???, workaround: increase FSIZE),\n  but works in indirect read mode\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyperflash mode)\n- perl script \u0027stm32_gpio_conf.pl\u0027 for GPIO setup\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"a20cc9de2c63d7211a49cbe1231a06808ab89415":{"kind":"REWORK","_number":5,"created":"2018-11-02 10:38:36.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/5 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"2ed21488cd52eb8eac10b7984096bdf0652cbae7","subject":"tcl: target: omit apcsw for hla"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-11-02 09:25:24.000000000","tz":60},"subject":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (probably due to\n  SWD clock and USB connection)\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- \u0027set\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027cmd\u0027 command for sending arbitrary SPI commands (reconfiguration, testing etc.)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on nucleo-f767zi, nucleo-h743zi with two\n  w25q256fv, and on nucleo-l496zg-p, nucleo-l4r5zi with two w25q128fv,\n  sample cfg files included\n- read/verify works only partially on h743 (last word unreadable in\n  memory mapped mode, silicon bug or prefetch issue, workaround: increase FSIZE),\n  but works in indirect read mode\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyper flash mode)\n- perl script \u0027stm32_gpio_conf.pl\u0027 for GPIO setup\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"e8c8f8812293d3f759f9f7257f04e2f292c3c6fd":{"kind":"REWORK","_number":2,"created":"2018-01-02 15:40:19.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/2 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1c2e3d41de30c5e47d3fc8eda3de0a0a8229895a","subject":"config for ESPRESSObin from Globalscale Tech. Inc."}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 15:38:35.000000000","tz":60},"subject":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (probably due to\n  SWD clock and USB connection)\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- \u0027setparms\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027spicmd\u0027 command for reconfiguration, testing etc.\n- erase check (standard check takes ages ...)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on nucleo-f767zi, nucleo-h743zi with two\n  w25q256fv, and on nucleo-l496zg-p, nucleo-l4r5zi with two w25q128fv,\n  cfg files included\n- read/verify works only partially on h743 (last word unreadable in\n  memory mapped mode, silicon bug???, workaround: increase FSIZE),\n  but works in indirect read mode\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyperflash mode)\n- perl script for GPIO setup\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"2a9a9d5cf9f99fd6981cd2ba34e411304260291a":{"kind":"REWORK","_number":3,"created":"2018-01-02 16:01:39.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/3 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1c2e3d41de30c5e47d3fc8eda3de0a0a8229895a","subject":"config for ESPRESSObin from Globalscale Tech. Inc."}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 16:01:20.000000000","tz":60},"subject":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (probably due to\n  SWD clock and USB connection)\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- \u0027setparms\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027spicmd\u0027 command for reconfiguration, testing etc.\n- erase check (standard check takes ages ...)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on nucleo-f767zi, nucleo-h743zi with two\n  w25q256fv, and on nucleo-l496zg-p, nucleo-l4r5zi with two w25q128fv,\n  cfg files included\n- read/verify works only partially on h743 (last word unreadable in\n  memory mapped mode, silicon bug???, workaround: increase FSIZE),\n  but works in indirect read mode\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyperflash mode)\n- perl script for GPIO setup\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"8e83bc46f42ef36200ff5c6dee49c3fbdc1f3208":{"kind":"REWORK","_number":1,"created":"2018-01-02 15:12:03.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/21/4321/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/21/4321/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/1 \u0026\u0026 git checkout -b change-4321 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/21/4321/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/21/4321/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1c2e3d41de30c5e47d3fc8eda3de0a0a8229895a","subject":"config for ESPRESSObin from Globalscale Tech. Inc."}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2016-12-21 09:35:58.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 15:10:57.000000000","tz":60},"subject":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface","message":"Flash and EEPROM driver for STM32 QUAD-/OCTOSPI interface\n\n- write speed up to 150 kByte/s on STM32F469I-disco (probably due to\n  SWD clock and USB connection)\n- tested with STM32L476G-disco (64MBit flash, 3-byte addresses),\n  STM32F412G-disco, STM32F469I-disco, STM32F746G-disco, and\n  STM32L476G-disco (all 128Mbit flash, 3-byte addresses),\n  STM32F723E-disco, STM32F769I-disco (512Mbit flash, 4-byte addresses)\n  STM32L4R9I-disco (512MBit octo-flash, 4-byte addresses)\n- suitable cfg for STM32L476G-disco, STM32F412G-disco, STM32F469I-disco,\n  STM32F723E-disco, STM32F746G-disco, STM32F769I-disco, and\n  STM32L476G-disco, STM32L4R9I-disco included\n- \u0027setparms\u0027 command for auto detection override (e. g. for EEPROMS)\n- \u0027spicmd\u0027 command for reconfiguration, testing etc.\n- erase check (standard check takes ages ...)\n- makefile for creation of binary loader files\n- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg\n- tcl/board/stm32f7discovery.cfg removed as name is ambiguous\n  (superseded by stm32f746g-disco vs. stm32f769i-disco)\n- dual 4-line mode tested on nucleo-f767zi, nucleo-h743zi with two\n  w25q256fv, and on nucleo-l496zg-p, nucleo-l4r5zi with two w25q128fv,\n  cfg files included\n- read/verify works only partially on h743 (last word unreadable in\n  memory mapped mode, silicon bug???, workaround: increase FSIZE),\n  but works in indirect read mode\n- octospi supported only in single/dual 1-line, 2-line, 4-line\n  and single 8-line modes, (not in hyperflash mode)\n- perl script for GPIO setup\n\nRequirements:\nGPIOs must be initialized appropriately, and SPI flash chip be configured\nappropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip\nspecific, cf. included cfg files. The driver infers most parameters from\ncurrent setting in CR, CCR, ... registers.\n\nNote that \u0027flash write_image\u0027 with automatic erase is NOT feasible if huge\nportion of spi flash is to be rewritten: Sector erase is incredible slow.\n\nChange-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}