)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002154,"name":"Bill Hass","username":"bhass1"},"change_message_id":"ce5a75b1f6372e3026c2c043bd50efdf4890a0ea","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"8c2ca309_376256cb","updated":"2023-06-17 18:33:58.000000000","message":"FYI there is a binary with powerpc support from ST Micro distributed with SPC5-STUDIO. Could be worthwhile to pursue this source code from ST directly (is anyone already working for ST here?).\n\nI emailed their legal dept. and posted to the ST community page asking for the source: https://stcommunity.st.com/t5/automotive-microcontrollers/spc5-studio-openocd-source-code-gplv2/m-p/568206/highlight/true#M5833","commit_id":"254580df4382729cb138e41ba4b59c741e14c198"}],"src/target/xpc56.c":[{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"969a9a2bccf2345b79924d623c0ca03bf63c079f","unresolved":false,"context_lines":[{"line_number":48,"context_line":"*/"},{"line_number":49,"context_line":"#define xPC56_IR_TAP_FIRST\t0x10"},{"line_number":50,"context_line":"#define xPC56_IR_TAP_NPC\t0x10"},{"line_number":51,"context_line":"#define xPC56_IR_TAP_ONCE\t0x11"},{"line_number":52,"context_line":"#define xPC56_IR_TAP_TCU\t0x1B"},{"line_number":53,"context_line":"#define xPC56_IR_BYPASS\t\t0x1F"},{"line_number":54,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aedf27f1_2f0a0925","line":51,"updated":"2021-04-05 06:26:49.000000000","message":"Hm.. looks like i need to understand this shared TAP concept first.","commit_id":"254580df4382729cb138e41ba4b59c741e14c198"},{"author":{"_account_id":1001877,"name":"Luis de Arquer","email":"luis.dearquer@inertim.com","username":"ldearquer"},"change_message_id":"6c51f9a98ef10bd1003a8139e809aefa0a40e7fc","unresolved":true,"context_lines":[{"line_number":457,"context_line":"{"},{"line_number":458,"context_line":"\t/* Scan chain is { WBBR_low, WBBR_high, MSR, PC, IR, CTL }"},{"line_number":459,"context_line":"\tOther debuggers using PC 0xFFFFc000 (BAM ROM code) */"},{"line_number":460,"context_line":"\tuint32_t scan[6] \u003d { wbbrl ? *wbbrl : 0, 0, 0, 0, inst, BIT(1) | (ffra ? BIT(10) : 0)};"},{"line_number":461,"context_line":""},{"line_number":462,"context_line":"\txpc56_cpuscr(target, true, scan);"},{"line_number":463,"context_line":"\t/* E200_IR_CPUSCR not working */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"83e9d659_86a9cc6a","line":460,"updated":"2023-06-19 08:45:27.000000000","message":"Setting PC to zero may cause failure if the FLASH ECC is wrong (e.g. due to writing without erasing first), and cause an exception.\nThat happened to me quite a lot while developing the flash driver. I used to set the cpuscr PC to point to RAM, and then erase the flash to correct the ECC.\nBut RAM has its own ECC I think, so I don\u0027t know of a generic solution, which works even before initializing RAM on a cold start. Maybe BAM is the right one after all... :)","commit_id":"254580df4382729cb138e41ba4b59c741e14c198"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"969a9a2bccf2345b79924d623c0ca03bf63c079f","unresolved":false,"context_lines":[{"line_number":841,"context_line":"\tnexus_check \u003d 0;"},{"line_number":842,"context_line":"\txpc56_nexus_rw(target, NEXUS_RWA , (uint8_t *) \u0026nexus_check, 0);"},{"line_number":843,"context_line":"\tif (nexus_check \u003d\u003d 0x12345678)"},{"line_number":844,"context_line":"\t\tinfo-\u003enexus2 \u003d true;"},{"line_number":845,"context_line":"#endif"},{"line_number":846,"context_line":"\t/* backup cpuscr content"},{"line_number":847,"context_line":"\txpc56_state_save(target);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aedf27f1_0f05c513","line":844,"updated":"2021-04-05 06:26:49.000000000","message":"Ok, so I see that nexus support is currently not used. In any case the nexus specific code should go to a separate file. Since this interface can be accessed over TAP in a vendor defined way or over AUX port, the main nexus code should not use TAP access directly. There should be a nexus access function. Something like:\nnexus_read_reg(...)\n{\n   nexus_tap_read_reg()\n}\n\nTo make it easier to extend the code with other types of access if needed.\n\nDo not forget, nexus seems to have own state machine\n\nThe price question is, can we detect what is supported by the nexus interface just by reading some register nuxes register? Looks like not. There is a lot of vendor defined things","commit_id":"254580df4382729cb138e41ba4b59c741e14c198"}]}