)]}'
{"id":"openocd~master~Id685f94054aeddd67836146b0ad8b09947f0fae3","project":"openocd","branch":"master","attention_set":{"1001036":{"account":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"last_update":"2022-10-02 13:15:14.000000000","reason":"A robot voted negatively on a label"}},"removed_from_attention_set":{},"hashtags":[],"change_id":"Id685f94054aeddd67836146b0ad8b09947f0fae3","subject":"Bitbanging driver for SPI flash, SPI/MW/UNIO/I2C EEPROMs for Cortex-M","status":"NEW","created":"2018-11-09 15:57:03.000000000","updated":"2022-11-17 17:50:16.000000000","submit_type":"CHERRY_PICK","mergeable":false,"submittable":false,"total_comment_count":21,"unresolved_comment_count":0,"has_review_started":true,"meta_rev_id":"ede77ecb3069269a15285b63399c492cb9828ee5","_number":4760,"owner":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"actions":{},"labels":{"Verified":{"approved":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"value":1,"date":"2022-11-17 17:50:16.000000000","permitted_voting_range":{"min":-1,"max":1},"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"}],"values":{"-1":"Fails"," 0":"No score","+1":"Verified"},"description":"","default_value":0},"Code-Review":{"all":[{"value":0,"permitted_voting_range":{"min":-2,"max":2},"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"value":0,"permitted_voting_range":{"min":-1,"max":1},"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"value":0,"permitted_voting_range":{"min":-1,"max":1},"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"}],"values":{"-2":"This shall not be merged","-1":"I would prefer this is not merged as is"," 0":"No score","+1":"Looks good to me, but someone else must approve","+2":"Looks good to me, approved"},"description":"","default_value":0}},"removable_reviewers":[],"reviewers":{"CC":[{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"}],"REVIEWER":[{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"}]},"pending_reviewers":{},"reviewer_updates":[{"updated":"2019-04-09 22:47:01.000000000","updated_by":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"reviewer":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"state":"REVIEWER"},{"updated":"2020-02-11 23:18:58.000000000","updated_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"reviewer":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"state":"REVIEWER"},{"updated":"2022-10-02 17:41:40.000000000","updated_by":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"reviewer":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"state":"CC"}],"messages":[{"id":"f41362c0bbf9af25e1c2685308a659385b0c80f0","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-11-09 15:57:03.000000000","message":"Uploaded patch set 1.","accounts_in_message":[],"_revision_number":1},{"id":"2dbda576108151a2d6be157b70b5192dcf748d49","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-11-09 16:16:11.000000000","message":"Patch Set 1: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/10797/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10149/ : SUCCESS","accounts_in_message":[],"_revision_number":1},{"id":"c42cef3a7910a251a4071a666cd65ac193d66bc0","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-10 23:33:33.000000000","message":"Patch Set 1:\n\nAndreas, can you please split the driver from the spi chips table update. I\u0027d like to merge the new spi table ASAP.\nPlease also take a look to http://openocd.zylin.com/4749, W25Q128JV is not in your change. Thanks.","accounts_in_message":[],"_revision_number":1},{"id":"0e6824573410ebc12132428f56b08f0193bb5a1d","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-10 23:44:20.000000000","message":"Patch Set 1:\n\nBTW: msoft strongly evokes Microsoft. If you mean \u0027m\u0027 as a Cortex-M, why not use cm (or cmsspi...)","accounts_in_message":[],"_revision_number":1},{"id":"376abc297162473d25be2a9f4e4c01549cd44239","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-11-11 08:31:21.000000000","message":"Patch Set 1:\n\nRegarding \u0027msoft\u0027: This company had gone out ouf my mind more than a decade ago ;-) Your suggestion \u0027cmspi\u0027 looks quite nice (and even means less typing ...).\n\nRegading the SPI table: It\u0027s not easily possible to separate it as  this driver needs an additional entry (qread). Maybe the simplest way would be if you merge the other outstanding additions first, then I\u0027ll add new devices to this driver\u0027s table afterwards? The devices I\u0027ve added here are probably not that important right now. This driver can\u0027t/shouldn\u0027t be merged soon anyway, as some more feedback is a good idea.","accounts_in_message":[],"_revision_number":1},{"id":"9e21dd0ffd63227b7389a786f242512b38a5657b","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-11 10:42:17.000000000","message":"Patch Set 1:\n\nI think the we can merge spi.[ch] changes even if (q)read_cmd and pprog_cmd fields are currently not used by any driver. And we should do it fast, as time to time people send updates, e.g. http://openocd.zylin.com/4749\n\nI\u0027m not sure about FRAM definitions. Do you know what happens if a FRAM is detected by some of the current spi drivers?","accounts_in_message":[],"_revision_number":1},{"id":"7f2ba77cb05d88bd44e6773e9ada8e16fcef76a5","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-21 13:12:52.000000000","message":"Patch Set 1:\n\n(7 comments)\n\nI tested with FRDM-K28F and on-board MT25QU256ABA\nThe flash was detected correctly as \u0027micron n25q256 1.8v\u0027 id \u003d 0x19bb20, size \u003d 32768kbytes.\nerase_sector did not work due to the missing addr bytes in cmd.\nerase_check works well in qpi mode. In spi mode shows\n\nsuccessfully checked erase state\n        #307: 0x01330000 (0x10000 64kB) not erased\n        #308: 0x01340000 (0x10000 64kB) not erased\nand all sectors from 307 to the end of the device as not erased.\nHave not tried to find why.\n\nI also wonder if there is a way to connect a flash which is in qpi mode on OpenOCD startup. I succeeded only after \u0027msoftspi set\u0027 with all parameters.","accounts_in_message":[],"_revision_number":1},{"id":"176273302dbc5798a142ab1e59907df391807438","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-21 15:40:20.000000000","message":"Patch Set 1:\n\n(1 comment)","accounts_in_message":[],"_revision_number":1},{"id":"3582a23dbebfc04e73f076b0a17c5f15b70392c8","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-11-21 17:16:12.000000000","message":"Patch Set 1:\n\n(1 comment)","accounts_in_message":[],"_revision_number":1},{"id":"271060aee33cac0692f428811ccd98911bd76601","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-11-24 15:54:09.000000000","message":"Patch Set 1:\n\n(4 comments)\n\nRe. erase_check: I\u0027ll see into that.\n\nTo start in a specific mode (e. g. QPI) doesn\u0027t help that much. In general, the initial operating mode of the flash chip is completely unknown (could have been set by non-volatile register, or by already programmed/started firmware). To catch all possibilities it\u0027s necessary to try all modes in turn, then configure flash to a (then known) mode, see the example for STM32F769I-disco.","accounts_in_message":[],"_revision_number":1},{"id":"b31a6a924a28653d7847b7b8c776cf21ad33b431","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-12-03 16:16:57.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"64ee5e113982eed4adba66eeb0568615e523ebc1","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-12-03 16:19:27.000000000","message":"Patch Set 2:\n\nRebased, comments processed. Re. K28F: Will check this issue as soon I\u0027ll get a k28f.","accounts_in_message":[],"_revision_number":2},{"id":"911ce22bd8ee806301035b8f23cc43873f07ea57","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2018-12-03 16:37:52.000000000","message":"Patch Set 2: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/10863/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10213/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"9b7d2aabdffc995a1d9a4852c0f199135f90d054","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-12-05 14:11:25.000000000","message":"Patch Set 2:\n\n(3 comments)\n\nI re-tested with FRDM-K28F.\nThe problem with erase_check is dependent on WORKAREASIZE.\nerase_check works with the work area extended to 16k.\nTry WORKAREASIZE 512 and the algo will run for each 8 sector.\n\nOMG I caught it! In setup_regs_spi you save the input port address back to port_pin_io1. In the next run the offset is added again...\n\nA mystery: (WTF qpi mode slower than spi??)\n\n\u003e flash erase_check 1\ncmspi blank checked in 62.101254s (527.654 KiB/s)\nsuccessfully checked erase state\n        Bank is erased\n\u003e cmspi cmd 1 0 0x35; cmspi qpi 1 10; cmspi cmd 1 3 0xAF\nspi: 35 -\u003e\nqpi: af -\u003e 20 bb 19\n\u003e flash erase_check 1\ncmspi blank checked in 63.714535s (514.294 KiB/s)\nsuccessfully checked erase state\n        Bank is erased","accounts_in_message":[],"_revision_number":2},{"id":"06fc1e75d91ae68bdd95b1f91bfd72e18f53900c","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-12-05 15:23:59.000000000","message":"Patch Set 2:\n\nThanks a lot for pinpointing the error. \n\nYes, QPI is (but only slightly) slower than SPI. That\u0027s the price for flexibility: The data pins *might* be on different ports, non-adjacent port pins or in wrong order. If they would be on adjacent port pins on the same port ...\nThe point for supporting DPI/QPI at all is not speed, but the fact that the flash chip might be in QPI mode by default. So at least partial  QPI support is necessary. Hence the complicated stuff for configuring all four data pins is needed, too. Whereas the assembly parts are rather simple.","accounts_in_message":[],"_revision_number":2},{"id":"ac6a33b3b91f904a3b29737ad1b8d2073c019461","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-12-05 19:00:27.000000000","message":"Patch Set 2:\n\n(2 comments)\n\nAndreas, your cmspi is a really useful and flexible tool.\nIn the meantime I tested it with SAMD21 Xplained kit (serial flash AT25DF81A on board) - no problems, just the flash id 0x01451f is not in spi.c, cmspi set solved it. I also tested an i2c eeprom and also (ab)used the driver to test i2c sensors (cmspi set a dummy i2c memory with desired i2c addr and then cmspi cmd can access any i2c chip).\n\nUnfortunately it seems you optimized data too much. Signed byte offsets - ok, until we found a MCU where is the range too short. cmspi_info-\u003edir_off is in fact a 4 signed byte array but it is accessed by bitshifts. All this complicates both asm and c code.\n\nWhat if we use the simpler structure: just 32-bit words, addresses and bitmasks. No offsets, no bytes. Same struct for both host and target (just endianess converted)\nFor each pin: io_bitmask output_addr input_addr\nfor setting direction to out: addr setbits clearbit\nand same for setting dir in.\n\nFor 6 pins we need 6x9 words \u003d 216 bytes, it is comparable to the asm code size. Using two address for setting direction in and out enables working with SAM4 and similar series. Two distinct operation for dir in/out eliminate the need to save the initial status cmspi_info-\u003eio_def (and also no need to set dir register beforehand)\n\nWe should also reduce the number of positional parameters.\nWhat about removing pin config from \u0027flash bank spi.flash cmspi...\u0027 and introducing a cmd for each pin:\ncmspi pin io0 bitmask outaddr inaddr -dirout addr setbits clearbits -dirin addr setbits clearbits\ncmspi pin ncs bitmask outaddr\n\nWhat do you think?","accounts_in_message":[],"_revision_number":2},{"id":"9ff2258c68b381627a5541302d216a5660302137","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-12-09 10:55:43.000000000","message":"Patch Set 2:\n\nI\u0027ve (ab)used the I2C part for a sensor, too. But it\u0027s intended for memories only, so no clock stretching, no 10-bit addresses, and no timeout mechanism.\n\nRegarding the offset range I wouldn\u0027t expect any problem, but it\u0027s possible to extend to 10-bit offset as the two lowest bits can be implied as 0. Certainly the offset handling complicates the host part significantly, but for the assembly part I\u0027m not sure. Keeping all four in a single register is quite convenient. And the total size of assembly code and data block should be as small as possible. For devices with 4k or even 2k of RAM the remaining buffer size impacts the transfer speed significantly.\n\nTo support the SAM family with this awkward read-only or write-only registers via two addresses (or offsets) and two bit masks it will be necessary to add some hack (e. g. if set/reset address coincide) to still use the read-modify-write approach with one (or two exor) masks for the more \u0027conventional\u0027 types (if more than one bit per pin is used to control direction). The set/reset approach will still work only if a single bit flip is sufficient. So ok for the SAM family, but others ... (hopefully nobody else does such weird things like the Atmel guys).\n\nYes, the number of parameters for \u0027flash bank\u0027 isn\u0027t nice. But what I most dislike is that setup it already split into three parts: \u0027flash bank\u0027, port init and (sometimes) flash setup. Does scattering this into even more parts really make it more simple? The only advantage I see is that mode selection (I2C, 4-pin or 6-pin SPI) must be done explicitly and not implicitly by the number or parameters. However, that\u0027s more or less done automatically by the helper scripts.","accounts_in_message":[],"_revision_number":2},{"id":"3a1b47c2a37bde36d00985edea4bbfa0c01f7e35","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2018-12-10 11:26:19.000000000","message":"Patch Set 2:\n\n\u003e ... And the total\n \u003e size of assembly code and data block should be as small as\n \u003e possible. For devices with 4k or even 2k of RAM the remaining\n \u003e buffer size impacts the transfer speed significantly.\n\nWell, I would not expect a 2k RAM device equipped by many-of-MBytes flash.\nI think speed is a priority (with a big flash and reasonable sized RAM buffer) and the second criterion is ability to work in a small RAM no matter how slow speed is.\n\nI submitted http://openocd.zylin.com/4797 for easy testing with different work area sizes. On a slow SAMD21 (cpuclk 48MHz) the speed of \u0027flash read_bank\u0027 with 1k workarea is 67% of the speed with 16k. A faster SAME54 (cpuclk 120MHz) with USB-HS cmsis-dap reads 140 KiB/s with 32k work area and still has 96 KiB/s with 2k (and drops to 58 KiB/s with only 1k).\n\nSo IMHO 100-200 bytes longer target code does not matter.\n\n \u003e To support the SAM family with this awkward read-only or write-only\n \u003e registers via two addresses (or offsets) and two bit masks it will\n \u003e be necessary to add some hack (e. g. if set/reset address coincide)\n \u003e to still use the read-modify-write approach with one (or two exor)\n \u003e masks for the more \u0027conventional\u0027 types (if more than one bit per\n \u003e pin is used to control direction). The set/reset approach will\n \u003e still work only if a single bit flip is sufficient.\n\nA little misunderstanding?\nLet\u0027s use for set-direction-to-output:\n *ADDR1 \u003d (*ADDR1 \u0026 ~CLR1) | SET1\nand for set-direction-to-input:\n *ADDR2 \u003d (*ADDR2 \u0026 ~CLR2) | SET2\nthen we can e.g clear bit 3 and set bit 4 for dir-output\n CLR1 \u003d 1\u003c\u003c3, SET1 \u003d 1\u003c\u003c4\nand use ADDR2 same as ADDR1, CLR2 \u003d 1\u003c\u003c4, SET2 \u003d 1\u003c\u003c3 to switch back to input. No need to XOR for any bit combination in one word and no problem if set-direction-to-output is executed twice as we\u0027re not toggling.\n\nAnd the asm part is as simple as this\n ldmia r4!, {r5, r6, r7}\n ldr   r3, [r5]\n bics  r3, r7\n orrs  r3, r6\n str   r3, [r5]\n\nIn fact the write-only registers of SAM4 PIO are read-as-zero, so read-modify-write is feasible. Eventually (if a device hard-faults on reg read) we can test clearbits for all ones (bitmask instead of clearbits would be easier to test for zero) and avoid useless read:\n *ADDR1 \u003d (~CLR1 ? (*ADDR1 \u0026 ~CLR1) : 0) | SET1","accounts_in_message":[],"_revision_number":2},{"id":"46bb62c1e1f437e3de0649fb95fc8ee810b5034a","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2018-12-15 12:23:12.000000000","message":"Patch Set 2:\n\nIndeed, the read-modify write would work the way you suggested, but that requires even *4* bitmasks. I had in mind using either 1 bitmask in case of the set/reset registers and 1 for the read-modify-write case. Two addresses or two offsets are inevitable anyway.\n\nRe. the write-only registers: Even if a read returns 0 without error on some/all SAMs, this is still undocumented(???) behaviour and should not be relied upon.","accounts_in_message":[],"_revision_number":2},{"id":"dd9b86c74c75ec25712a4d9a1f335a2e19b00cb1","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-02-11 17:31:04.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"054082c1ab45260a915481ddc59013d41fc8b62a","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-02-11 17:48:34.000000000","message":"Patch Set 3: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/10479/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/11137/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"b0139eb7b96de35ce1a92f91085399a97c3160da","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-02-11 18:28:34.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"1f5c750971dcd5528213a7f299f2d5a5478870f5","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-02-11 18:49:15.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11138/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10480/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"6bcdf055e3f66f46cd270d06feb6c295586b42e2","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2019-04-06 21:48:00.000000000","message":"Patch Set 4:\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"3300fda86675e31d0297d6e073469f6036f51f04","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2019-04-09 16:30:15.000000000","message":"Patch Set 4:\n\nAndreas, I tested how sfdp works. I removed micron n25q256 3v item from spi.c and probed N25Q256A13E40 chip. Unfortunately the result was not too encouraging:\nflash \u0027sfdp\u0027, device id \u003d 0x19ba20, flash size \u003d 32768kBytes\n(page size \u003d 64, read \u003d 0x03, qread \u003d 0xff, pprog \u003d 0x02, mass_erase \u003d 0xc7, sector_size \u003d 2097152kBytes, sector_erase \u003d 0xff)\n\nMissing sector erase is clearly a problem of sfdp data in the chip.\nWe should detect -1 cmd and set it as 0, not 0xff.\n\nFYI the sfdp data captured in gdb:\n\n(gdb) p/x header\n{signature \u003d 0x50444653, revision \u003d 0xff000100}\n\n(gdb) p/x *table\n$4 \u003d {fast_addr \u003d 0xfffb20e5, density \u003d 0xffffffff, fast_1x4 \u003d 0xffffffff,\n  fast_1x2 \u003d 0xffffffff, fast_444 \u003d 0xffffffff, read_222 \u003d 0xffffffff,\n  read_444 \u003d 0xffffffff, erase_t12 \u003d 0xffffffff, erase_t34 \u003d 0xffffffff,\n  erase_time \u003d 0x13dd9, chip_byte \u003d 0x0, susp_time \u003d 0x0, susp_instr \u003d 0x0,\n  pwrd_instr \u003d 0x0, quad_req \u003d 0x0, addr_reset \u003d 0x0, read_1x8 \u003d 0x0,\n  dtr_drive \u003d 0x0, octal_req \u003d 0x0, speed_888 \u003d 0x0}","accounts_in_message":[],"_revision_number":4},{"id":"836e61e37877fc16c441e09f2af149d453bcdda1","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-04-09 18:16:39.000000000","message":"Patch Set 4:\n\n(1 comment)\n\nHm, maybe a bug in SFDP read code. The datasheet says 0C/0C/10/D8/00/00/00/00 for erase_t12/erase_t34. No idea where the two 0xffffffff come from. Density 0xffffffff is wrong, too, has to be 0x0fffffff. And the following data does\u0027t fit either.\nOr the SFDP data in the flash is invalid. I already came across W25Q256 which should have SFDP data according to data sheet and date code, but contained all 0xFF instead ...\nMaybe you could post a raw dump of the SFDP data block? Via\n\ncmspi cmd \u003cbank\u003e 0x60 0x5A 0x00 0x00 0x00","accounts_in_message":[],"_revision_number":4},{"id":"b2d69ef7d4c7c19abb9ad881284b961909136964","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2019-04-09 22:47:01.000000000","message":"Patch Set 4:\n\n\u003e cmspi cmd 1 0x60 0x5A 0x00 0x00 0x00\nspi: 5a 00 00 00 -\u003e ff 53 46 44 50 00 01 00 ff 07 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff\n\n\u003e cmspi cmd 1 16 0x5A 0x00 0x00 0x02 0x00\nspi: 5a 00 00 02 00 -\u003e 44 50 00 01 00 ff 00 00 01 09 ff ff ff ff ff ff\n\nThere is a problem: slow bitbang in cmd or in sfdp read can finish 8-10 bytes, then MISO goes Hi-Z:\n\n\u003e flash mdb 0x90000000 32\n0x90000000: 2f 2a 0a 20 2a 20 73 70 69 5f 63 6f 6e 2e 63 0a 20 2a 0a 20 2a 20 20 43 72 65 61 74 65 64 20 6f\n\n\u003e cmspi cmd 1 16 0x03 0 0 0\nspi: 03 00 00 00 -\u003e 2f 2a 0a 20 2a 20 73 70 69 5f ff ff ff ff ff ff\n\u003e cmspi cmd 1 16 0x03 0 0 0\nspi: 03 00 00 00 -\u003e 2f 2a 0a 20 2a 20 73 7f ff ff ff ff ff ff ff ff\n\u003e cmspi cmd 1 16 0x03 0 0 0\nspi: 03 00 00 00 -\u003e 2f 2a 0a 20 2a 20 73 70 69 5f ff ff ff ff ff ff\n\u003e cmspi cmd 1 16 0x03 0 0 0\nspi: 03 00 00 00 -\u003e 2f 2a 0a 20 2a 20 73 77 ff ff ff ff ff ff ff ff\n\u003e cmspi cmd 1 16 0x03 0 0 0\nspi: 03 00 00 00 -\u003e 2f 2a 0a 20 2a 20 73 70 69 5f ff ff ff ff ff ff\n\nI added 0x5A to allowed read commands, issued\n\n\u003e cmspi set 1 n25q256 0x2000000 0x100 0x5a 0 0x2 0xc7 0x10000 0xd8\nflash \u0027micron n25q256 3v\u0027 id \u003d 0x19ba20, size \u003d 32768kbytes\nflash \u0027n25q256\u0027 id \u003d unknown\nflash size \u003d 32768kbytes\n\u003e flash mdb 0x90000000 0x60\n0x90000000: 53 46 44 50 00 01 00 ff 00 00 01 09 30 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff\n0x90000020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e5 20 fb ff ff ff ff 0f 29 eb 27 6b 08 3b 27 bb\n0x90000040: ff ff ff ff ff ff 27 bb ff ff 29 eb 0c 20 10 d8 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff ff\n\nand here we have correct sfdp data.\n\nI checked DQ3/NHOLD pin: I cannot enable weak pullup, as SAME54 controls weak pull up/down by OUT bit. The pin goes high at the begining of cmd processing and then disconnects to Hi-Z - slowly goes low and breaks the operation. After removing DQ2 and DQ3 from cmspi config and setting them to weak pullup, cmd works:\n\n\u003e cmspi cmd 1 0x60 0x5A 0x00 0x00 0x00\nspi: 5a 00 00 00 -\u003e ff 53 46 44 50 00 01 00 ff 00 00 01 09 30 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e5 20 fb ff ff ff ff 0f 29 eb 27 6b 08 3b 27 bb ff ff ff ff ff ff 27 bb ff ff 29 eb 0c 20 10 d8 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff\n\nand detected parameters are almost correct:\n\nflash \u0027sfdp\u0027, device id \u003d 0x19ba20, flash size \u003d 32768kBytes\n(page size \u003d 64, read \u003d 0x03, qread \u003d 0xeb, pprog \u003d 0x02, mass_erase \u003d 0xc7, sector_size \u003d 64kBytes, sector_erase \u003d 0xd8)\n\n- except smaller page size, which is not defined in sfdp.","accounts_in_message":[],"_revision_number":4},{"id":"a0e48e8fe1046c3c7ab8c482e24920b0ff3ddb87","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-04-10 07:26:13.000000000","message":"Patch Set 4:\n\nThanks a lot for this test. So, a solution would be to drive DQ3 high (and DQ2, too, to disable write protection) in SPI/DPI mode instead of relying on a pull-up.","accounts_in_message":[],"_revision_number":4},{"id":"3306922bbf86de493c4d119e8dfe69f632585593","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-04-19 15:01:45.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"f4ceefc2c1ad90cdd058ecb17a59fe07796486b2","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-19 15:22:20.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11600/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10925/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"2c367d77fe545ac5b69841bbd4b7c273c84eb089","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-04-19 15:28:05.000000000","message":"Patch Set 5:\n\nIO3/NHOLD and IO2/NWP are now actively pulled high in SPI/DPI modes.","accounts_in_message":[],"_revision_number":5},{"id":"1ab20fda9db23f7908a74c8583b89c4b84928941","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2019-08-30 16:48:35.000000000","message":"Uploaded patch set 6.","accounts_in_message":[],"_revision_number":6},{"id":"59dac03fdd10a98b9fa816aa34e24ad9e0323794","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-08-30 17:08:59.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/12058/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11367/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"7acd505f6089f92da00e8168bf0a825902f452f0","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2020-02-11 22:22:31.000000000","message":"Uploaded patch set 7.","accounts_in_message":[],"_revision_number":7},{"id":"8615c05a814f4b33fa78701222e8e3c8f36f7643","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2020-02-11 23:18:58.000000000","message":"Patch Set 7: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/12528/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11825/ : SUCCESS","accounts_in_message":[],"_revision_number":7},{"id":"ce73fdb29242fde87aa806e3db2db1cb42e1fb93","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2022-10-02 10:28:34.000000000","message":"Uploaded patch set 8.","accounts_in_message":[],"_revision_number":8},{"id":"c60b4401f4f7755161e26e82ffba3c855b3e938b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2022-10-02 13:15:14.000000000","message":"Patch Set 8: Verified-1\n\nBuild Failed \n\nhttps://build.openocd.org/job/openocd-gerrit-build/16040/ : FAILURE\n\nhttps://build.openocd.org/job/openocd-gerrit/16830/ : FAILURE","accounts_in_message":[],"_revision_number":8},{"id":"8c4c57c14491b786010bcb160d812a22fa147b91","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2022-10-02 16:36:00.000000000","message":"Patch Set 8:\n\nBuild Failed \n\nhttps://build.openocd.org/job/openocd-gerrit/16830/ : FAILURE\n\nhttps://build.openocd.org/job/openocd-gerrit-build/16046/ : FAILURE","accounts_in_message":[],"_revision_number":8},{"id":"b51ba17712a94895f0d05efb8bfefde29876040e","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2022-10-02 17:41:40.000000000","message":"Patch Set 8:\n\n(1 comment)","accounts_in_message":[],"_revision_number":8},{"id":"76ba626210dfacbcd2ade06ca093186b1bab70d0","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"real_author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"date":"2022-11-17 16:32:52.000000000","message":"Uploaded patch set 9.","accounts_in_message":[],"_revision_number":9},{"id":"ede77ecb3069269a15285b63399c492cb9828ee5","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2022-11-17 17:50:16.000000000","message":"Patch Set 9: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit-build/16251/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit/17041/ : SUCCESS","accounts_in_message":[],"_revision_number":9}],"current_revision":"07150397f052cc44c328f8dea10d29599fb28d7a","revisions":{"ecb098bf6e673aebda296cde22eb7d93eeeafb2c":{"kind":"REWORK","_number":1,"created":"2018-11-09 15:57:03.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/1 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"010b09121ca08f955921654c6a3d405be80afef1","subject":"armv7a: ARMv7-A MMU tools"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-11-09 15:55:56.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write (some SAMs don\u0027t have that!!!) direction\nregisters. Several banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-disco, STM32F746G-disco, STM32F769I-disco and\nSTM32F030, STM32F103 boards, additionally with various Flash,\nEEPROMs and FRAMs on STM32F103 and Kinetis K64F.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe verify_image command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read. However, verify_bank does work as expected.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"9a21fac0e2274e9c717a19bb6a3f37fc98160a52":{"kind":"REWORK","_number":2,"created":"2018-12-03 16:16:57.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/2 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"42f1cc576ab9b503fadd0b8916a139cd0bc6563e","subject":"SPI table updates (some new devices and new info)"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-12-03 16:16:23.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write (some SAMs don\u0027t have that!!!) direction\nregisters. Several banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-disco, STM32F746G-disco, STM32F769I-disco and\nSTM32F030, STM32F103 boards, additionally with various Flash,\nEEPROMs and FRAMs on STM32F103 and Kinetis K64F.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe verify_image command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read. However, verify_bank does work as expected.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"9a8d2b4d10349ba89674cb0dc92f48bee4e7b317":{"kind":"REWORK","_number":3,"created":"2019-02-11 17:31:04.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/3 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6c2020eb48803b941a94d600e2a96728d05a7da9","subject":"jlink: Use correct SWD buffer size"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-02-11 17:27:14.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nFRDM-K64F, FRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030,\nSTM32F103 boards, with various Flash, EEPROMs and FRAMs.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe verify_image command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read. However, verify_bank does work as expected.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"fe43d7eaf5b276787dc8f283a149a09fd144b1b4":{"kind":"REWORK","_number":4,"created":"2019-02-11 18:28:34.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/4 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6c2020eb48803b941a94d600e2a96728d05a7da9","subject":"jlink: Use correct SWD buffer size"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-02-11 18:16:27.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nFRDM-K64F, FRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030,\nSTM32F103 boards, with various Flash, EEPROMs and FRAMs.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe verify_image command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read. However, verify_bank does work as expected.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"8d952bd2b54243b2f072d86b40b0df237bcf4fb7":{"kind":"REWORK","_number":5,"created":"2019-04-19 15:01:45.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/5 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"a4ac56152d9fc13c3fa479397407d9b86ffb13d8","subject":"target/cortex_m: Implement maskisr steponly option"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-04-19 14:25:49.000000000","tz":120},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nWith STLink-V3 at 24MHz, read up to 600kByte/s and write up to\n400kByte/s is possible (Nucleo-F767ZI, W25Q256).\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nFRDM-K64F, FRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030,\nSTM32F103 boards, with various Flash, EEPROMs and FRAMs.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe verify_image command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read. However, verify_bank does work as expected.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"08cc6be6b89605f02b082327f41d58ac735800a0":{"kind":"REWORK","_number":6,"created":"2019-08-30 16:48:35.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/6 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"081954136681b26ad30db9b4cc40cb360f47602c","subject":"gdb_server, rtos: Fine-grained RTOS register access"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2019-08-30 16:43:17.000000000","tz":120},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nWith STLink-V3 at 24MHz, read up to 600kByte/s and write up to\n400kByte/s is possible (Nucleo-F767ZI, W25Q256).\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nFRDM-K64F, FRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030,\nSTM32F103 boards, with various Flash, EEPROMs and FRAMs.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe \u0027verify_image\u0027 command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read (However, verify_bank does work as expected).\nInstead, \u0027flash verify_image\u0027 command may be used.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"1b59e3232a961cc826d95dbdd24b7f49f6757daa":{"kind":"REWORK","_number":7,"created":"2020-02-11 22:22:31.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/7 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"853a05287c987d419440b21e2b22f5ab75297739","subject":"jtag: Fix copy-paste error in \u0027irscan\u0027 help"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2020-02-11 22:19:55.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachement:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nWith STLink-V3 at 24MHz, read up to 600kByte/s and write up to\n400kByte/s is possible (Nucleo-F767ZI, W25Q256).\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nFRDM-K64F, FRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030,\nSTM32F103, STM32H7A3ZI, STM32L552ZE boards, with various Flash,\nEEPROMs and FRAMs.\nAdditionally, DPI and QPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor I2C EEPROMs and FRAMs read, write, erase check and some utilities\nare available. Only very few I2C memories support an id readout,\ntherefore this is not implemented and parameters must be specified\nmanually.\nThe \u0027verify_image\u0027 command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read (However, verify_bank does work as expected).\nInstead, \u0027flash verify_image\u0027 command may be used.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"c2d91171c7449fad0e5ca0e6d23124b157df1bba":{"kind":"REWORK","_number":8,"created":"2022-10-02 10:28:34.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/8 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"ae937791d35b0820e0bc9bf0ab134c2bebd113e4","subject":"flash/nor/rp2040: remove new line from error message"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2022-10-02 09:28:51.000000000","tz":120},"subject":"Bitbanging driver for SPI flash, SPI/MW/UNIO/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/MW/UNIO/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachment:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nWith STLink-V3 at 24MHz, read up to 600kByte/s and write up to\n400kByte/s is possible (Nucleo-F767ZI, W25Q256).\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nSTM32L4P5G-Disco, STM32H7B3I-Disco, STM32H735G-Diskco, FRDM-K64F,\nFRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030, STM32F103,\nSTM32H7A3ZI, STM32L552ZE boards, with various Flash, EEPROMs and FRAMs.\n\nAdditionally, DPI, QPI and OPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor SPI, DPI and QPI dual mode is supported with single NCS or\nseparate NCS signals for both devices.\nOctal devices are still rather uncommon, tested with some Adesto,\nCypress, GigaDdevices and Macronix devices.\n\nFor Microwire, UNIO and I2C EEPROMs and FRAMs read, write, erase check\nand some utilities are available. Only some I2C memories support\nan id readout, therefore this is not implemented and parameters must\nbe specified manually for Microwire, UNIO and I2C devices.\n\nThe \u0027verify_image\u0027 command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read (However, verify_bank does work as expected).\nFor inspecting memory contents, use \u0027flash mdw\u0027 and friends.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}},"07150397f052cc44c328f8dea10d29599fb28d7a":{"kind":"REWORK","_number":9,"created":"2022-11-17 16:32:52.000000000","uploader":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"ref":"refs/changes/60/4760/9","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/60/4760/9","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/9 \u0026\u0026 git checkout -b change-4760 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/9 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/9 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/9 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/60/4760/9","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/60/4760/9 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"9d925776b4504f71306b16467c1b731e57b6e7d0","subject":"target/armv7m: fix feature name of ARMv8M security extension regs"}],"author":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2018-01-02 19:03:31.000000000","tz":60},"committer":{"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","date":"2022-11-17 16:27:26.000000000","tz":60},"subject":"Bitbanging driver for SPI flash, SPI/MW/UNIO/I2C EEPROMs for Cortex-M","message":"Bitbanging driver for SPI flash, SPI/MW/UNIO/I2C EEPROMs for Cortex-M\n\nSome Cortex-M controllers include a specialized SPI interface\nfor external serial flash chips (with a dedicated driver) but\nothers do not, so downloading firmware employing an external flash\nor EEPROM require a second procedure for programming or dumping\ntheir contents. This driver overcomes this nuisance by emulating\nan additional flash bank. The SPI flash is connected via 3, 4\nor 6 GPIO pins (NCS, CLK, IO3/NHOLD, IO2/NWP, IO1/MISO, IO0/MOSI)\nonly, no hardware SPI is required, therefore the driver should work\non any little-endian Cortex-M (M0 and up) supporting word addressable\nGPIO ports with read/write or set/clr direction registers.\nSeveral banks of this type may be used simultaneously.\nOn STM32F746 more than 1.5 MByte/s raw read is possible. However,\nthe limiting factor is the debug interface and its USB attachment:\nread/write on STM32F746G-disco via ST-Link V2 up to approx. 150kByte/s.\nWith STLink-V3 at 24MHz, read up to 600kByte/s and write up to\n400kByte/s is possible (Nucleo-F767ZI, W25Q256).\nSetup is somewhat complicated as GPIOs must be initialized by a\ndedicated script (e. g. in reset init hook, examples included).\nTested on STM32F469I-Disco, STM32F746G-Disco, STM32F769I-Disco,\nSTM32L4P5G-Disco, STM32H7B3I-Disco, STM32H735G-Diskco, FRDM-K64F,\nFRDM-K28F, Arduino-Due, SAM-E70-Xpld and STM32F030, STM32F103,\nSTM32H7A3ZI, STM32L552ZE boards, with various Flash, EEPROMs and FRAMs.\n\nAdditionally, DPI, QPI and OPI modes are supported with a configurable\nnumber of dummy cycles. Some flash devices require different\ninstructions in these modes, and enabling/disabling of these modes\nis quite device dependent, this must be considered separately.\nNote that DPI/QPI mode imply that even instructions are sent on 2 or\n4 lines, respectively, that\u0027s not the same as dual/quad read etc.\nOnly some recent high capacity devices do support DPI/QPI modes.\nFor SPI, DPI and QPI dual mode is supported with single NCS or\nseparate NCS signals for both devices.\nOctal devices are still rather uncommon, tested with some Adesto,\nCypress, GigaDdevices and Macronix devices. Command formats supported:\n1-byte, 2-byte with second byte inverted/non-inverted.\n\nFor Microwire, UNIO and I2C EEPROMs and FRAMs read, write, erase check\nand some utilities are available. Only some I2C memories support\nan id readout, therefore this is not implemented and parameters must\nbe specified manually for Microwire, UNIO and I2C devices.\n\nThe \u0027verify_image\u0027 command doesn\u0027t work for any these types of memory\nbank, as it does not use the read function of this driver but plain\nmemory read (However, verify_bank does work as expected).\nFor inspecting memory contents, use \u0027flash mdw\u0027 and friends.\n\nChange-Id: Id685f94054aeddd67836146b0ad8b09947f0fae3\nSigned-off-by: Andreas Bolsch \u003chyphen0break@gmail.com\u003e\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"NOT_READY","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"NEED"}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"UNSATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"]}}]}