)]}'
{"contrib/loaders/flash/stm32/stm32l4x.S":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"ccd4adab860412a462137d3cf153ed2a8de629a7","unresolved":false,"context_lines":[{"line_number":69,"context_line":"\tdsb"},{"line_number":70,"context_line":"busy:"},{"line_number":71,"context_line":"\tldr \tr6, [r4, #FLASH_SR_OFFS]\t/* get status register */"},{"line_number":72,"context_line":"\tlsrs\tr7, r6, #FLASH_BSY+1\t\t/* BSY \u003d\u003d 1 \u003d\u003e operation in progress */"},{"line_number":73,"context_line":"\tbne \tbusy\t\t\t\t\t\t/* wait more ... */"},{"line_number":74,"context_line":"\tmovs\tr7, #FLASH_ERROR_MASK\t\t/* PGSERR | SIZERR | PGPERR | PGAERR | WRPERR | OPERR */"},{"line_number":75,"context_line":"\tuxtb\tr7, r7\t\t\t\t\t\t/* discard upper 24 bits */"},{"line_number":76,"context_line":"\ttst\t\tr6, r7\t\t\t\t\t\t/* check for any error bit */"}],"source_content_type":"text/x-asm","patch_set":1,"id":"ee703fc5_6d16bdae","line":73,"range":{"start_line":72,"start_character":0,"end_line":73,"end_character":35},"updated":"2019-04-26 07:14:54.000000000","message":"This doesn\u0027t look correct. Why shift 17 bits when you\u0027re interested in bit 16? Surely it will get shifted out. Also, the NE condition means that the effective behaviour of the loop condition will be to wait until bits 31:17 of SR are all zero. I\u0027m guessing most of those are reserved and should be masked out as well.\n\nPerhaps you meant to check the carry bit instead, which would explain the +1?","commit_id":"830592b5dae03147316009289f4586e0df2c2b86"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"529958c9d0a96b704fbefbb8bb8778accfaa3278","unresolved":false,"context_lines":[{"line_number":69,"context_line":"\tdsb"},{"line_number":70,"context_line":"busy:"},{"line_number":71,"context_line":"\tldr \tr6, [r4, #FLASH_SR_OFFS]\t/* get status register */"},{"line_number":72,"context_line":"\tlsrs\tr7, r6, #FLASH_BSY+1\t\t/* BSY \u003d\u003d 1 \u003d\u003e operation in progress */"},{"line_number":73,"context_line":"\tbne \tbusy\t\t\t\t\t\t/* wait more ... */"},{"line_number":74,"context_line":"\tmovs\tr7, #FLASH_ERROR_MASK\t\t/* PGSERR | SIZERR | PGPERR | PGAERR | WRPERR | OPERR */"},{"line_number":75,"context_line":"\tuxtb\tr7, r7\t\t\t\t\t\t/* discard upper 24 bits */"},{"line_number":76,"context_line":"\ttst\t\tr6, r7\t\t\t\t\t\t/* check for any error bit */"}],"source_content_type":"text/x-asm","patch_set":1,"id":"ee703fc5_8d96b1f2","line":73,"range":{"start_line":72,"start_character":0,"end_line":73,"end_character":35},"in_reply_to":"ee703fc5_6d16bdae","updated":"2019-04-28 12:50:44.000000000","message":"Your\u0027re quite right. I\u0027m wondering why it still worked flawlessly ...","commit_id":"830592b5dae03147316009289f4586e0df2c2b86"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"564b984a1d144b6a3c99d88bf5feb249cdeadb3f","unresolved":false,"context_lines":[{"line_number":69,"context_line":"\tdsb"},{"line_number":70,"context_line":"busy:"},{"line_number":71,"context_line":"\tldr \tr6, [r4, #FLASH_SR_OFFS]\t/* get status register */"},{"line_number":72,"context_line":"\tlsrs\tr7, r6, #FLASH_BSY+1\t\t/* BSY \u003d\u003d 1 \u003d\u003e operation in progress */"},{"line_number":73,"context_line":"\tbne \tbusy\t\t\t\t\t\t/* wait more ... */"},{"line_number":74,"context_line":"\tmovs\tr7, #FLASH_ERROR_MASK\t\t/* PGSERR | SIZERR | PGPERR | PGAERR | WRPERR | OPERR */"},{"line_number":75,"context_line":"\tuxtb\tr7, r7\t\t\t\t\t\t/* discard upper 24 bits */"},{"line_number":76,"context_line":"\ttst\t\tr6, r7\t\t\t\t\t\t/* check for any error bit */"}],"source_content_type":"text/x-asm","patch_set":1,"id":"ee703fc5_e835dbd8","line":73,"range":{"start_line":72,"start_character":0,"end_line":73,"end_character":35},"in_reply_to":"ee703fc5_8d96b1f2","updated":"2019-04-30 08:24:17.000000000","message":"Probably because the bus stalls on the second write, until the first one completes. Just guessing. This would make polling BSY rather pointless but I\u0027m not sure it\u0027s safe to rely on that behaviour.\n\nAlso, you could\u0027ve tested against the mask loaded into r7 like you do below, which could\u0027ve avoided the \"unrelated\" changes to the register defines.","commit_id":"830592b5dae03147316009289f4586e0df2c2b86"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"564b984a1d144b6a3c99d88bf5feb249cdeadb3f","unresolved":false,"context_lines":[{"line_number":72,"context_line":"\tlsrs\tr7, r6, #FLASH_BSY+1\t\t/* BSY \u003d\u003d 1 \u003d\u003e operation in progress */"},{"line_number":73,"context_line":"\tbne \tbusy\t\t\t\t\t\t/* wait more ... */"},{"line_number":74,"context_line":"\tmovs\tr7, #FLASH_ERROR_MASK\t\t/* PGSERR | SIZERR | PGPERR | PGAERR | WRPERR | OPERR */"},{"line_number":75,"context_line":"\tuxtb\tr7, r7\t\t\t\t\t\t/* discard upper 24 bits */"},{"line_number":76,"context_line":"\ttst\t\tr6, r7\t\t\t\t\t\t/* check for any error bit */"},{"line_number":77,"context_line":"\tbne\t\terror\t\t\t\t\t\t/* fail... */"},{"line_number":78,"context_line":""}],"source_content_type":"text/x-asm","patch_set":1,"id":"ee703fc5_08336ff4","line":75,"range":{"start_line":75,"start_character":1,"end_line":75,"end_character":45},"updated":"2019-04-30 08:24:17.000000000","message":"Meaningless, just make sure FLASH_ERROR_MASK doesn\u0027t contain the unwanted bits, which it doesn\u0027t.","commit_id":"830592b5dae03147316009289f4586e0df2c2b86"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"14ff6ce1bfcb8bbca72dab9960ac5a99ef92e9c2","unresolved":false,"context_lines":[{"line_number":72,"context_line":"\tlsrs\tr7, r6, #FLASH_BSY+1\t\t/* BSY \u003d\u003d 1 \u003d\u003e operation in progress */"},{"line_number":73,"context_line":"\tbne \tbusy\t\t\t\t\t\t/* wait more ... */"},{"line_number":74,"context_line":"\tmovs\tr7, #FLASH_ERROR_MASK\t\t/* PGSERR | SIZERR | PGPERR | PGAERR | WRPERR | OPERR */"},{"line_number":75,"context_line":"\tuxtb\tr7, r7\t\t\t\t\t\t/* discard upper 24 bits */"},{"line_number":76,"context_line":"\ttst\t\tr6, r7\t\t\t\t\t\t/* check for any error bit */"},{"line_number":77,"context_line":"\tbne\t\terror\t\t\t\t\t\t/* fail... */"},{"line_number":78,"context_line":""}],"source_content_type":"text/x-asm","patch_set":1,"id":"8e7fc396_5c9135fa","line":75,"range":{"start_line":75,"start_character":1,"end_line":75,"end_character":45},"in_reply_to":"ee703fc5_08336ff4","updated":"2019-06-29 14:44:08.000000000","message":"Indeed, deleted.","commit_id":"830592b5dae03147316009289f4586e0df2c2b86"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"52b748ece92bf38bd9a8ebfc14653591b35a326e","unresolved":false,"context_lines":[{"line_number":10,"context_line":" *                                                                         *"},{"line_number":11,"context_line":" *   Copyright (C) 2019 Andreas Bolsch                                     *"},{"line_number":12,"context_line":" *   andreas.bolsch@mni.thm.de                                             *"},{"line_number":13,"context_line":" *                                                                         *"},{"line_number":14,"context_line":" *   This program is free software; you can redistribute it and/or modify  *"},{"line_number":15,"context_line":" *   it under the terms of the GNU General Public License as published by  *"},{"line_number":16,"context_line":" *   the Free Software Foundation; either version 2 of the License, or     *"}],"source_content_type":"text/x-asm","patch_set":3,"id":"8e7fc396_2ab2e792","line":13,"updated":"2019-09-01 21:31:31.000000000","message":"Is there anything left of the original file?  It appears to be an almost complete rewrite.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"b7492ad999541ea69a0a886d2156b675897749a1","unresolved":false,"context_lines":[{"line_number":10,"context_line":" *                                                                         *"},{"line_number":11,"context_line":" *   Copyright (C) 2019 Andreas Bolsch                                     *"},{"line_number":12,"context_line":" *   andreas.bolsch@mni.thm.de                                             *"},{"line_number":13,"context_line":" *                                                                         *"},{"line_number":14,"context_line":" *   This program is free software; you can redistribute it and/or modify  *"},{"line_number":15,"context_line":" *   it under the terms of the GNU General Public License as published by  *"},{"line_number":16,"context_line":" *   the Free Software Foundation; either version 2 of the License, or     *"}],"source_content_type":"text/x-asm","patch_set":3,"id":"8e7fc396_c52fa49b","line":13,"in_reply_to":"8e7fc396_2ab2e792","updated":"2019-10-06 17:25:20.000000000","message":"Well, this file shouldn\u0027t be considered isolated from the rest. And e. g. parameter handling isn\u0027t modified. More or less a 1:1 rewrite to reduced instruction set, padding added.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"}],"doc/openocd.texi":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"d3b934204a466df39cdb78e3ea3e84fd085091a5","unresolved":false,"context_lines":[{"line_number":6891,"context_line":"@end deffn"},{"line_number":6892,"context_line":""},{"line_number":6893,"context_line":"@deffn {Flash Driver} stm32l4x"},{"line_number":6894,"context_line":"All members of the STM32L4, STM32L4+, STM32WB, STM32WB and STM32G4"},{"line_number":6895,"context_line":"microcontroller families from STMicroelectronics include internal flash"},{"line_number":6896,"context_line":"and use ARM Cortex-M4 cores."},{"line_number":6897,"context_line":"Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core."}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"2e76d7c5_fc7cbd1d","line":6894,"updated":"2020-01-20 00:07:54.000000000","message":"WL?","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7e130441df9218ff93976f21b249a4b1ca71549d","unresolved":false,"context_lines":[{"line_number":6891,"context_line":"@end deffn"},{"line_number":6892,"context_line":""},{"line_number":6893,"context_line":"@deffn {Flash Driver} stm32l4x"},{"line_number":6894,"context_line":"All members of the STM32L4, STM32L4+, STM32WB, STM32WB and STM32G4"},{"line_number":6895,"context_line":"microcontroller families from STMicroelectronics include internal flash"},{"line_number":6896,"context_line":"and use ARM Cortex-M4 cores."},{"line_number":6897,"context_line":"Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core."}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"2e76d7c5_bcbc05b3","line":6894,"in_reply_to":"2e76d7c5_fc7cbd1d","updated":"2020-01-20 17:27:35.000000000","message":"Oh yes indeed. This list ist getting longer and longer ...","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"f7984d9ecba8566de976efa4e7c4037a9b069d41","unresolved":false,"context_lines":[{"line_number":6893,"context_line":"@end deffn"},{"line_number":6894,"context_line":""},{"line_number":6895,"context_line":"@deffn {Flash Driver} stm32l4x"},{"line_number":6896,"context_line":"All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4"},{"line_number":6897,"context_line":"microcontroller families from STMicroelectronics include internal flash"},{"line_number":6898,"context_line":"and use ARM Cortex-M4 cores."},{"line_number":6899,"context_line":"Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core."}],"source_content_type":"text/x-texinfo","patch_set":9,"id":"2e76d7c5_8896a3f2","line":6896,"range":{"start_line":6896,"start_character":47,"end_line":6896,"end_character":54},"updated":"2020-03-01 21:31:05.000000000","message":"mention of STM32WL (I don\u0027t mind this)","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"}],"src/flash/nor/stm32l4x.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"16b10bdd6233b74d8ed7deab7c97a7011bdabf22","unresolved":false,"context_lines":[{"line_number":679,"context_line":"\t\tbuffer_size \u003d 16384;"},{"line_number":680,"context_line":"\t}"},{"line_number":681,"context_line":""},{"line_number":682,"context_line":"\tif (target_alloc_working_area_try(target, buffer_size, \u0026source) !\u003d ERROR_OK) {"},{"line_number":683,"context_line":"\t\tLOG_ERROR(\"allocating working area failed\");"},{"line_number":684,"context_line":"\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"},{"line_number":685,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2e76d7c5_c776ce39","line":682,"range":{"start_line":682,"start_character":30,"end_line":682,"end_character":34},"updated":"2020-01-29 11:10:39.000000000","message":"A version without _try suffix seems better if not used in the loop.","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"d3b934204a466df39cdb78e3ea3e84fd085091a5","unresolved":false,"context_lines":[{"line_number":882,"context_line":"\t\tflash_size_in_kb \u003d part_info-\u003emax_flash_size_kb;"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":""},{"line_number":885,"context_line":"\t/* if the user sets the size manually then ignore the probed value"},{"line_number":886,"context_line":"\t * this allows us to work around devices that have a invalid flash size register value */"},{"line_number":887,"context_line":"\tif (stm32l4_info-\u003euser_bank_size) {"},{"line_number":888,"context_line":"\t\tLOG_INFO(\"ignoring flash probed value, using configured bank size\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2e76d7c5_dc7f8110","line":885,"in_reply_to":"","updated":"2020-01-20 00:07:54.000000000","message":"IMO this is the wrong place to override the probed value, as this can trigger some errors in discovering the flash layout.\nThis may be good for testing and gap emulation, but in real world this should be after the device ID switch case.\n\nFor example with STM32L4R9xI the flash is 2M and the code should check the bit 22 for dual bank detection. And if the user set 1M as size the code will chech for bit 21 which will give erronoues value of page size","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"63178c28494fb61b93c141f8d970d89bcdca0989","unresolved":false,"context_lines":[{"line_number":882,"context_line":"\t\tflash_size_in_kb \u003d part_info-\u003emax_flash_size_kb;"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":""},{"line_number":885,"context_line":"\t/* if the user sets the size manually then ignore the probed value"},{"line_number":886,"context_line":"\t * this allows us to work around devices that have a invalid flash size register value */"},{"line_number":887,"context_line":"\tif (stm32l4_info-\u003euser_bank_size) {"},{"line_number":888,"context_line":"\t\tLOG_INFO(\"ignoring flash probed value, using configured bank size\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2e76d7c5_bc8ba5c3","line":885,"in_reply_to":"2e76d7c5_5cd9312b","updated":"2020-01-29 10:32:36.000000000","message":"IMO, we don\u0027t give the user the possibility to break the driver the ask him to not break it.\nI believe the size override is a nice cheating feature, but I suggest to move it after dual bank and page size detection.\nOr you can simply propose it into another patch to not block this one.","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"7e130441df9218ff93976f21b249a4b1ca71549d","unresolved":false,"context_lines":[{"line_number":882,"context_line":"\t\tflash_size_in_kb \u003d part_info-\u003emax_flash_size_kb;"},{"line_number":883,"context_line":"\t}"},{"line_number":884,"context_line":""},{"line_number":885,"context_line":"\t/* if the user sets the size manually then ignore the probed value"},{"line_number":886,"context_line":"\t * this allows us to work around devices that have a invalid flash size register value */"},{"line_number":887,"context_line":"\tif (stm32l4_info-\u003euser_bank_size) {"},{"line_number":888,"context_line":"\t\tLOG_INFO(\"ignoring flash probed value, using configured bank size\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2e76d7c5_5cd9312b","line":885,"in_reply_to":"2e76d7c5_dc7f8110","updated":"2020-01-20 17:27:35.000000000","message":"Depends. The intention is to override precisely the value from the flash size register, regardless of anything else.\nYou\u0027re quite right that misuse might cause trouble. On the other hand, in the standard cfg files the size is always set to 0, so to tamper with this \"feature\" needs some extra effort so that accidental use is rather unlikely.\n\nBut maybe emitting an explicit warning in this case (and remark in the doc) is sufficient?","commit_id":"3bf3bb35ec2b6aa6033a963d6b5febb0cf69e917"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"0873e81642ff803faf0a50ae305d195645d83f19","unresolved":false,"context_lines":[{"line_number":310,"context_line":"\t  .flash_regs_base       \u003d 0x58004000,"},{"line_number":311,"context_line":"\t  .fsize_addr            \u003d 0x1FFF75E0,"},{"line_number":312,"context_line":"\t},"},{"line_number":313,"context_line":"\t{"},{"line_number":314,"context_line":"\t  .id                    \u003d 0x497,"},{"line_number":315,"context_line":"\t  .revs                  \u003d stm32_497_revs,"},{"line_number":316,"context_line":"\t  .num_revs              \u003d ARRAY_SIZE(stm32_497_revs),"},{"line_number":317,"context_line":"\t  .device_str            \u003d \"STM32WLEx\","},{"line_number":318,"context_line":"\t  .max_flash_size_kb     \u003d 256,"},{"line_number":319,"context_line":"\t  .has_dual_bank         \u003d false,"},{"line_number":320,"context_line":"\t  .flash_regs_base       \u003d 0x58004000,"},{"line_number":321,"context_line":"\t  .fsize_addr            \u003d 0x1FFF75E0,"},{"line_number":322,"context_line":"\t},"},{"line_number":323,"context_line":"};"},{"line_number":324,"context_line":""},{"line_number":325,"context_line":"/* flash bank stm32l4x \u003cbase\u003e \u003csize\u003e 0 0 \u003ctarget#\u003e */"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"2e76d7c5_08cff383","line":322,"range":{"start_line":313,"start_character":1,"end_line":322,"end_character":3},"updated":"2020-02-27 10:24:59.000000000","message":"this conflicts with #5450 adding the support of STM32WL devices ...","commit_id":"44e50666b4219e3df5686c296564a020a46ee6fa"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"f7984d9ecba8566de976efa4e7c4037a9b069d41","unresolved":false,"context_lines":[{"line_number":844,"context_line":"\t}"},{"line_number":845,"context_line":""},{"line_number":846,"context_line":"\tif (!stm32l4_info-\u003epart_info) {"},{"line_number":847,"context_line":"\t\tLOG_WARNING(\"Cannot identify target as an STM32L4/L4+/WB/WL/G4/G0 family device.\");"},{"line_number":848,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":849,"context_line":"\t}"},{"line_number":850,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_289bcf1c","line":847,"range":{"start_line":847,"start_character":59,"end_line":847,"end_character":61},"updated":"2020-03-01 21:31:05.000000000","message":"mention of WL (I don\u0027t mind this one too)","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"f7984d9ecba8566de976efa4e7c4037a9b069d41","unresolved":false,"context_lines":[{"line_number":915,"context_line":"\t\t\tstm32l4_info-\u003ebank1_sectors \u003d num_pages / 2;"},{"line_number":916,"context_line":"\t\t}"},{"line_number":917,"context_line":"\t\tbreak;"},{"line_number":918,"context_line":"\tcase 0x435: /* STM32L43/L44xx */"},{"line_number":919,"context_line":"\tcase 0x460: /* STM32G07/G08xx */"},{"line_number":920,"context_line":"\tcase 0x462: /* STM32L45/L46xx */"},{"line_number":921,"context_line":"\tcase 0x464: /* STM32L41/L42xx */"},{"line_number":922,"context_line":"\tcase 0x466: /* STM32G03/G04xx */"},{"line_number":923,"context_line":"\tcase 0x468: /* STM32G43/G44xx */"},{"line_number":924,"context_line":"\t\t/* single bank flash */"},{"line_number":925,"context_line":"\t\tpage_size_kb \u003d 2;"},{"line_number":926,"context_line":"\t\tnum_pages \u003d flash_size_kb / page_size_kb;"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_48d2cbd6","line":923,"range":{"start_line":918,"start_character":1,"end_line":923,"end_character":33},"updated":"2020-03-01 21:31:05.000000000","message":"0x497 (STM32WLE) should be here, but this should be managed out of this change","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"f7984d9ecba8566de976efa4e7c4037a9b069d41","unresolved":false,"context_lines":[{"line_number":972,"context_line":"\t\tnum_pages \u003d flash_size_kb / page_size_kb;"},{"line_number":973,"context_line":"\t\tstm32l4_info-\u003ebank1_sectors \u003d num_pages;"},{"line_number":974,"context_line":"\t\tbreak;"},{"line_number":975,"context_line":"\tcase 0x497: /* STM32WLEx */"},{"line_number":976,"context_line":"\t\t/* single bank flash */"},{"line_number":977,"context_line":"\t\tpage_size_kb \u003d 2;"},{"line_number":978,"context_line":"\t\tnum_pages \u003d flash_size_kb / page_size_kb;"},{"line_number":979,"context_line":"\t\tstm32l4_info-\u003ebank1_sectors \u003d num_pages;"},{"line_number":980,"context_line":"\t\tbreak;"},{"line_number":981,"context_line":"\tdefault:"},{"line_number":982,"context_line":"\t\tLOG_ERROR(\"unsupported device\");"},{"line_number":983,"context_line":"\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_e8d637c8","line":980,"range":{"start_line":975,"start_character":0,"end_line":980,"end_character":8},"updated":"2020-03-01 21:31:05.000000000","message":"conflicts with STM32WLEx support : http://openocd.zylin.com/#/c/5450/","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"f7984d9ecba8566de976efa4e7c4037a9b069d41","unresolved":false,"context_lines":[{"line_number":1077,"context_line":"\t\t\t\t(stm32l4_info-\u003edual_bank_mode ? \" dual-bank\" : \" single-bank\") : \"\");"},{"line_number":1078,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1079,"context_line":"\t} else {"},{"line_number":1080,"context_line":"\t\tsnprintf(buf, buf_size, \"Cannot identify target as an STM32L4/L4+/WB/WL/G4/G0 device\");"},{"line_number":1081,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1082,"context_line":"\t}"},{"line_number":1083,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_08d4d3bd","line":1080,"range":{"start_line":1080,"start_character":71,"end_line":1080,"end_character":73},"updated":"2020-03-01 21:31:05.000000000","message":"another mention of WL (I don\u0027t mind this one)","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"}],"src/flash/nor/stm32l4x.h":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"6bf6554a01296dca2b05fe433fc7af97d52e41a6","unresolved":false,"context_lines":[{"line_number":16,"context_line":" *   along with this program.  If not, see \u003chttp://www.gnu.org/licenses/\u003e. *"},{"line_number":17,"context_line":" ***************************************************************************/"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"#ifndef _STM32L4X_H_"},{"line_number":20,"context_line":"#define _STM32L4X_H_"},{"line_number":21,"context_line":""},{"line_number":22,"context_line":"/* Flash registers offsets */"},{"line_number":23,"context_line":"#define STM32_FLASH_ACR\t\t\t0x00"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_68c3070b","line":20,"range":{"start_line":19,"start_character":0,"end_line":20,"end_character":20},"updated":"2020-03-01 19:25:50.000000000","message":"I think the safeguard should be OPENOCD_FLASH_NOR_STM32L4X_H","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"8b877230eed7f66ffeb2e1d28cfccb0bfdecf615","unresolved":false,"context_lines":[{"line_number":16,"context_line":" *   along with this program.  If not, see \u003chttp://www.gnu.org/licenses/\u003e. *"},{"line_number":17,"context_line":" ***************************************************************************/"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"#ifndef _STM32L4X_H_"},{"line_number":20,"context_line":"#define _STM32L4X_H_"},{"line_number":21,"context_line":""},{"line_number":22,"context_line":"/* Flash registers offsets */"},{"line_number":23,"context_line":"#define STM32_FLASH_ACR\t\t\t0x00"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"2e76d7c5_48764bd7","line":20,"range":{"start_line":19,"start_character":0,"end_line":20,"end_character":20},"in_reply_to":"2e76d7c5_68c3070b","updated":"2020-03-02 08:10:40.000000000","message":"Right, changed.","commit_id":"ee9d45713bd85aa60eab306694fc3dc536459ab9"}],"tcl/target/stm32g0x.cfg":[{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"52b748ece92bf38bd9a8ebfc14653591b35a326e","unresolved":false,"context_lines":[{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#jtag scan chain"},{"line_number":26,"context_line":"if { [info exists CPUTAPID] } {"},{"line_number":27,"context_line":"   set _CPUTAPID $CPUTAPID"},{"line_number":28,"context_line":"} else {"},{"line_number":29,"context_line":"\t# Section 37.5.5 - corresponds to Cortex-M0+"},{"line_number":30,"context_line":"\tset _CPUTAPID 0x0bc11477"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_4ab72382","line":27,"updated":"2019-09-01 21:31:31.000000000","message":"indentation with spaces here?","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"b7492ad999541ea69a0a886d2156b675897749a1","unresolved":false,"context_lines":[{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#jtag scan chain"},{"line_number":26,"context_line":"if { [info exists CPUTAPID] } {"},{"line_number":27,"context_line":"   set _CPUTAPID $CPUTAPID"},{"line_number":28,"context_line":"} else {"},{"line_number":29,"context_line":"\t# Section 37.5.5 - corresponds to Cortex-M0+"},{"line_number":30,"context_line":"\tset _CPUTAPID 0x0bc11477"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_651c907d","line":27,"in_reply_to":"8e7fc396_4ab72382","updated":"2019-10-06 17:25:20.000000000","message":"Right, typo ...","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"52b748ece92bf38bd9a8ebfc14653591b35a326e","unresolved":false,"context_lines":[{"line_number":45,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":46,"context_line":"flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"# Common knowledge tells SWD speed should be \u003c\u003d F_CPU/6."},{"line_number":49,"context_line":"# F_CPU after reset is HSI16 16MHz, so use F_JTAG \u003d 1000 kHz to stay on"},{"line_number":50,"context_line":"# the safe side."},{"line_number":51,"context_line":"adapter_khz 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_eaab8f19","line":48,"updated":"2019-09-01 21:31:31.000000000","message":"source?","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"37aa2c7089cc52fe48cfa4edba27c8a8197d7185","unresolved":false,"context_lines":[{"line_number":45,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":46,"context_line":"flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"# Common knowledge tells SWD speed should be \u003c\u003d F_CPU/6."},{"line_number":49,"context_line":"# F_CPU after reset is HSI16 16MHz, so use F_JTAG \u003d 1000 kHz to stay on"},{"line_number":50,"context_line":"# the safe side."},{"line_number":51,"context_line":"adapter_khz 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"2e76d7c5_b34d1842","line":48,"in_reply_to":"8e7fc396_8521acae","updated":"2019-12-15 11:02:42.000000000","message":"Andreas, I believe this limit has no meaning on SWD. Please read http://openocd.zylin.com/3366\nespecially Andreas Fritiofson\u0027s comment from Jul 5th.\n\nIn practice Nucleo G070RB connected to a FT232H adapter works happily @ adapter_khz somewhat higher than HCLK and if stm32g0x.dap memaccess is increased or SWD WAIT correctly handled adapter_khz can be more than 10 times HCLK. I recommend to keep SWCLK freq \u003c HCLK to be safe.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"b7492ad999541ea69a0a886d2156b675897749a1","unresolved":false,"context_lines":[{"line_number":45,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":46,"context_line":"flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"# Common knowledge tells SWD speed should be \u003c\u003d F_CPU/6."},{"line_number":49,"context_line":"# F_CPU after reset is HSI16 16MHz, so use F_JTAG \u003d 1000 kHz to stay on"},{"line_number":50,"context_line":"# the safe side."},{"line_number":51,"context_line":"adapter_khz 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_8521acae","line":48,"in_reply_to":"8e7fc396_eaab8f19","updated":"2019-10-06 17:25:20.000000000","message":"Maybe better: rumors say ...\nExcept for the H7 never saw explicit specs for the entire STM32 family. ARM\u0027s documents don\u0027t give any hint, either.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"}],"tcl/target/stm32g4x.cfg":[{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"52b748ece92bf38bd9a8ebfc14653591b35a326e","unresolved":false,"context_lines":[{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32g4x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Work-area is a space in RAM used for flash programming"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_0aa92b21","line":14,"updated":"2019-09-01 21:31:31.000000000","message":"This file has completely different spacing to the other file.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"b7492ad999541ea69a0a886d2156b675897749a1","unresolved":false,"context_lines":[{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32g4x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Work-area is a space in RAM used for flash programming"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_2516985b","line":14,"in_reply_to":"8e7fc396_0aa92b21","updated":"2019-10-06 17:25:20.000000000","message":"Hm, yes. Indention varies grossly among all cfg files. Some three spaces, some four, some one tab per level, even mixed in one file. Not sure about a good choice.\n\nBut for new files it should be consistent within each file, no doubt.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001631,"name":"Guillaume Revaillot","email":"guillaume@ppp0.dev","username":"grevaillot"},"change_message_id":"46fd21bfe5d6d9942e11ba23ecefa859bfcf2038","unresolved":false,"context_lines":[{"line_number":81,"context_line":"\t# CPU comes out of reset with HSION | HSIRDY."},{"line_number":82,"context_line":"\t# Use HSI 16 MHz clock, compliant even with VOS \u003d\u003d 2."},{"line_number":83,"context_line":"\t# 1 WS compliant with VOS \u003d\u003d 2 and 16 MHz."},{"line_number":84,"context_line":"\tmww 0x40022000 0x00000101   ;# FLASH_ACR \u003d PRFTBE | 1(Latency)"},{"line_number":85,"context_line":"\tmww 0x40021000 0x00000010   ;# RCC_CR \u003d HSION"},{"line_number":86,"context_line":"\tmww 0x40021008 0x00000005   ;# RCC_CFGR \u003d HSI16"},{"line_number":87,"context_line":"\t# Boost JTAG frequency"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_2a3f47d5","line":84,"updated":"2019-09-03 13:16:56.000000000","message":"this mww will clear the DBG_SWEN bit - disabling \"core debug access\".","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"b7492ad999541ea69a0a886d2156b675897749a1","unresolved":false,"context_lines":[{"line_number":81,"context_line":"\t# CPU comes out of reset with HSION | HSIRDY."},{"line_number":82,"context_line":"\t# Use HSI 16 MHz clock, compliant even with VOS \u003d\u003d 2."},{"line_number":83,"context_line":"\t# 1 WS compliant with VOS \u003d\u003d 2 and 16 MHz."},{"line_number":84,"context_line":"\tmww 0x40022000 0x00000101   ;# FLASH_ACR \u003d PRFTBE | 1(Latency)"},{"line_number":85,"context_line":"\tmww 0x40021000 0x00000010   ;# RCC_CR \u003d HSION"},{"line_number":86,"context_line":"\tmww 0x40021008 0x00000005   ;# RCC_CFGR \u003d HSI16"},{"line_number":87,"context_line":"\t# Boost JTAG frequency"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8e7fc396_451b9482","line":84,"in_reply_to":"8e7fc396_2a3f47d5","updated":"2019-10-06 17:25:20.000000000","message":"Right, changed to \u0027mmw\u0027 here and in stm32g0x.cfg, too.","commit_id":"434cf2f8a25a8d082f4c955c21761dcd45570516"}]}