)]}'
{"tcl/board/adsp-sc584-ezbrd.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ac64e11a7b05c4f60b3aadce125d8fcde8e4bfd6","unresolved":false,"context_lines":[{"line_number":1,"context_line":"#"},{"line_number":2,"context_line":"# Analog Devices ADSP-SC584-EZBRD evaluation board"},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# evaluation boards by Analog Devices (and designs derived from them) use a non-standard 10-pin 0.05\" ARM Cortex Debug Connector"},{"line_number":5,"context_line":"# pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST"},{"line_number":6,"context_line":"# as a result, a standards-compliant debug pod will only force the processor\u0027s debug interface into reset, preventing usage"},{"line_number":7,"context_line":"# so, a connector adapter must be employed on these boards to isolate or otherwise prevent /TRST from being asserted"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with this board, but"},{"line_number":10,"context_line":"# this is an ARM target (and subject to the qualification above) many ARM debug pods should be compatible"},{"line_number":11,"context_line":""},{"line_number":12,"context_line":"source [find interface/cmsis-dap.cfg]"},{"line_number":13,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0e6cb3ef_1d53b71b","line":10,"range":{"start_line":4,"start_character":0,"end_line":10,"end_character":105},"updated":"2019-01-18 08:16:51.000000000","message":"Please reformat lines not to exceed ~80 columns","commit_id":"ddf96a363e828b0890694af6068c4ba06883e9b2"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ac64e11a7b05c4f60b3aadce125d8fcde8e4bfd6","unresolved":false,"context_lines":[{"line_number":14,"context_line":"# Analog\u0027s silicon supports SWD and JTAG, but their ICE is limited to JTAG"},{"line_number":15,"context_line":"# SWD is chosen here, as:"},{"line_number":16,"context_line":"# 1) SWD is more efficient"},{"line_number":17,"context_line":"# 2) OpenOCD in JTAG mode assumes /TRST usage"},{"line_number":18,"context_line":"# /TRST is not part of the \"Cortex\" 10-pin ARM connector (which is why Analog overloaded the pinout)"},{"line_number":19,"context_line":""},{"line_number":20,"context_line":"transport select swd"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0e6cb3ef_7d4e7374","line":17,"range":{"start_line":17,"start_character":5,"end_line":17,"end_character":45},"updated":"2019-01-18 08:16:51.000000000","message":"It does not until TRST is explicitly configured in reset_config","commit_id":"ddf96a363e828b0890694af6068c4ba06883e9b2"}],"tcl/target/adsp-sc58x.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ac64e11a7b05c4f60b3aadce125d8fcde8e4bfd6","unresolved":false,"context_lines":[{"line_number":38,"context_line":"   sc58x_enabledebug $_TARGETNAME"},{"line_number":39,"context_line":"}"},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"proc sc58x_enabledebug {target} {"},{"line_number":42,"context_line":"   # Enable debugging functionality by setting relevant bits in the TAPC_DBGCTL register"},{"line_number":43,"context_line":"   # it is not possible to halt the target unless these register bits have been set"},{"line_number":44,"context_line":"   ap0.mem mww 0x31131000 0xFFFF"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0e6cb3ef_5d492f69","line":41,"range":{"start_line":41,"start_character":24,"end_line":41,"end_character":30},"updated":"2019-01-18 08:16:51.000000000","message":"Not needed now","commit_id":"ddf96a363e828b0890694af6068c4ba06883e9b2"}]}