)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"74053f699b640bf2d55615172c26f51286482920","unresolved":true,"context_lines":[{"line_number":7,"context_line":"target/aarch64: MRS/MSR support for system register access"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"AArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR"},{"line_number":10,"context_line":"should be used."},{"line_number":11,"context_line":""},{"line_number":12,"context_line":"AArch64 System Registers can be accessed by mrs/msr commands,"},{"line_number":13,"context_line":"both by name and (op0, op1, CRn, CRm, op2). The read command"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":13,"id":"a87b233f_a3a47a5f","line":10,"updated":"2022-04-29 08:00:36.000000000","message":"The OpenOCD target aarch64 covers devices ARMv8-A (soon also ARMv8-R).\nThese devices can switch, at runtime, between AArch64 and AArch32 modes.\nGDB is unable to handle this switch, but that\u0027s another problem (I have no info about LLDB).\nThis patch only adds AArch64 commands for MRS/MSR.\nWhat about AArch32 commands MCR/MRC?\nWhat about checking for mode AArch64 to know the commands are valid and can be executed?\nI\u0027m not asking to modify further this patch, we can improve it in following ones; I\u0027m just asking your feedback.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"change_message_id":"38043d26cd38edd6e540c17a59a48f7c294c4625","unresolved":false,"context_lines":[{"line_number":7,"context_line":"target/aarch64: MRS/MSR support for system register access"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"AArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR"},{"line_number":10,"context_line":"should be used."},{"line_number":11,"context_line":""},{"line_number":12,"context_line":"AArch64 System Registers can be accessed by mrs/msr commands,"},{"line_number":13,"context_line":"both by name and (op0, op1, CRn, CRm, op2). The read command"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":13,"id":"9032c148_55690c08","line":10,"in_reply_to":"6322476f_9cbb7a58","updated":"2022-06-27 20:21:31.000000000","message":"The mrc/mcr behavior is merged.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"40f0731b3eba60ce9eb4b5e8443677855329b33f","unresolved":true,"context_lines":[{"line_number":7,"context_line":"target/aarch64: MRS/MSR support for system register access"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"AArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR"},{"line_number":10,"context_line":"should be used."},{"line_number":11,"context_line":""},{"line_number":12,"context_line":"AArch64 System Registers can be accessed by mrs/msr commands,"},{"line_number":13,"context_line":"both by name and (op0, op1, CRn, CRm, op2). The read command"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":13,"id":"b6afbe7e_ee29ac81","line":10,"in_reply_to":"a87b233f_a3a47a5f","updated":"2022-04-29 14:54:28.000000000","message":"We have a patch in our downstream openocd that adds mrc/mcr to the aarch64 target and which allows us to read/write system registers while in AArch32 state. Let me see if we can get it submitted as well since it proved useful, too.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"6d6abe8b414b6049eb060000512ac1aba2054b08","unresolved":true,"context_lines":[{"line_number":7,"context_line":"target/aarch64: MRS/MSR support for system register access"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"AArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR"},{"line_number":10,"context_line":"should be used."},{"line_number":11,"context_line":""},{"line_number":12,"context_line":"AArch64 System Registers can be accessed by mrs/msr commands,"},{"line_number":13,"context_line":"both by name and (op0, op1, CRn, CRm, op2). The read command"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":13,"id":"6322476f_9cbb7a58","line":10,"in_reply_to":"b6afbe7e_ee29ac81","updated":"2022-05-06 22:05:33.000000000","message":"Replying to myself, I had forgotten that Kamal had contributed this change a while back:\n\nhttps://review.openocd.org/c/openocd/+/4483/","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"8aa9af0f8912d8c11cedcc42ed8e634d10c4ab3f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"56ed5332_75876ab5","updated":"2022-02-23 11:09:44.000000000","message":"On my x86_64 PC this patch increases the memory footprint of openocd by 27%\n   text\t   data\t    bss\t    dec\t    hex\tfilename\n3757915\t 342208\t 532560\t4632683\t 46b06b\topenocd.before\n4048587\t1315008\t 532560\t5896155\t 59f7db\topenocd.after\nmainly due to the table.\nI see some way to reduce the memory size of the table, but it should not save that much.\nI don\u0027t want to delay this further, so I think that after this get merged would be good to have a compile option to remove the table and let read command only print the raw values, not decoded.\nI also see some coding style mismatch that can be fixed later on.\nLet\u0027s wait for Daniel Glöckner to reply to Florian\u0027s question.","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1001918,"name":"Dietmar May","email":"dietmar.may@outlook.com","username":"dmay"},"change_message_id":"5fae4f4db46a9fe786aa82a11c8f633b63a8530b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"cedfc35f_4121c653","updated":"2022-06-27 21:58:46.000000000","message":"Copied from $7054\n\nI submitted patches for this (#7054) 1 year ago. #6474 \n\nhttps://review.openocd.org/c/openocd/+/6474\n\nI did get 1 comment after 3.5 months that there was an older unmerged patch, patch #5003 with more  features.\n\nhttps://review.openocd.org/c/openocd/+/5003\n\nAFAICS, that\u0027s never made it into OpenOCD, either.\n\nIn the mean time, OpenOCD is not terribly useful for aarch64 without some kind of support, since MRC/MRS + MCR/MSR is pretty fundamental for ARM targets.\n\nPatch #5003 \"increases the memory footprint of openocd by 27%\", which seems like a hefty penalty for such a simple operation, especially for users with other (non-aarch64) targets. Similar support for ARMv7 would be really nice, too; but would substantially increase the footprint further.\n\nMeanwhile, none of this is actually necessary for MSR / MRS support. The architecture takes several values containing groups of encoded bits, so the bare minimum to do the job is a minor adaptation of the existing MCR/MRC code.\n\nPerhaps the best balance would be found by adapting that 32 bit MCR/MRC code to support 64 MSR/MRS operations, and simply use encoded numeric (bit group) values. That\u0027s already done in #6474.\n\nThen, instead of adding bloat to OpenOCD for a specific architecture, which is not needed for other targets, create a standalone tool to generate the MRS / MCR bit group values from mnemonics.\n\nThe generate_arm_sysreg_table.py code could probably be adapted for ARMv8 / aarch64. It should be straightforward to adapt that for ARMv7. With careful design, it might be generalizable to other architecture families.\n\nSuch a tool could even read a target-specific .conf file, look for specially formatted comments, and emit an updated OpenOCD .conf file containing encoded values with comments to indicate the mnemonics (sort of like older compilers which emitted assembly code, or cfront which generated C code from C++).\n\nThis may well be a design decision that impacts the project philosophy of OpenOCD: keep it lean and mean, and move target-specific bulk to external tools; or take a kitchen-sink approach, and add all useful target-specific bling to the core application.\n\nWhatever the case, clearly *something* needs to be done; or OpenOCD users will continue to re-invent the wheel, because they need it and OpenOCD doesn\u0027t currently support it.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001918,"name":"Dietmar May","email":"dietmar.may@outlook.com","username":"dmay"},"change_message_id":"7ae63c263cfa3f5f5e76d2d58baa8ad1c4296f6c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"045e7301_10fa082c","updated":"2022-06-28 02:35:33.000000000","message":"I like the idea of register names. Might have used them if they had been available when I added my target.\n\nHowever, I calculated the values once, and used them for the past year of debugging. Never had to go back and change them.\n\nFor me, the real issue is need vs. want. I can drive a car without heated leather seats, or even air conditioning; but I can\u0027t drive it without tires, wheels, an engine and transmission.\n\nI really appreciate having OpenOCD available - and all of the hard work that\u0027s gone into making it perform as well as it does. I was able to bring up a multi-core aarch64 ASIC prototyping board using a $70 FTDI JTAG probe + OpenOCD. The other developers in my group are all using a $10,000 probe from a well known embedded tool company. Now I\u0027m working with real silicon and I\u0027m able to bootstrap firmware onto an ASIC development board using the same $70 probe + OpenOCD, and connect with GDB. Very nice!\n\nBut none of that would have been possible without MRS / MSR support - which still isn\u0027t available in OpenOCD.\n\nThis patch is over 3 years old, and still not merged. My patch is almost 1 year old, and the code is much simpler and straightforward. Someone could have reviewed it in just a few minutes of time. Instead, I\u0027ve had to maintain my own (friendly) fork of OpenOCD, so I can have a tool without which I can\u0027t use OpenOCD.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"change_message_id":"38043d26cd38edd6e540c17a59a48f7c294c4625","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"a1e2dbee_9be385b2","updated":"2022-06-27 20:21:31.000000000","message":"I\u0027ve been testing this against an rpi4, and it appears to work great, ex:\n\n\u003e bcm2711.cpu1 aarch64 mrs mpidr_el1 decode\nMPIDR_EL1 [11_000_0000_0000_101]: 0x0000000080000001\n.Aff3 \u003d0x0 \u003d0b00000000\n.U \u003d0x0 \u003d0b0\n.MT \u003d0x0 \u003d0b0\n.Aff2 \u003d0x0 \u003d0b00000000\n.Aff1 \u003d0x0 \u003d0b00000000\n.Aff0 \u003d0x1 \u003d0b00000001\n\n\u003e aarch64 mrs ttbr0_el1                   \nTTBR0_EL1 [11_000_0010_0000_000]: 0x0000000063336000\n\n\u003e aarch64 msr ttbr0_el1 0x0000000063337000\n\u003e aarch64 mrs ttbr0_el1                   \nTTBR0_EL1 [11_000_0010_0000_000]: 0x0000000063337000\n\nI\u0027ve also, taken a quick look at the .c/.h files and they appear to be what I would expect.\n\nI\u0027m not sure if this project uses tested-by/reviewed-by tags but,\n\ntested-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\n\nand \n\nreviewed-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\n\nThanks,","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"5a22ebf5af27992a630aeaea0448cf0ee51cd7ea","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"e2900904_eb62d5a9","updated":"2022-06-28 03:19:45.000000000","message":"Is the license of the register definition provided by ARM compatible with the GPL?","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"d6ae879e6dec91dfcce0e0c3a34e5eac370f1134","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"14d73e4f_b6689989","updated":"2022-04-26 23:29:03.000000000","message":"Looks good now.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"33ecd850442559e9fc2b09319a24dcc2ef2134aa","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":13,"id":"a749d198_6d430600","in_reply_to":"2d6c06a0_c992e0ce","updated":"2022-09-26 15:20:43.000000000","message":"I suppose that a new version with the auto-generated headers would allow us to get going, let me try to get that submitted later this week.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"change_message_id":"ade3dcd1d9c73bf4bd916760cd4564037e361c34","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"a9b2c4ce_565197a4","in_reply_to":"35977032_a56d14e7","updated":"2022-06-28 01:50:03.000000000","message":"Except we are talking about a 4M binary. The majority of size increase are due the register descriptions. Moving them out of the binary doesn\u0027t really do anything to the overall size of the package (likely increases it), and either slows down the commands by having to dynamically parse the file, or bloats up the in memory footprint by preparsing it. Presumably what is needed is to build without the aarch64 support if the binary is getting too big (!).\n\nOTOH, the user interface is significantly improved by having descriptions of the registers in place, rather than having to hand encode/decode them with the ref manual handy. I find the bit field formatting a bit clumsy but its _very_ helpful.\n\nBTW: By comparison gdb is consuming ~14M for each of a half dozen architectures on my machine, not counting a fairly long set of shared library dependencies.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001918,"name":"Dietmar May","email":"dietmar.may@outlook.com","username":"dmay"},"change_message_id":"7ae63c263cfa3f5f5e76d2d58baa8ad1c4296f6c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"6a8c18c0_e45a8289","in_reply_to":"35977032_a56d14e7","updated":"2022-06-28 02:35:33.000000000","message":"There is a limited set - looks like CP14 and CP15.\n\nFrom DDI0406C_d_armv7ar_arm.pdf\n\nA8-494: refs B3-1444, B5-1769 Additional rules for MCR to CP14 and CP15 for VMSA \u0026 PMSA\n\nIn particular, CP14 (debug) is defined at C6-2112\nCP15 (memory control) is defined at B3-1466 (VMSA) and B5-1780 (PMSA)\n\nOne thing I found interesting is that MRS / MSR are also present in ARMv7a, apparently solely for accessing the APSR.\n\nOther CP registers are either reserved or presumably implementation dependent.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1002005,"name":"Jeremy Linton","email":"lintonrjeremy@gmail.com","username":"jlinton"},"change_message_id":"73ce439518b59b863dec4c23ab42cc78c9fb7994","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":13,"id":"2d6c06a0_c992e0ce","in_reply_to":"92c4a568_5bb93ac5","updated":"2022-09-02 18:39:14.000000000","message":"The summer vacations and other issues have keep this from progressing internally, hopefully that should be changing soon. I wonder if the best short term solution is to check this in minus the complete register definition file, under the assumption that it might take a while yet. That way the MRS/MSR functionality exists, and in the future a complete register definition file can be added. This actually plays into the way I suspect approval if/when it happens would look like anyway.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"2c4cf35cf28701b62accad964b19817034980ac5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"640ee5d7_22912a2a","in_reply_to":"a749d198_6d430600","updated":"2023-01-03 21:01:45.000000000","message":"Done","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"647277f7983b5fea17f07ea859984f50a37ab69c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"35977032_a56d14e7","in_reply_to":"cedfc35f_4121c653","updated":"2022-06-27 22:06:42.000000000","message":"\u003e The generate_arm_sysreg_table.py code could probably be adapted for ARMv8 / aarch64. It should be straightforward to adapt that for ARMv7. With careful design, it might be generalizable to other architecture families.\n\nI am not sure that there is a published machine readable list of system registers for ARMv7 or any other architecture than ARMv8 for that matter.\n\n\u003e \n\u003e Such a tool could even read a target-specific .conf file, look for specially formatted comments, and emit an updated OpenOCD .conf file containing encoded values with comments to indicate the mnemonics (sort of like older compilers which emitted assembly code, or cfront which generated C code from C++).\n\nOK, this is actually a good idea, rather than embedding the table in the binary...","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"change_message_id":"b580a086587c0972df0e257330f860f57a88287b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"92c4a568_5bb93ac5","in_reply_to":"e2900904_eb62d5a9","updated":"2022-07-07 11:44:57.000000000","message":"Its been a few days, I\u0027m still here. It is a good idea to clarify this, and get a license tag applied to the generated file. So, it is being looked at, but legal questions take longer.","commit_id":"50f307525b11e92c2c710ffbc9df851933475c32"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"36220997_cd394d9c","updated":"2023-01-04 08:00:25.000000000","message":"Sad to see the code for register names and decoding go until the license issue has been clarified, but if we do that, it should be removed completely.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1002090,"name":"Philipp Schulz","email":"schulz.phil@gmx.de","username":"dinkelhacker"},"change_message_id":"a6b5e5ca6bd07f8cac30d3b8bef74d62fca00a68","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"4742532f_7c25d5e0","updated":"2022-12-05 13:49:58.000000000","message":"Tested it with a raspberry pi4. Works fine for me.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1002090,"name":"Philipp Schulz","email":"schulz.phil@gmx.de","username":"dinkelhacker"},"change_message_id":"80addd3715535383336ff26d7fc73c8cdf2629b0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"2087c564_6f9114d8","updated":"2022-12-06 07:44:45.000000000","message":"Tested it with a raspberry pi4. Works fine for me. (sorry had to resubmit bc. i forgot to check the resolved box)","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"bac3e245bc81931f2dc997f8a1f2b7d6925c2b21","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"1c983e68_e8b7dfb5","in_reply_to":"36220997_cd394d9c","updated":"2023-01-04 19:26:08.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"c124b36b186e5f2573e880ac6790f7bd2ab9de32","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":17,"id":"90d96e9f_e9e446c2","updated":"2023-01-05 00:52:30.000000000","message":"Looks good now","commit_id":"04e892d48447f7fb7b521dfb74941c441962b1f1"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"c18794a32bee420b4a7e39d83ff48a4ca3ee796f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":18,"id":"5c1dede5_0adc16b1","updated":"2023-07-11 02:14:24.000000000","message":"Rebased and tested on my target; ping?","commit_id":"ebe9e819e8717eb81b5e7c68e08dd7db7fcf5fd4"},{"author":{"_account_id":1001891,"name":"Michele Bisogno","email":"michele.bisogno.ct@renesas.com","username":"MicBiso"},"change_message_id":"36a679977ba7d39d2fba402d30faebec3a133cf6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":19,"id":"bafac585_f68360da","updated":"2024-04-12 06:41:04.000000000","message":"Hi,\nwhy hasn\u0027t this patch been merged yet?\nNo serious AArch64 debugging is possible without it.\nThe previous version with decoding was great but the latest one is good enough.","commit_id":"3c02afe1d45874605728ef0171ed8a612e35716d"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"55d6ff8590d5c2480cb89ad4fd1bf675f65ba323","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":19,"id":"b0bb1e62_8d25ce5b","updated":"2023-10-27 01:23:50.000000000","message":"Ping^2. I\u0027ve been using this patch for several months to debug various issues and it would be good for it to land upstream. Most recently I discovered that this patch did not support registers with op0[1]\u003d0b0 which includes several of the pseudo-registers used for CMOs, the latest update fixes that.","commit_id":"3c02afe1d45874605728ef0171ed8a612e35716d"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"77dff82f22718a61e69980328e26a0c5cef841b5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":19,"id":"f39d8d15_a357ee5a","in_reply_to":"bafac585_f68360da","updated":"2024-08-06 22:32:29.000000000","message":"I don\u0027t think there is a good story on this one, short of the XML file that was used to source the register names/bitfields did not have a clear license.\n\nSince then the ARM Linux kernel has its own database that we might be able to leverage:\n\nhttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/tools/sysreg","commit_id":"3c02afe1d45874605728ef0171ed8a612e35716d"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"ae0094223b450d9d481e3bd7302702781d636627","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":19,"id":"fcd20a27_00e0bf64","in_reply_to":"f39d8d15_a357ee5a","updated":"2024-08-06 22:51:43.000000000","message":"The system register names are largely a convenience feature though and I don\u0027t see why it should be a prerequisite for this patch to land. For my part I\u0027ve been using this patch together with a script that I wrote for looking up the op0, op1, CRn, CRm, op2 values from a copy of the XML file that I downloaded. It\u0027s basically this:\n```\n$ cat ~/bin/sysreg\n#!/bin/sh\n\ngrep -i -B7 \u0027\u003centry\u003e\u0027\"$1\"\u0027\u003c/entry\u003e\u0027 ~/Downloads/SysReg_xml_A_profile-2023-06/SysReg_xml_A_profile-2023-06/enc_index.xml\n```\nAnother option besides Linux\u0027s database is the one that LLVM uses which includes more registers including the EL3 registers but is missing the field descriptions.\n\nhttps://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64SystemOperands.td","commit_id":"3c02afe1d45874605728ef0171ed8a612e35716d"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"9345631b2149091fa4d316eca1c4dd60e118d6f0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":19,"id":"c31c092a_a82fbcc3","in_reply_to":"fcd20a27_00e0bf64","updated":"2024-08-06 22:55:19.000000000","message":"Oh right, I have been on and off that patch set for so long that I forgot there was even a version posted with the friendly register decoding.","commit_id":"3c02afe1d45874605728ef0171ed8a612e35716d"}],"doc/openocd.texi":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":9175,"context_line":"@option{on}."},{"line_number":9176,"context_line":"@end deffn"},{"line_number":9177,"context_line":""},{"line_number":9178,"context_line":"@deffn Command {aarch64 mrs} [|sysreg|op0 op1 CRn CRm op2]"},{"line_number":9179,"context_line":"Read the system register encoded with"},{"line_number":9180,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2} or"},{"line_number":9181,"context_line":"with name @var{sysreg}"}],"source_content_type":"text/x-texinfo","patch_set":7,"id":"6ec1af18_6d2d7541","line":9178,"updated":"2021-06-28 19:31:44.000000000","message":"the syntax should be:\n{aarch64 mrs} [sysreg|op0 op1 CRn CRm op2]\nwhitout the \"|\" before \"sysreg\"","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":9180,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2} or"},{"line_number":9181,"context_line":"with name @var{sysreg}"},{"line_number":9182,"context_line":"using the MSR instruction. Run without arguments to list all system registers."},{"line_number":9183,"context_line":"(Uses x0 register)"},{"line_number":9184,"context_line":"@end deffn"},{"line_number":9185,"context_line":""},{"line_number":9186,"context_line":"@deffn Command {aarch64 msr} [|sysreg value|op0 op1 CRn CRm op2 value]"}],"source_content_type":"text/x-texinfo","patch_set":7,"id":"6ec1af18_0d22b150","line":9183,"updated":"2021-06-28 19:31:44.000000000","message":"the use of x0 is an internal detail, not relevant for the user. OpenOCD will take care of handling it.","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":9183,"context_line":"(Uses x0 register)"},{"line_number":9184,"context_line":"@end deffn"},{"line_number":9185,"context_line":""},{"line_number":9186,"context_line":"@deffn Command {aarch64 msr} [|sysreg value|op0 op1 CRn CRm op2 value]"},{"line_number":9187,"context_line":"Write @var{value} to the system register encoded with"},{"line_number":9188,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2} or"},{"line_number":9189,"context_line":"with name @var{sysreg}"}],"source_content_type":"text/x-texinfo","patch_set":7,"id":"6ec1af18_2d276d61","line":9186,"updated":"2021-06-28 19:31:44.000000000","message":"same here, no \"|\" before \"sysreg value\"","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":9188,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2} or"},{"line_number":9189,"context_line":"with name @var{sysreg}"},{"line_number":9190,"context_line":"using the MSR instruction. Run without arguments to list all system registers."},{"line_number":9191,"context_line":"(Uses x0 register)"},{"line_number":9192,"context_line":"@end deffn"},{"line_number":9193,"context_line":""},{"line_number":9194,"context_line":"@section EnSilica eSi-RISC Architecture"}],"source_content_type":"text/x-texinfo","patch_set":7,"id":"6ec1af18_cd1b4920","line":9191,"updated":"2021-06-28 19:31:44.000000000","message":"same here, internal detail","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[{"line_number":10303,"context_line":"@deffn Command {aarch64 mrs} op0 op1 CRn CRm op2"},{"line_number":10304,"context_line":"Read the system register encoded with"},{"line_number":10305,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2}"},{"line_number":10306,"context_line":"using the MRS instruction. Run without arguments to list all system registers."},{"line_number":10307,"context_line":"Specify @var{decode} to show the bit by bit decoding of the register."},{"line_number":10308,"context_line":"@end deffn"},{"line_number":10309,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":16,"id":"238229da_3eba2bf1","line":10306,"updated":"2023-01-04 08:00:25.000000000","message":"The code no longer lists the registers and doesn\u0027t decode them. These sentences should be removed. Same for msr below.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"bac3e245bc81931f2dc997f8a1f2b7d6925c2b21","unresolved":false,"context_lines":[{"line_number":10303,"context_line":"@deffn Command {aarch64 mrs} op0 op1 CRn CRm op2"},{"line_number":10304,"context_line":"Read the system register encoded with"},{"line_number":10305,"context_line":"@var{op0}, @var{op1}, @var{CRn}, @var{CRm}, @var{op2}"},{"line_number":10306,"context_line":"using the MRS instruction. Run without arguments to list all system registers."},{"line_number":10307,"context_line":"Specify @var{decode} to show the bit by bit decoding of the register."},{"line_number":10308,"context_line":"@end deffn"},{"line_number":10309,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":16,"id":"658fae72_1150a0a2","line":10306,"in_reply_to":"238229da_3eba2bf1","updated":"2023-01-04 19:26:08.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"}],"src/target/Makefile.am":[{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[{"line_number":209,"context_line":"\t%D%/cortex_m.h \\"},{"line_number":210,"context_line":"\t%D%/cortex_a.h \\"},{"line_number":211,"context_line":"\t%D%/aarch64.h \\"},{"line_number":212,"context_line":"\t%D%/aarch64_system_registers.h \\"},{"line_number":213,"context_line":"\t%D%/embeddedice.h \\"},{"line_number":214,"context_line":"\t%D%/etb.h \\"},{"line_number":215,"context_line":"\t%D%/etm.h \\"}],"source_content_type":"application/octet-stream","patch_set":16,"id":"999be219_f7ce3e46","line":212,"updated":"2023-01-04 08:00:25.000000000","message":"Again, the header file should be omitted for now.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"bac3e245bc81931f2dc997f8a1f2b7d6925c2b21","unresolved":false,"context_lines":[{"line_number":209,"context_line":"\t%D%/cortex_m.h \\"},{"line_number":210,"context_line":"\t%D%/cortex_a.h \\"},{"line_number":211,"context_line":"\t%D%/aarch64.h \\"},{"line_number":212,"context_line":"\t%D%/aarch64_system_registers.h \\"},{"line_number":213,"context_line":"\t%D%/embeddedice.h \\"},{"line_number":214,"context_line":"\t%D%/etb.h \\"},{"line_number":215,"context_line":"\t%D%/etm.h \\"}],"source_content_type":"application/octet-stream","patch_set":16,"id":"87a89f79_07ec459b","line":212,"in_reply_to":"999be219_f7ce3e46","updated":"2023-01-04 19:26:08.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"ee84368c_ea783c89","line":270,"updated":"2023-01-04 08:00:25.000000000","message":"unrelated whitespace change","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"bac3e245bc81931f2dc997f8a1f2b7d6925c2b21","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"9ef0642a_a1669ec4","line":270,"in_reply_to":"ee84368c_ea783c89","updated":"2023-01-04 19:26:08.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"}],"src/target/aarch64.c":[{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"31de8060c1cc53ac6d946dd687e64f5b69a62646","unresolved":false,"context_lines":[{"line_number":2622,"context_line":"\t}"},{"line_number":2623,"context_line":""},{"line_number":2624,"context_line":"\tif (rt \u003e 31) {"},{"line_number":2625,"context_line":"\t\t\tcommand_print(CMD_CTX, \"Rt should be \u003c\u003d 32\");"},{"line_number":2626,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2627,"context_line":"\t}"},{"line_number":2628,"context_line":"\tif (op0 \u003e 3) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ee703fc5_b9589f5a","line":2625,"updated":"2019-03-31 01:41:53.000000000","message":"Should this be \u003c\u003d 31?","commit_id":"7b0edab551132b890cb393c8fecd116892954b15"},{"author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"change_message_id":"d4dd033e111ef384ce0767f25f205ee4c26a6fa3","unresolved":false,"context_lines":[{"line_number":2622,"context_line":"\t}"},{"line_number":2623,"context_line":""},{"line_number":2624,"context_line":"\tif (rt \u003e 31) {"},{"line_number":2625,"context_line":"\t\t\tcommand_print(CMD_CTX, \"Rt should be \u003c\u003d 32\");"},{"line_number":2626,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2627,"context_line":"\t}"},{"line_number":2628,"context_line":"\tif (op0 \u003e 3) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ee703fc5_fc6a857d","line":2625,"in_reply_to":"ee703fc5_b9589f5a","updated":"2019-03-31 16:26:32.000000000","message":"Actually, I think the if condition should be \u003e 30, and the message should be \u003c\u003d 30, since x30 is the last register in AArch64.","commit_id":"7b0edab551132b890cb393c8fecd116892954b15"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"31de8060c1cc53ac6d946dd687e64f5b69a62646","unresolved":false,"context_lines":[{"line_number":2644,"context_line":"\tif (op2 \u003e 7) {"},{"line_number":2645,"context_line":"\t\t\tcommand_print(CMD_CTX, \"op2 should be \u003c\u003d 7\");"},{"line_number":2646,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2647,"context_line":"\t}"},{"line_number":2648,"context_line":""},{"line_number":2649,"context_line":"\tuint32_t systemreg \u003d (op0 \u003c\u003c 14) | (op1 \u003c\u003c 11) | (crN \u003c\u003c 7) | (crM \u003c\u003c 3) | op2;"},{"line_number":2650,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ee703fc5_995b5b57","line":2647,"updated":"2019-03-31 01:41:53.000000000","message":"You could factor the argument parsing into a specific function since you have it done identically twice.","commit_id":"7b0edab551132b890cb393c8fecd116892954b15"},{"author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"change_message_id":"d4dd033e111ef384ce0767f25f205ee4c26a6fa3","unresolved":false,"context_lines":[{"line_number":2644,"context_line":"\tif (op2 \u003e 7) {"},{"line_number":2645,"context_line":"\t\t\tcommand_print(CMD_CTX, \"op2 should be \u003c\u003d 7\");"},{"line_number":2646,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2647,"context_line":"\t}"},{"line_number":2648,"context_line":""},{"line_number":2649,"context_line":"\tuint32_t systemreg \u003d (op0 \u003c\u003c 14) | (op1 \u003c\u003c 11) | (crN \u003c\u003c 7) | (crM \u003c\u003c 3) | op2;"},{"line_number":2650,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ee703fc5_dc6d4198","line":2647,"in_reply_to":"ee703fc5_995b5b57","updated":"2019-03-31 16:26:32.000000000","message":"Absolutely, I will fix.","commit_id":"7b0edab551132b890cb393c8fecd116892954b15"},{"author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"change_message_id":"bcbcab41886c483c94fe136d3ce5ecc4774f57b4","unresolved":false,"context_lines":[{"line_number":2662,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[4], op2);"},{"line_number":2663,"context_line":""},{"line_number":2664,"context_line":"\tif (op0 \u003e 3) {"},{"line_number":2665,"context_line":"\t\t\tcommand_print(CMD_CTX, \"op0 should be \u003c\u003d 3\");"},{"line_number":2666,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2667,"context_line":"\t}"},{"line_number":2668,"context_line":"\tif (op1 \u003e 7) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"ee703fc5_ad461553","line":2665,"range":{"start_line":2665,"start_character":0,"end_line":2665,"end_character":3},"updated":"2019-04-18 19:52:44.000000000","message":"too many tabs","commit_id":"6d418abaa2a3e6ca5d51ec94c0e57ae32e587b1f"},{"author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"change_message_id":"0480574b5250dbe59f098275b61aa7da06b7548d","unresolved":false,"context_lines":[{"line_number":2662,"context_line":"\tCOMMAND_PARSE_NUMBER(u8, CMD_ARGV[4], op2);"},{"line_number":2663,"context_line":""},{"line_number":2664,"context_line":"\tif (op0 \u003e 3) {"},{"line_number":2665,"context_line":"\t\t\tcommand_print(CMD_CTX, \"op0 should be \u003c\u003d 3\");"},{"line_number":2666,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":2667,"context_line":"\t}"},{"line_number":2668,"context_line":"\tif (op1 \u003e 7) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"ee703fc5_adbff5a6","line":2665,"range":{"start_line":2665,"start_character":0,"end_line":2665,"end_character":3},"in_reply_to":"ee703fc5_ad461553","updated":"2019-04-25 07:21:38.000000000","message":"will fix","commit_id":"6d418abaa2a3e6ca5d51ec94c0e57ae32e587b1f"},{"author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"change_message_id":"bcbcab41886c483c94fe136d3ce5ecc4774f57b4","unresolved":false,"context_lines":[{"line_number":2721,"context_line":"\tuint32_t encoding;"},{"line_number":2722,"context_line":""},{"line_number":2723,"context_line":"\tswitch (CMD_ARGC) {"},{"line_number":2724,"context_line":"\t\tcase 6:"},{"line_number":2725,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u64, CMD_ARGV[5], value);"},{"line_number":2726,"context_line":"\t\t\tretval \u003d get_aarch64_system_register_encoding_from_command_arguments("},{"line_number":2727,"context_line":"\t\t\t\t\tcmd,"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"ee703fc5_cd434942","line":2724,"range":{"start_line":2724,"start_character":1,"end_line":2724,"end_character":2},"updated":"2019-04-18 19:52:44.000000000","message":"please adopt the existing switch/case style.","commit_id":"6d418abaa2a3e6ca5d51ec94c0e57ae32e587b1f"},{"author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"change_message_id":"0480574b5250dbe59f098275b61aa7da06b7548d","unresolved":false,"context_lines":[{"line_number":2721,"context_line":"\tuint32_t encoding;"},{"line_number":2722,"context_line":""},{"line_number":2723,"context_line":"\tswitch (CMD_ARGC) {"},{"line_number":2724,"context_line":"\t\tcase 6:"},{"line_number":2725,"context_line":"\t\t\tCOMMAND_PARSE_NUMBER(u64, CMD_ARGV[5], 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binval[64];"},{"line_number":3250,"context_line":"\t\t\t\ttobin(binval, val, (msb-lsb+1));"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"82f44df1_ef736c05","line":3247,"in_reply_to":"316ceda3_398e71e1","updated":"2022-02-23 14:47:55.000000000","message":"You are right!\nAnd CNTPCT_EL0 is not the only one to require a mask of 64 bits, as\nfgrep \u0027, 63, 0},\u0027 src/target/aarch64_system_registers_defs.h | wc -l\nreturns 276!\n\nIn Linux kernel we have today (I simplified the macros a little)\n#define BIT(nr)            (1UL \u003c\u003c (nr))\n#define BIT_ULL(nr)        (1ULL \u003c\u003c (nr))\n\n#define GENMASK(h, l)      (((~0UL) - (1UL \u003c\u003c (l)) + 1) \u0026 \\\n                            (~0UL \u003e\u003e (BITS_PER_LONG - 1 - (h))))\n#define GENMASK_ULL(h, l)  (((~0ULL) - (1ULL \u003c\u003c (l)) + 1) \u0026 \\\n                           (~0ULL \u003e\u003e (BITS_PER_LONG_LONG - 1 - (h))))\n\nAs you can see, generating the mask in 64 bits is not done with\n(BIT_ULL(n) - 1)\nas in this code but with\n(~0ULL \u003e\u003e (BITS_PER_LONG_LONG - 1 - (n)))\n\nI suggest to replace here with\nuint64_t mask \u003d ~0ULL \u003e\u003e (63 - msb + lsb);\n\nMaybe I should add BIT_ULL(), GENMASK() and GENMASK_ULL() in src/helper/bits.h","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"b58a2e5a41611f34a64c12b7c44dbf1d0035a739","unresolved":true,"context_lines":[{"line_number":3244,"context_line":"\t\t\t\tuint8_t msb \u003d field.msb;"},{"line_number":3245,"context_line":"\t\t\t\tuint8_t lsb \u003d field.lsb;"},{"line_number":3246,"context_line":""},{"line_number":3247,"context_line":"\t\t\t\tuint64_t mask \u003d (1 \u003c\u003c (msb - lsb + 1)) - 1;"},{"line_number":3248,"context_line":"\t\t\t\tuint64_t val \u003d ((value \u003e\u003e lsb) \u0026 mask);"},{"line_number":3249,"context_line":"\t\t\t\tchar binval[64];"},{"line_number":3250,"context_line":"\t\t\t\ttobin(binval, val, (msb-lsb+1));"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"5a03f8af_9c0a4f24","line":3247,"in_reply_to":"4b529e38_26b1fb0d","updated":"2022-02-23 12:27:36.000000000","message":"Any case where msb - lsb + 1 is \u003e\u003d 32, on a 32-bit host, will be UB.\n\nJust changing the shifted 1 to 1ULL should be enough to fix it for all meaningful combinations of msb and lsb.","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"ea839108d8b812964608d7ec69f0f6684a6eb494","unresolved":true,"context_lines":[{"line_number":3244,"context_line":"\t\t\t\tuint8_t msb \u003d field.msb;"},{"line_number":3245,"context_line":"\t\t\t\tuint8_t lsb \u003d field.lsb;"},{"line_number":3246,"context_line":""},{"line_number":3247,"context_line":"\t\t\t\tuint64_t mask \u003d (1 \u003c\u003c (msb - lsb + 1)) - 1;"},{"line_number":3248,"context_line":"\t\t\t\tuint64_t val \u003d ((value \u003e\u003e lsb) \u0026 mask);"},{"line_number":3249,"context_line":"\t\t\t\tchar binval[64];"},{"line_number":3250,"context_line":"\t\t\t\ttobin(binval, val, (msb-lsb+1));"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"316ceda3_398e71e1","line":3247,"in_reply_to":"4b529e38_26b1fb0d","updated":"2022-02-23 12:55:15.000000000","message":"If I remember correctly I wanted to look at CNTFRQ_EL0. This register is not 0, but since the shift is done as an int, msb - lsb + 1 \u003d 32 \u003d sizeof(int) * 8 triggers undefined (according to the C standard) behavior and the resulting mask is 0. Simply changing \"1 \u003c\u003c\" to \"1ULL \u003c\u003c\" would fix it for all cases except msb - lsb + 1 \u003d 64 (as in CNTPCT_EL0).","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"ce3807e3c261ee43d7d8269be331775622f96170","unresolved":false,"context_lines":[{"line_number":3244,"context_line":"\t\t\t\tuint8_t msb \u003d field.msb;"},{"line_number":3245,"context_line":"\t\t\t\tuint8_t lsb \u003d field.lsb;"},{"line_number":3246,"context_line":""},{"line_number":3247,"context_line":"\t\t\t\tuint64_t mask \u003d (1 \u003c\u003c (msb - lsb + 1)) - 1;"},{"line_number":3248,"context_line":"\t\t\t\tuint64_t val \u003d ((value \u003e\u003e lsb) \u0026 mask);"},{"line_number":3249,"context_line":"\t\t\t\tchar binval[64];"},{"line_number":3250,"context_line":"\t\t\t\ttobin(binval, val, (msb-lsb+1));"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"f1932335_a91c2f69","line":3247,"in_reply_to":"82f44df1_ef736c05","updated":"2022-05-04 12:10:17.000000000","message":"has been fixed","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"88f3fc4c819ecac1b65e7d2ea1d6d624f7f3b16d","unresolved":true,"context_lines":[{"line_number":3244,"context_line":"\t\t\t\tuint8_t msb \u003d field.msb;"},{"line_number":3245,"context_line":"\t\t\t\tuint8_t lsb \u003d field.lsb;"},{"line_number":3246,"context_line":""},{"line_number":3247,"context_line":"\t\t\t\tuint64_t mask \u003d (1 \u003c\u003c (msb - lsb + 1)) - 1;"},{"line_number":3248,"context_line":"\t\t\t\tuint64_t val \u003d ((value \u003e\u003e lsb) \u0026 mask);"},{"line_number":3249,"context_line":"\t\t\t\tchar binval[64];"},{"line_number":3250,"context_line":"\t\t\t\ttobin(binval, val, (msb-lsb+1));"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"4b529e38_26b1fb0d","line":3247,"in_reply_to":"a9190f2b_662c21ef","updated":"2022-02-23 00:17:41.000000000","message":"Do you have a specific example to test against?","commit_id":"a10ac56d5b591a5001bf0e6330b22372511732ab"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[{"line_number":22,"context_line":"#include \"jtag/interface.h\""},{"line_number":23,"context_line":"#include \"smp.h\""},{"line_number":24,"context_line":"#include \u003chelper/time_support.h\u003e"},{"line_number":25,"context_line":"#include \"aarch64_system_registers.h\""},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"enum restart_mode {"},{"line_number":28,"context_line":"\tRESTART_LAZY,"}],"source_content_type":"text/x-csrc","patch_set":16,"id":"1e4b20c1_3e01c81a","line":25,"updated":"2023-01-04 08:00:25.000000000","message":"No longer needed. The header file should be omitted from the commit.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"change_message_id":"bac3e245bc81931f2dc997f8a1f2b7d6925c2b21","unresolved":false,"context_lines":[{"line_number":22,"context_line":"#include \"jtag/interface.h\""},{"line_number":23,"context_line":"#include \"smp.h\""},{"line_number":24,"context_line":"#include \u003chelper/time_support.h\u003e"},{"line_number":25,"context_line":"#include \"aarch64_system_registers.h\""},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"enum restart_mode {"},{"line_number":28,"context_line":"\tRESTART_LAZY,"}],"source_content_type":"text/x-csrc","patch_set":16,"id":"86a045b0_d3bdf0e3","line":25,"in_reply_to":"1e4b20c1_3e01c81a","updated":"2023-01-04 19:26:08.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"12042760e6cd394874f2b7aaa43794cc37bbb0d1","unresolved":true,"context_lines":[{"line_number":3082,"context_line":"\t}"},{"line_number":3083,"context_line":""},{"line_number":3084,"context_line":"\tswitch (CMD_ARGC) {"},{"line_number":3085,"context_line":"\tcase 6:"},{"line_number":3086,"context_line":"\tcase 5:"},{"line_number":3087,"context_line":"\t\tretval \u003d get_aarch64_system_register_encoding_from_command_arguments(cmd,"},{"line_number":3088,"context_line":"\t\t\t\t\u0026encoding);"}],"source_content_type":"text/x-csrc","patch_set":16,"id":"6b8cb418_1e804c4c","line":3085,"updated":"2023-01-04 08:00:25.000000000","message":"Without \"decode\" there is no case 6.","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"},{"author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"change_message_id":"c124b36b186e5f2573e880ac6790f7bd2ab9de32","unresolved":false,"context_lines":[{"line_number":3082,"context_line":"\t}"},{"line_number":3083,"context_line":""},{"line_number":3084,"context_line":"\tswitch (CMD_ARGC) {"},{"line_number":3085,"context_line":"\tcase 6:"},{"line_number":3086,"context_line":"\tcase 5:"},{"line_number":3087,"context_line":"\t\tretval \u003d get_aarch64_system_register_encoding_from_command_arguments(cmd,"},{"line_number":3088,"context_line":"\t\t\t\t\u0026encoding);"}],"source_content_type":"text/x-csrc","patch_set":16,"id":"3127b89f_8359cc24","line":3085,"in_reply_to":"6b8cb418_1e804c4c","updated":"2023-01-05 00:52:30.000000000","message":"Done","commit_id":"192cf7df1e36e4dc00480d36252ec4564b27198a"}],"src/target/aarch64_system_registers.h":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c9c75f6654e163bd735d817258b8a41d74ddfb7a","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/***************************************************************************"},{"line_number":2,"context_line":" *   Copyright (C) 2019 by Mete Balci\t\t\t\t\t\t\t\t\t   *"},{"line_number":3,"context_line":" *                                                                         *"},{"line_number":4,"context_line":" *   This program is free software; you can redistribute it and/or modify  *"},{"line_number":5,"context_line":" *   it under the terms of the GNU General Public License as published by  *"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_aaf4b7ba","line":2,"range":{"start_line":2,"start_character":37,"end_line":2,"end_character":49},"updated":"2019-08-21 13:06:01.000000000","message":"Trivial, but use spaces here.","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"84215c69d1bc5f4d2b2d241f83e15306daa336ac","unresolved":false,"context_lines":[{"line_number":26,"context_line":"\tuint8_t lsb;"},{"line_number":27,"context_line":"} aarch64_system_register_field_t;"},{"line_number":28,"context_line":""},{"line_number":29,"context_line":"typedef struct aarch64_system_register_t {"},{"line_number":30,"context_line":"\tconst char *short_name;"},{"line_number":31,"context_line":"\tconst char *long_name;"},{"line_number":32,"context_line":"\tconst char *op0;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_ead14f28","line":29,"updated":"2019-08-21 14:14:54.000000000","message":"Also, style guide says not to use typedefs, please remove them and call the types by their full name, struct aarch64_system_register etc. Note that _t at the end of identifiers is reserved in POSIX or smth, and rather pointless anyway, so remove that suffix as well.","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":26,"context_line":"\tuint8_t lsb;"},{"line_number":27,"context_line":"} aarch64_system_register_field_t;"},{"line_number":28,"context_line":""},{"line_number":29,"context_line":"typedef struct aarch64_system_register_t {"},{"line_number":30,"context_line":"\tconst char *short_name;"},{"line_number":31,"context_line":"\tconst char *long_name;"},{"line_number":32,"context_line":"\tconst char *op0;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"6ec1af18_6daa5584","line":29,"in_reply_to":"8e7fc396_ead14f28","updated":"2021-06-28 19:31:44.000000000","message":"Agree, no typedefs","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":31,"context_line":"\tconst char *long_name;"},{"line_number":32,"context_line":"\tconst char *op0;"},{"line_number":33,"context_line":"\tconst char *op1;"},{"line_number":34,"context_line":"\tconst char *crN;"},{"line_number":35,"context_line":"\tconst char *crM;"},{"line_number":36,"context_line":"\tconst char *op2;"},{"line_number":37,"context_line":"\tuint32_t encoding;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"6ec1af18_4da519b1","line":34,"updated":"2021-06-28 19:31:44.000000000","message":"fix mixed case","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c9c75f6654e163bd735d817258b8a41d74ddfb7a","unresolved":false,"context_lines":[{"line_number":43,"context_line":" * https://developer.arm.com/-/media/Files/ATG/Beta10/ARMv85A-SysReg-00bet10.tar.gz"},{"line_number":44,"context_line":" * */"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"static aarch64_system_register_t aarch64_system_registers[] \u003d {"},{"line_number":47,"context_line":"\t{"},{"line_number":48,"context_line":"\t\t\"OSDTRRX_EL1\","},{"line_number":49,"context_line":"\t\t\"OS Lock Data Transfer Register, Receive\","}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_6abe9fd3","line":46,"updated":"2019-08-21 13:06:01.000000000","message":"Shouldn\u0027t this be const?","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"c9c75f6654e163bd735d817258b8a41d74ddfb7a","unresolved":false,"context_lines":[{"line_number":51,"context_line":"\t\t0x8002,"},{"line_number":52,"context_line":"\t\t{"},{"line_number":53,"context_line":"\t\t\t{\"None\", 31, 0},"},{"line_number":54,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":55,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":56,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":57,"context_line":"\t\t\t{NULL, 0, 0},"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_caf1f3c9","line":54,"updated":"2019-08-21 13:06:01.000000000","message":"OK, this is autogenerated, but what what a waste of characters to list all these null elements explicitly...","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"a46336ade5843f3e89adbf30acf93ae385e592aa","unresolved":false,"context_lines":[{"line_number":51,"context_line":"\t\t0x8002,"},{"line_number":52,"context_line":"\t\t{"},{"line_number":53,"context_line":"\t\t\t{\"None\", 31, 0},"},{"line_number":54,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":55,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":56,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":57,"context_line":"\t\t\t{NULL, 0, 0},"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_aacb5774","line":54,"in_reply_to":"8e7fc396_2ab8a7e1","updated":"2019-08-21 14:39:17.000000000","message":"Ok, I don\u0027t get any warnings with an initializer of this form in either Clang/GCC/Clang++/G++:\n\n  static const aarch64_system_register_t \n  aarch64_system_registers[] \u003d {\n          {\n                  \"MDCCINT_EL1\",\n                  \"Monitor DCC Interrupt Enable Register\",\n                  \"10\", \"000\", \"0000\", \"0000\", \"000\",\n                  0x8010,\n                  {\n                          {\"RX\", 30, 30},\n                          {\"TX\", 29, 29}\n                  }\n          },\n          { NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0, { { NULL, 0, 0 } } }\n  };\n\nThe final element can be { 0 } in C but not in C++.\n\nAnyway, it\u0027s not really an issue that it\u0027s explicit since it\u0027s not intended for human consumption.","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"},{"author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"change_message_id":"b8bc1f6d611f3e1f3c5252ff3525803d6dcb43dc","unresolved":false,"context_lines":[{"line_number":51,"context_line":"\t\t0x8002,"},{"line_number":52,"context_line":"\t\t{"},{"line_number":53,"context_line":"\t\t\t{\"None\", 31, 0},"},{"line_number":54,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":55,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":56,"context_line":"\t\t\t{NULL, 0, 0},"},{"line_number":57,"context_line":"\t\t\t{NULL, 0, 0},"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_2ab8a7e1","line":54,"in_reply_to":"8e7fc396_caf1f3c9","updated":"2019-08-21 13:32:30.000000000","message":"actually I started with using only a single 0 for the null elements of these structures first. I dont remember the details at the moment and the correct term for it but it didnt work with the compiler, due to compiler version and/or c++ level.","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"}],"src/target/aarch64_system_registers_defs.h":[{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","unresolved":false,"context_lines":[{"line_number":11,"context_line":"\t{"},{"line_number":12,"context_line":"\t\t\"MDCCINT_EL1\","},{"line_number":13,"context_line":"\t\t\"Monitor DCC Interrupt Enable Register\","},{"line_number":14,"context_line":"\t\t\"10\", \"000\", \"0000\", \"0000\", \"000\","},{"line_number":15,"context_line":"\t\t0x8010,"},{"line_number":16,"context_line":"\t\t{"},{"line_number":17,"context_line":"\t\t\t{\"RX\", 30, 30},"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"4eceab4c_f2af00dd","line":14,"updated":"2021-07-27 20:30:26.000000000","message":"This encoding looks incorrect. MDCCINT_EL1 is op0\u003d2, op1\u003d0, CRn\u003d0, CRm\u003d2 and op2\u003d0.","commit_id":"da27c44dd1a0d7c07951543ff6e806a05c4177d8"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","unresolved":false,"context_lines":[{"line_number":21,"context_line":"\t{"},{"line_number":22,"context_line":"\t\t\"MDSCR_EL1\","},{"line_number":23,"context_line":"\t\t\"Monitor Debug System Control Register\","},{"line_number":24,"context_line":"\t\t\"10\", \"000\", \"0000\", \"0000\", \"010\","},{"line_number":25,"context_line":"\t\t0x8012,"},{"line_number":26,"context_line":"\t\t{"},{"line_number":27,"context_line":"\t\t\t{\"TFO\", 31, 31},"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"4eceab4c_92bc7c1c","line":24,"updated":"2021-07-27 20:30:26.000000000","message":"This encoding looks incorrect. MDSCR_EL1 is op0\u003d2, op1\u003d0, CRn\u003d0, CRm\u003d2 and op2\u003d2.","commit_id":"da27c44dd1a0d7c07951543ff6e806a05c4177d8"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","unresolved":false,"context_lines":[{"line_number":44,"context_line":"\t{"},{"line_number":45,"context_line":"\t\t\"OSDTRTX_EL1\","},{"line_number":46,"context_line":"\t\t\"OS Lock Data Transfer Register, Transmit\","},{"line_number":47,"context_line":"\t\t\"10\", \"000\", \"0000\", \"0000\", \"010\","},{"line_number":48,"context_line":"\t\t0x801a,"},{"line_number":49,"context_line":"\t\t{"},{"line_number":50,"context_line":"\t\t\t{\"None\", 31, 0},"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"4eceab4c_b2b9782b","line":47,"updated":"2021-07-27 20:30:26.000000000","message":"This encoding looks incorrect. OSDTRTX_EL1 is op0\u003d2, op1\u003d0, CRn\u003d0, CRm\u003d3 and op2\u003d2.","commit_id":"da27c44dd1a0d7c07951543ff6e806a05c4177d8"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","unresolved":false,"context_lines":[{"line_number":53,"context_line":"\t{"},{"line_number":54,"context_line":"\t\t\"OSECCR_EL1\","},{"line_number":55,"context_line":"\t\t\"OS Lock Exception Catch Control Register\","},{"line_number":56,"context_line":"\t\t\"10\", \"000\", \"0000\", \"0100\", \"010\","},{"line_number":57,"context_line":"\t\t0x8032,"},{"line_number":58,"context_line":"\t\t{"},{"line_number":59,"context_line":"\t\t\t{\"EDECCR\", 31, 0},"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"4eceab4c_5286146c","line":56,"updated":"2021-07-27 20:30:26.000000000","message":"This encoding looks incorrect. OSECCR_EL1 is op0\u003d2, op1\u003d0, CRn\u003d0, CRm\u003d6 and op2\u003d2.","commit_id":"da27c44dd1a0d7c07951543ff6e806a05c4177d8"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","unresolved":false,"context_lines":[{"line_number":6235,"context_line":"\t{"},{"line_number":6236,"context_line":"\t\t\"SCTLR_EL3\","},{"line_number":6237,"context_line":"\t\t\"System Control Register (EL3)\","},{"line_number":6238,"context_line":"\t\t\"10\", \"010\", \"0000\", \"0000\", \"000\","},{"line_number":6239,"context_line":"\t\t0xf080,"},{"line_number":6240,"context_line":"\t\t{"},{"line_number":6241,"context_line":"\t\t\t{\"DSSBS\", 44, 44},"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"4eceab4c_d2b20448","line":6238,"updated":"2021-07-27 20:30:26.000000000","message":"This encoding looks incorrect. SCTLR_EL3 is op0\u003d3, op1\u003d6, CRn\u003d1, CRm\u003d0 and op2\u003d0.","commit_id":"da27c44dd1a0d7c07951543ff6e806a05c4177d8"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c81c368256d61caf944f7fcb12f53760065a87c1","unresolved":false,"context_lines":[{"line_number":11341,"context_line":"\t\t{"},{"line_number":11342,"context_line":"\t\t\t{\"CompareValue\", 63, 0},"},{"line_number":11343,"context_line":"\t\t}"},{"line_number":11344,"context_line":"\t},"},{"line_number":11345,"context_line":"};"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"4eceab4c_d5e0ae27","line":11344,"updated":"2021-08-06 15:39:16.000000000","message":"NULL terminating entry needs to be inserted to indicate end-of-list for routines traversing this list. Issue can be seen when executing \"aarch64 mrs\" command.","commit_id":"814619a4891c15b7c83b3a548d0bdaeada56cf9e"}],"tools/generate_arm_sysreg_table.py":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","unresolved":false,"context_lines":[{"line_number":35,"context_line":"    if s \u003e\u003d 0:"},{"line_number":36,"context_line":"        e \u003d bitstr.find(\u0027]\u0027)"},{"line_number":37,"context_line":"        if e \u003e\u003d 0:"},{"line_number":38,"context_line":"            # omiting [n:"},{"line_number":39,"context_line":"            grp \u003d bitstr[s+3:e]"},{"line_number":40,"context_line":"            parts \u003d grp.split(\u0027:\u0027)"},{"line_number":41,"context_line":"            if len(parts) \u003d\u003d 1:"}],"source_content_type":"text/x-python","patch_set":7,"id":"6ec1af18_0daf1193","line":38,"updated":"2021-06-28 19:31:44.000000000","message":"typo","commit_id":"64de3d3ef4799f606437d78117778da1de332fd6"}]}