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The ARMv8 ARM typically references system registers through their \u003csystemreg\u003e name, do you think we could offer a table that translates between names and full encoding for convenience such that you could either do:\n\nmrs ACTLR_1\nor\nmrs 3 1 0 1 0\n\nfor instance?","accounts_in_message":[],"_revision_number":1},{"id":"d4dd033e111ef384ce0767f25f205ee4c26a6fa3","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-03-31 16:26:32.000000000","message":"Patch Set 1:\n\n(2 comments)\n\nThanks Florian. Actually I thought passing the systemreg name can be added later, but why not, I will add it now.","accounts_in_message":[],"_revision_number":1},{"id":"913c97a60377f34367efad18f521ec124ddaac44","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-02 12:30:15.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"67c29eda11f085d824eba1f6d1bc77b5d748404e","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-02 12:51:36.000000000","message":"Patch Set 2: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/10764/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/11430/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"1322f9baac074f35414d6be060894365b0b1f67e","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-02 12:57:24.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"2b910afb401f5dae8e13b409f8651c2f2e780a4e","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-02 13:54:48.000000000","message":"Patch Set 3: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/10767/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/11433/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"12eb5ad96c9722ad4465d5003cf5bf62d9155abb","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2019-04-03 01:53:23.000000000","message":"Patch Set 3: Code-Review+1\n\nWoah this looks great thanks a lot for the quick turnaround and supporting all of these registers via symbolic name.","accounts_in_message":[],"_revision_number":3},{"id":"077c3616aef24be20e555dd7a64068879b28e7a4","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-03 07:45:45.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"543091067c7ccf48952e776b5bd120abd703344d","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-03 07:49:32.000000000","message":"Patch Set 3:\n\n\u003e Woah this looks great thanks a lot for the quick turnaround and\n \u003e supporting all of these registers via symbolic name.\n\nThanks Florian. I have also added the tool that I used to generate the table in the header file in the new patchset. Also, I am not sure if I should remove mcr/mrc commands, the handler simply quits under ARM_STATE_AARCH64, not sure if this can be called in any other way.","accounts_in_message":[],"_revision_number":3},{"id":"b2d0af29daf74e7c03bdd18676a5a6f3f3742751","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-03 08:07:40.000000000","message":"Patch Set 4: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/10776/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/11442/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"90b63af396a5621465bc0b46c5d8ba26fff1c6ea","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-03 08:19:12.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"811eea46481c09c7fbd4001f723a2e29622ae444","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-03 08:35:51.000000000","message":"Uploaded patch set 6.","accounts_in_message":[],"_revision_number":6},{"id":"80a0a053fbdef0985ed8090e47168a6a73daeb15","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-03 08:35:51.000000000","message":"Patch Set 5: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/10778/ : ABORTED\n\nhttp://build.openocd.org/job/openocd-gerrit/11444/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"b21c57f694d3c21706556862247d4ec393d5d725","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-03 08:58:06.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11445/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10779/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"bcbcab41886c483c94fe136d3ce5ecc4774f57b4","author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"real_author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"date":"2019-04-18 19:52:44.000000000","message":"Patch Set 6:\n\n(2 comments)\n\nExcellent work, but please check coding style to be in line with rest of file. I think your tab spacing is off. Tab width is 4 in openocd and so is level indent.\n\nregarding switch/case style, it\u0027s not entirely consistent throughout the file yet but I want it to be kernel coding style with switch/case on same indent level.","accounts_in_message":[],"_revision_number":6},{"id":"0480574b5250dbe59f098275b61aa7da06b7548d","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-25 07:21:38.000000000","message":"Patch Set 6:\n\n(2 comments)\n\nThanks Matthias. I was trying to be careful but I missed these, I will fix.\n\n \u003e (2 comments)\n \u003e \n \u003e Excellent work, but please check coding style to be in line with\n \u003e rest of file. I think your tab spacing is off. Tab width is 4 in\n \u003e openocd and so is level indent.\n \u003e \n \u003e regarding switch/case style, it\u0027s not entirely consistent\n \u003e throughout the file yet but I want it to be kernel coding style\n \u003e with switch/case on same indent level.","accounts_in_message":[],"_revision_number":6},{"id":"b0964c6c1f579695ac5aaf0a5273e1c612f5f17d","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-04-25 07:23:40.000000000","message":"Uploaded patch set 7.","accounts_in_message":[],"_revision_number":7},{"id":"305dd290052fd7299872cf2ea82dc7fb02a89629","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-04-25 07:46:07.000000000","message":"Patch Set 7: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/11626/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/10951/ : SUCCESS","accounts_in_message":[],"_revision_number":7},{"id":"ac780882f97b91698d20a818552c0d507f72eb19","author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"real_author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"date":"2019-05-29 08:33:48.000000000","message":"Patch Set 7: Code-Review+2","accounts_in_message":[],"_revision_number":7},{"id":"c9c75f6654e163bd735d817258b8a41d74ddfb7a","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2019-08-21 13:06:01.000000000","message":"Patch Set 7:\n\n(3 comments)","accounts_in_message":[],"_revision_number":7},{"id":"b8bc1f6d611f3e1f3c5252ff3525803d6dcb43dc","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2019-08-21 13:32:30.000000000","message":"Patch Set 7:\n\n(1 comment)","accounts_in_message":[],"_revision_number":7},{"id":"84215c69d1bc5f4d2b2d241f83e15306daa336ac","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2019-08-21 14:14:54.000000000","message":"Patch Set 7:\n\n(1 comment)","accounts_in_message":[],"_revision_number":7},{"id":"a46336ade5843f3e89adbf30acf93ae385e592aa","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2019-08-21 14:39:17.000000000","message":"Patch Set 7:\n\n(1 comment)","accounts_in_message":[],"_revision_number":7},{"id":"43596d37868abb87ff82b079f532927c638f36e6","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-06-28 16:57:13.000000000","message":"Patch Set 7:\n\nMete, were you going to resubmit this or should someone pick up and address the latest comments?","accounts_in_message":[],"_revision_number":7},{"id":"cf87a26054a434ca5a75e0072abeb34e3d96f627","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-06-28 18:52:02.000000000","message":"Patch Set 7:\n\n\u003e Mete, were you going to resubmit this or should someone pick up and\n \u003e address the latest comments?\n\nSorry I missed the last comments. I dont have the environment right now, so if it possible, it would be great if someone else picks it up.","accounts_in_message":[],"_revision_number":7},{"id":"b2008d1764f1adc71ea0d0b87d9cad3e808329cc","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-06-28 19:31:44.000000000","message":"Patch Set 7: Code-Review-1\n\n(26 comments)\n\nIt doesn\u0027t merge (minor conflict in doc/openocd.texi) and doesn\u0027t compile because the prototype of command_print() has changed","accounts_in_message":[],"_revision_number":7},{"id":"ec59d71106e51180d585942f19696b3a687b6b50","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-07 21:20:40.000000000","message":"Patch Set 7:\n\nI have taken this pull request, addressed all of the comments, fixed the writing of registers, and tested it against a Cortex-A76 successfully. When my lovely IT department allows me to access gerrit, I should be able to push Mete\u0027s updated version.","accounts_in_message":[],"_revision_number":7},{"id":"2adbb3758593283d0f290d3ef61d3d1ee800f649","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-08 02:22:54.000000000","message":"Uploaded patch set 8.","accounts_in_message":[],"_revision_number":8},{"id":"3482098708f006246d76ae13aa9acab61921fd36","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-08 04:26:46.000000000","message":"Patch Set 8: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/14076/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit/14830/ : SUCCESS","accounts_in_message":[],"_revision_number":8},{"id":"6c96b3e40ef1e13486b69ba6c96c6bcc9b49d090","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-08 14:31:10.000000000","message":"Patch Set 8:\n\nI haven\u0027t been able to review and test this patch yet. The support of symbolic names is a welcomed addition. I would prefer the solution supported exception level elevation during the access and secure/non-secure access options that patch http://openocd.zylin.com/#/c/5572 provides, but I can add them later once 5003 is approved.","accounts_in_message":[],"_revision_number":8},{"id":"540a62bf5346e1d9b3ea6db0bfa5fe8a92b5e5db","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-08 16:44:08.000000000","message":"Patch Set 8:\n\n\u003e I haven\u0027t been able to review and test this patch yet. The support\n \u003e of symbolic names is a welcomed addition. I would prefer the\n \u003e solution supported exception level elevation during the access and\n \u003e secure/non-secure access options that patch http://openocd.zylin.com/#/c/5572\n \u003e provides, but I can add them later once 5003 is approved.\n\nSounds good, thanks Daniel. I do agree that we would benefit from exception level elevation, especially if you need to debug a monitor+hypervisor+kernel it may indeed be helpful to get a comprehensive view.\n\nLet me fix the jenkins build that failed.","accounts_in_message":[],"_revision_number":8},{"id":"3895961cbff3a3c8b1db3e41f5575932f9336d10","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-13 02:22:47.000000000","message":"Uploaded patch set 9.","accounts_in_message":[],"_revision_number":9},{"id":"d6a96405a9d1de7b1db0d9242eb8607a5d0316d6","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-13 02:53:20.000000000","message":"Patch Set 9: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14849/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14095/ : SUCCESS","accounts_in_message":[],"_revision_number":9},{"id":"2ec23b071ec0f8e8a55ed09c757c409e00a1a7bf","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-13 17:56:18.000000000","message":"Patch Set 9:\n\nI\u0027m testing now and so far this patch does work in my environment, but with a caveat. Patch http://openocd.zylin.com/#/c/5572 makes it relatively straightforward to implement a system register read-modify-write operation.\n\nFor example the following syntax can be used to mask bit 0 in reg SCTLR_EL1...\naarch64 msr 3 0 1 0 0 [expr {[aarch64 mrs 3 0 1 0 0] \u0026 0xFFFFFFFE}]\n\nWith this patch I need to get more creative to handle the formatting of the MRS command output. Maybe a flag can be added to only output the raw 64 bit result without the register bitfield breakout information? Or maybe suppress the bit breakout info and specify a flag to enable it?","accounts_in_message":[],"_revision_number":9},{"id":"6233d9aa2001ce230b9003db89ec1875922a8e6c","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-17 16:26:41.000000000","message":"Patch Set 9:\n\n\u003e I\u0027m testing now and so far this patch does work in my environment,\n \u003e but with a caveat. Patch http://openocd.zylin.com/#/c/5572 makes it\n \u003e relatively straightforward to implement a system register\n \u003e read-modify-write operation.\n \u003e \n \u003e For example the following syntax can be used to mask bit 0 in reg\n \u003e SCTLR_EL1...\n \u003e aarch64 msr 3 0 1 0 0 [expr {[aarch64 mrs 3 0 1 0 0] \u0026 0xFFFFFFFE}]\n \u003e \n \u003e With this patch I need to get more creative to handle the\n \u003e formatting of the MRS command output. Maybe a flag can be added to\n \u003e only output the raw 64 bit result without the register bitfield\n \u003e breakout information? Or maybe suppress the bit breakout info and\n \u003e specify a flag to enable it?\n\nYes that sounds reasonable to me, any suggestions on what the parameter name to indicate a per-bitfield breakout should be?","accounts_in_message":[],"_revision_number":9},{"id":"cf334b7b4e80af2977bf7bef4ab41a38057914f1","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-22 02:30:39.000000000","message":"Uploaded patch set 10.","accounts_in_message":[],"_revision_number":10},{"id":"01a5e570872e9edd5250d7004408bcbe4d028978","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-22 02:31:15.000000000","message":"Patch Set 10:\n\nI went with adding an optional parameter named \"decode\" in order to request the bit-by-bit decoding of the fields.","accounts_in_message":[],"_revision_number":10},{"id":"d175c4919cf07ff66364273d2e966271470e9833","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-22 03:04:10.000000000","message":"Patch Set 10: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14884/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14130/ : SUCCESS","accounts_in_message":[],"_revision_number":10},{"id":"009b2b54eaa65f0cdfb4c439fb37bec8b6b3e87c","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-27 02:26:58.000000000","message":"Patch Set 10:\n\n@Daniel, are you okay with the current version and adding a \"decode\" parameter to do the bit-by-bit pretty printing?","accounts_in_message":[],"_revision_number":10},{"id":"f2b9a3cfe21cf5b67a572022224fe71e9d196c33","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-27 16:57:07.000000000","message":"Patch Set 10:\n\n@Florian: the \u0027decode\u0027 parameter is fine and thanks for putting it in. It works with my testing.\n\nFor a system register read-modify-write operation I still need to extract the value from the string returned from the result of the read operation, but if no-one else objects I\u0027m fine with it.\n\nI have a question about the op0, op1, CRn, CRm, op2 encodings printed for the result of the \u0027mrs\u0027 command. Some examples...\n\n\u003e aarch64 mrs 3 6 1 0 0       \nSCTLR_EL3 [10_010_0000_0000_000]: 0x0000000030cd183f\n\n\u003e aarch64 mrs 3 4 1 0 0\nSCTLR_EL2 [10_000_0000_0000_000]: 0x000000003445d91d\n\n\u003e aarch64 mrs 3 0 1 0 0\nSCTLR_EL1 [10_000_0000_0000_000]: 0x0000000030d00800\n\nHow useful is this because the system register encodings don\u0027t match the values documented in the Arm ARM documentation? The encodings for SCTLR_EL2 and SCTLR_EL1 are also duplicates which is probably by design but I don\u0027t understand the reasoning behind it. Maybe someone can answer what the use case for this is.\n\nIs it adequate to display the results as the following, or is it preferred to also include the alternate system encodings?\n\n\u003e aarch64 mrs 3 6 1 0 0       \nSCTLR_EL3: 0x0000000030cd183f\n\n\u003e aarch64 mrs 3 4 1 0 0\nSCTLR_EL2: 0x000000003445d91d\n\n\u003e aarch64 mrs 3 0 1 0 0\nSCTLR_EL1: 0x0000000030d00800","accounts_in_message":[],"_revision_number":10},{"id":"21abb6e1c36f8ca3e8783ab31e2c743d3f322ad4","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-27 17:30:45.000000000","message":"Patch Set 10:\n\nSome thoughts on the system register encodings displayed...\n\nOutput during patch testing...\n\u003e aarch64 mrs sctlr_el3\nSCTLR_EL3 [10_010_0000_0000_000]: 0x0000000030cd183a\n\nIf using the system register encodings provided in the above output...\n\u003e aarch64 mrs 2 2 0 0 0\nOpcode 0xd5320000, DSCR.ERR\u003d1, DSCR.EL\u003d3\n\nDoes it make more sense to display it like this?\n\u003e aarch64 mrs sctlr_el3\nSCTLR_EL3 [11_110_0000_0000_000]: 0x0000000030cd183a\n\nIf using the system register encodings provided in the above output...\n\u003e aarch64 mrs 3 6 1 0 0\nSCTLR_EL3 [11_110_0000_0000_000]: 0x0000000030cd183a","accounts_in_message":[],"_revision_number":10},{"id":"35cf9293604b4c8a0c132e04581d300b2ccb0b2b","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-27 18:42:25.000000000","message":"Patch Set 10:\n\n\u003e Some thoughts on the system register encodings displayed...\n \u003e \n \u003e Output during patch testing...\n \u003e \u003e aarch64 mrs sctlr_el3\n \u003e SCTLR_EL3 [10_010_0000_0000_000]: 0x0000000030cd183a\n \u003e \n \u003e If using the system register encodings provided in the above\n \u003e output...\n \u003e \u003e aarch64 mrs 2 2 0 0 0\n \u003e Opcode 0xd5320000, DSCR.ERR\u003d1, DSCR.EL\u003d3\n \u003e \n \u003e Does it make more sense to display it like this?\n \u003e \u003e aarch64 mrs sctlr_el3\n \u003e SCTLR_EL3 [11_110_0000_0000_000]: 0x0000000030cd183a\n \u003e \n \u003e If using the system register encodings provided in the above\n \u003e output...\n \u003e \u003e aarch64 mrs 3 6 1 0 0\n \u003e SCTLR_EL3 [11_110_0000_0000_000]: 0x0000000030cd183a\n\nI don\u0027t think that encoding representation terribly useful either, going with a 64-bit hexadecimal representation sounds simpler and maybe more useful for opcode bit manipulation?","accounts_in_message":[],"_revision_number":10},{"id":"6d5503b0ccc05679caa269a4a544b1bfad1de7ed","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-27 20:30:26.000000000","message":"Patch Set 10:\n\n(5 comments)\n\nI\u0027m questioning the correctness of the system register encodings for the op0, op1, crn, crm and op2 strings contained in file aarch64_system_registers_defs.h. Most of them look incorrect to me, but maybe there is something going on I\u0027m not aware of.\n\nFor example, the SCTLR_EL3 encoding documented in the Arm ARM is op0\u003d3, op1\u003d6, CRn\u003d1, CRm\u003d0 and op2\u003d0. But file aarch64_system_registers_defs.h shows it as op0\u003d2, op1\u003d2, CRn\u003d0, CRm\u003d0 and op2\u003d0. With that said, the \"encoding\" variable in the structures look correct, it\u0027s the strings pointed to by op0, op1, crn, crm, op2 in the aarch64_system_register structure I\u0027m not sure of. I highlighted a few examples in the header file.","accounts_in_message":[],"_revision_number":10},{"id":"bd9d069edaa9abdaef769739052c603cb7f4988c","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-07-28 05:59:31.000000000","message":"Patch Set 10:\n\nI checked MDCCINT_EL1, for the issue mentioned, and the encoding (of CRm) in the header is incorrect. I dont know the reason for this, maybe there was/is a bug in py tool or there was a mistake in the XML dataset when I created that (2+ years ago). When I try the latest XML dataset, I think it is going to be generated correctly, but there is a problem because the XML dataset now contains elements like n[3:0] for registers like DBGBVR\u003cn\u003e_EL1, so the tool has to be modified too, and I dont know what n[3:0] means yet.","accounts_in_message":[],"_revision_number":10},{"id":"8dd4fece7a0653e3fd25155f643d0c9d1973d72c","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-28 14:27:18.000000000","message":"Patch Set 10:\n\n\u003eand I dont know what n[3:0] means yet\n\nn[3:0] refers to the number of registers. For example, DBGBVR0_EL1, DBGBVR1_EL1, DBGBVR2_EL1, ..., DBGBVR15_EL1.\n\nFor the DBGBVRx_EL1 example, those 16 registers would be encoded as...\nop0\u003d0b10, op1\u003d0b000, CRn\u003d0b0000, CRm\u003dn[3:0], op2\u003d0b100\n\nJust to throw some ideas out there... To simplify things it may be worthwhile to remove the op0, op1, CRn, CRm, op2 strings from the aarch64_system_register structure. The same information is encoded in the \"encoding\" variable in the same structure and that looks correct. Or the data in the \"encoding\" variable can be used to generate the op0, op1, CRn, CRm and op2 strings instead of relying on the data in the XML file.","accounts_in_message":[],"_revision_number":10},{"id":"be98c8a641261f1e2a4754f46ce889ea11e27ff2","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-07-28 17:24:37.000000000","message":"Patch Set 10:\n\nmultiple issues and a long comment:\n\n1) There was an error in generate script which was causing incorrect generation of the char* binary representations of encodings. That is why encoding value could be correct (see issue 3 below) but strings were showing incorrect values. I fixed this.\n\n2) It seems I already did something in the past to handle n[:] type encodings in the XML, but there are all combinations of these now (I guess these did not exist before otherwise I could not be able to generate the header, I am using the latest ARM register defs XML file at the moment), meaning n[:] can be alone or also together with a 0b either in front of it or after. I think I have fixed the script to handle all these.\n\n3) If I am not mistaken, in the current header, the encoding value is also not correct for \u003cn\u003e type registers when n \u003e 0. For example DBGBVR0_EL1 is 0x8004 -which I think correct- but DBGBVR1_EL1 is 0x8044 but -I think- it should be 0x800c. I think I also have fixed this in the generate script.\n\n4) You are actually right, it is unnecessary both encoding and the string representations are present in the header. I did not check, but I believe I did this to make maybe the display simpler? I can remove it from the generator if that is the way to go. Note: if I understand your sentence correct, it is a little incorrect to describe it this way. The generate script actually only uses one place (enc_index.xml. also see the last point below) for op/cr values, it generates all possible encodings (e.g. for \u003cn\u003e type registers), and then from the generated encodings it recreates the representations (which had an error, issue 1 above). So it actually shows the same information from the XML, but it is redundant that is definitely correct.\n\n5) I think for the moment (or maybe also for the future) this works well, but looking at the generate script now, I think it is better to read the encodings not from enc_index but from individual register xmls (access_instruction tag). Also, I had to make a stupid workaround because CRm can also be given as \u0027-\u0027 in enc_index, which I guess means dont care, so I replace it with 0s (but assuming it is in CRm, and it is a bit ambigious). In summary, I am not fully comfortable if I get the grammar of these XMLs right, to implement the generator script 100% correct.","accounts_in_message":[],"_revision_number":10},{"id":"2b9e30aaf6a88b4b06802014ca84e8f74194fb6c","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-07-28 17:45:48.000000000","message":"Uploaded patch set 11.","accounts_in_message":[],"_revision_number":11},{"id":"3f0346c98f5e27695cf3ac7550b58ede6f22ac7b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-28 18:19:10.000000000","message":"Patch Set 11: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14901/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14146/ : SUCCESS","accounts_in_message":[],"_revision_number":11},{"id":"31837b86a9ce9ccae8435fd7c3a604e21322f78e","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-08-06 03:03:08.000000000","message":"Patch Set 11:\n\n@Mete, thanks for the updates and the encodings look correct now. One thing I did notice during testing... when executing an \"aarch64 mrs\" command to list all registers, the listing looks correct, but garbage characters are included at the end of the listing.\n\nFor example:\n\u003e aarch64 mrs\nOSDTRRX_EL1: OS Lock Data Transfer Register, Receive\nMDCCINT_EL1: Monitor DCC Interrupt Enable Register\nMDSCR_EL1: Monitor Debug System Control Register\n...\n...\n...\nCNTPS_TVAL_EL1: Counter-timer Physical Secure Timer TimerValue register\nCNTPS_CTL_EL1: Counter-timer Physical Secure Timer Control register\nCNTPS_CVAL_EL1: Counter-timer Physical Secure Timer CompareValue register\n\u003cline of garbage characters\u003e\n\u003cline of garbage characters\u003e\n\u003cline of garbage characters\u003e\n\nI\u0027ll have more time in the morning and will look at this further to see what\u0027s going on. But overall this patch looks good and I\u0027m happy with it. I especially like the \"decode\" function.","accounts_in_message":[],"_revision_number":11},{"id":"c81c368256d61caf944f7fcb12f53760065a87c1","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-08-06 15:39:16.000000000","message":"Patch Set 11:\n\n(1 comment)\n\nFollow-up to the previous comment. NULL terminating entry missing from the aarch64_system_registers_defs.h list.","accounts_in_message":[],"_revision_number":11},{"id":"ff0ebf38978b2fc1bb71af73b1099c214bdc4648","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-08-06 19:24:55.000000000","message":"Uploaded patch set 12.","accounts_in_message":[],"_revision_number":12},{"id":"b5e25239d4b5a5733be77f5c7c987b03064cdd2d","author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"real_author":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"date":"2021-08-06 19:27:35.000000000","message":"Patch Set 12:\n\n\u003e (1 comment)\n \u003e \n \u003e Follow-up to the previous comment. NULL terminating entry missing\n \u003e from the aarch64_system_registers_defs.h list.\n\nI believe I fixed it with the last patch.","accounts_in_message":[],"_revision_number":12},{"id":"cfef2fee6171418d91b0c540710cca3c3cff2ea5","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-06 19:58:57.000000000","message":"Patch Set 12: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14964/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14199/ : SUCCESS","accounts_in_message":[],"_revision_number":12},{"id":"095b6d27d8a9ce4f6f498ddd19d9e82d01fe0910","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-08-06 22:56:32.000000000","message":"Patch Set 12: Code-Review+1\n\nLooks good to me. I tested the patch on an Ampere Altra Max server.","accounts_in_message":[],"_revision_number":12},{"id":"a9117d205a9d55f00dcaa924d8030a377aba6d88","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-10-20 21:54:48.000000000","message":"Patch Set 12: Code-Review+1","accounts_in_message":[],"_revision_number":12},{"id":"e4da87fd635480fb70f81bd81863b426338bd85d","author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"real_author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"date":"2021-12-10 02:06:47.000000000","message":"Patch Set 12: Code-Review-1\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"88f3fc4c819ecac1b65e7d2ea1d6d624f7f3b16d","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2022-02-23 00:17:41.000000000","message":"Patch Set 12:\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"8aa9af0f8912d8c11cedcc42ed8e634d10c4ab3f","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2022-02-23 11:09:44.000000000","message":"Patch Set 12: Code-Review+1\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"b58a2e5a41611f34a64c12b7c44dbf1d0035a739","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2022-02-23 12:27:36.000000000","message":"Patch Set 12:\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"ea839108d8b812964608d7ec69f0f6684a6eb494","author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"real_author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"date":"2022-02-23 12:55:15.000000000","message":"Patch Set 12:\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"f949cd6adf078795d8a42843212665d4e5325e02","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2022-02-23 14:47:55.000000000","message":"Patch Set 12: -Code-Review\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"cacf187767451eea82251be7e1cb4e726323cfc5","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2022-04-26 22:15:06.000000000","message":"Uploaded patch set 13.","accounts_in_message":[],"_revision_number":13},{"id":"368c26b0f7c3a4e62377b27e4d6a0940b64fc77c","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2022-04-26 23:03:28.000000000","message":"Patch Set 13: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/16069/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/15279/ : SUCCESS","accounts_in_message":[],"_revision_number":13},{"id":"d6ae879e6dec91dfcce0e0c3a34e5eac370f1134","author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"real_author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"date":"2022-04-26 23:29:03.000000000","message":"Patch Set 13: Code-Review+1\n\n(1 comment)","accounts_in_message":[],"_revision_number":13},{"id":"74053f699b640bf2d55615172c26f51286482920","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2022-04-29 08:00:36.000000000","message":"Patch Set 13:\n\n(1 comment)","accounts_in_message":[],"_revision_number":13},{"id":"40f0731b3eba60ce9eb4b5e8443677855329b33f","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2022-04-29 14:54:28.000000000","message":"Patch Set 13:\n\n(1 comment)","accounts_in_message":[],"_revision_number":13},{"id":"ce3807e3c261ee43d7d8269be331775622f96170","author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"real_author":{"_account_id":1000671,"name":"Daniel Glöckner","email":"daniel-gl@gmx.net","username":"denial"},"date":"2022-05-04 12:10:17.000000000","message":"Patch Set 13:\n\n(1 comment)","accounts_in_message":[],"_revision_number":13},{"id":"6d6abe8b414b6049eb060000512ac1aba2054b08","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2022-05-06 22:05:33.000000000","message":"Patch Set 13:\n\n(1 comment)","accounts_in_message":[],"_revision_number":13},{"id":"38043d26cd38edd6e540c17a59a48f7c294c4625","author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"real_author":{"_account_id":1002003,"name":"jlintonarm","display_name":"Jeremy Linton (Arm)","username":"jlintonarm"},"date":"2022-06-27 20:21:31.000000000","message":"Patch Set 13:\n\n(2 comments)","accounts_in_message":[],"_revision_number":13},{"id":"5fae4f4db46a9fe786aa82a11c8f633b63a8530b","author":{"_account_id":1001918,"name":"Dietmar May","email":"dietmar.may@outlook.com","username":"dmay"},"real_author":{"_account_id":1001918,"name":"Dietmar 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The read command\nalso decodes the bit fields.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional\n* removed name based decoding until license of XML source is clarified]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n[pcc:\n* Rebased\n* Fixed definition of ARMV8_MRS/ARMV8_MSR_GP to support op0[1]\u003d\u003d0b0]\nSigned-off-by: Peter Collingbourne \u003cpcc@google.com\u003e\n"}},"192cf7df1e36e4dc00480d36252ec4564b27198a":{"kind":"REWORK","_number":16,"created":"2022-11-30 22:05:48.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/16","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/16","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/16 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/16 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/16 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/16 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/16","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/16 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6ea1ccf3e6dd84c600c4ae9fb70347872634ded4","subject":"flash/nor/stm32lx: Add revision \u00271, X\u0027 for Cat.2 devices"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2022-11-30 21:09:07.000000000","tz":-480},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional\n* removed name based decoding until license of XML source is clarified]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"04e892d48447f7fb7b521dfb74941c441962b1f1":{"kind":"REWORK","_number":17,"created":"2023-01-04 19:25:51.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/17","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/17","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/17 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/17 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/17 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/17 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/17","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/17 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"dfe57baa16cdbc0dc2ae7182b5b3831028637223","subject":"Restore +dev suffix"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2023-01-04 19:24:17.000000000","tz":-480},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional\n* removed name based decoding until license of XML source is clarified]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"d0869d45f2cbe46961b87d26dbefe8b2f9a5313c":{"kind":"REWORK","_number":2,"created":"2019-04-02 12:30:15.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/2 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4db5299b5bd2c3e853f7383c076f9726dc588680","subject":"target/cortex_m: remove fp_code_available counting"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-02 12:28:48.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2).\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"845accb3550b31e4972334af89faa683e742dd8d":{"kind":"REWORK","_number":3,"created":"2019-04-02 12:57:24.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/3 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4db5299b5bd2c3e853f7383c076f9726dc588680","subject":"target/cortex_m: remove fp_code_available counting"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-02 12:57:19.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2).\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"7b0edab551132b890cb393c8fecd116892954b15":{"kind":"REWORK","_number":1,"created":"2019-03-30 11:08:31.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/1 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"a7479fa89def9d8b1854d629dfdaa0ba17132617","subject":"Constify struct flash_driver instances"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:49:54.000000000","tz":60},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"6d418abaa2a3e6ca5d51ec94c0e57ae32e587b1f":{"kind":"REWORK","_number":6,"created":"2019-04-03 08:35:51.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/6 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4db5299b5bd2c3e853f7383c076f9726dc588680","subject":"target/cortex_m: remove fp_code_available counting"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-03 08:35:47.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"64de3d3ef4799f606437d78117778da1de332fd6":{"kind":"REWORK","_number":7,"created":"2019-04-25 07:23:40.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/7 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"bbdb820c82d65cd11abdc329eaa91d410690436e","subject":"flash/fespi: Use COMMAND_PARSE_ADDRESS"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-25 07:22:56.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"bfacf3619ce1ca3cc8e8013c323341751400f22f":{"kind":"REWORK","_number":4,"created":"2019-04-03 07:45:45.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/4 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4db5299b5bd2c3e853f7383c076f9726dc588680","subject":"target/cortex_m: remove fp_code_available counting"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-03 07:42:06.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"6d7028dc20f953c62f5b3e5f1573f076a9694e96":{"kind":"REWORK","_number":5,"created":"2019-04-03 08:19:12.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/5 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4db5299b5bd2c3e853f7383c076f9726dc588680","subject":"target/cortex_m: remove fp_code_available counting"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-04-03 08:18:40.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n"}},"da27c44dd1a0d7c07951543ff6e806a05c4177d8":{"kind":"REWORK","_number":10,"created":"2021-07-22 02:30:39.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/10","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/10","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/10 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/10 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/10 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/10 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/10","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/10 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"20b29b7767097f999fe2eb4f7fb6c2917e9f66a6","subject":"openocd: manually fix Yoda conditions"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2021-07-22 02:28:59.000000000","tz":-420},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"814619a4891c15b7c83b3a548d0bdaeada56cf9e":{"kind":"REWORK","_number":11,"created":"2021-07-28 17:45:48.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/11","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/11","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/11 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/11 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/11 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/11 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/11","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/11 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"20b29b7767097f999fe2eb4f7fb6c2917e9f66a6","subject":"openocd: manually fix Yoda conditions"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2021-07-28 17:45:11.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"c22d6189e2b86f67ccb8f07178b6e9bb9f475344":{"kind":"REWORK","_number":8,"created":"2021-07-08 02:22:54.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/8 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"28c91b8f80937e6ec6521496f363038d9a5f9a04","subject":"tcl: Update Flyswatter product links"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2021-07-08 02:22:31.000000000","tz":-420},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  indepenently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"9b1d12e602818988d05726ce730147485e267250":{"kind":"REWORK","_number":9,"created":"2021-07-13 02:22:47.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/9","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/9","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/9 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/9 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/9 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/9 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/9","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/9 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"65c9653cc768f77a5e8cf2af73e0f40d614bdec2","subject":"target: add support for 64bit data in mem2array and array2mem"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2021-07-13 02:22:31.000000000","tz":-420},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  indepenently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"ec845d1815965c0896b630d2eb6e627048ad6aac":{"kind":"REWORK","_number":14,"created":"2022-11-30 20:57:54.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/14","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/14","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/14 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/14 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/14 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/14 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/14","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/14 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6ea1ccf3e6dd84c600c4ae9fb70347872634ded4","subject":"flash/nor/stm32lx: Add revision \u00271, X\u0027 for Cat.2 devices"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2022-11-30 20:52:43.000000000","tz":-480},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional\n* removed name based decoding until license of XML source is clarified]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"2c124e223059888c1728d1c07966da12c7b3358e":{"kind":"REWORK","_number":15,"created":"2022-11-30 21:06:06.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/15","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/15","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/15 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/15 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/15 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/15 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/15","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/15 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6ea1ccf3e6dd84c600c4ae9fb70347872634ded4","subject":"flash/nor/stm32lx: Add revision \u00271, X\u0027 for Cat.2 devices"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2022-11-30 21:04:59.000000000","tz":-480},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional\n* removed name based decoding until license of XML source is clarified]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"a10ac56d5b591a5001bf0e6330b22372511732ab":{"kind":"REWORK","_number":12,"created":"2021-08-06 19:24:55.000000000","uploader":{"_account_id":1001654,"name":"Mete Balci","email":"metebalci@gmail.com","username":"mete"},"ref":"refs/changes/03/5003/12","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/12","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/12 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/12 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/12 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/12 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/12","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/12 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"20b29b7767097f999fe2eb4f7fb6c2917e9f66a6","subject":"openocd: manually fix Yoda conditions"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2021-08-06 19:24:41.000000000","tz":120},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}},"50f307525b11e92c2c710ffbc9df851933475c32":{"kind":"REWORK","_number":13,"created":"2022-04-26 22:15:06.000000000","uploader":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"ref":"refs/changes/03/5003/13","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/03/5003/13","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/13 \u0026\u0026 git checkout -b change-5003 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/13 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/13 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/13 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/03/5003/13","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/03/5003/13 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"9de084e0067a86b8040f8ea2c3f46dff0b9e6a70","subject":"flash/nor/stm32f1x: add can_load_options flag for GD32F1x0, F3x0 and E23x"}],"author":{"name":"Mete Balci","email":"metebalci@gmail.com","date":"2019-03-30 10:36:24.000000000","tz":60},"committer":{"name":"Florian Fainelli","email":"f.fainelli@gmail.com","date":"2022-04-26 22:14:54.000000000","tz":-420},"subject":"target/aarch64: MRS/MSR support for system register access","message":"target/aarch64: MRS/MSR support for system register access\n\nAArch32 MCR/MRC is not supported in AArch64. Instead, MRS/MSR\nshould be used.\n\nAArch64 System Registers can be accessed by mrs/msr commands,\nboth by name and (op0, op1, CRn, CRm, op2). The read command\nalso decodes the bit fields.\n\nThe information related to System Registers are stored in\naarch64_system_registers_defs.h and are generated from the ARM\nSystem Registers XML dataset using the\ntools/generate_arm_sysreg_table.py tool.\n\nChange-Id: I55f114adf95e576475fb81867315d9564c5e353d\nSigned-off-by: Mete Balci \u003cmetebalci@gmail.com\u003e\n[florian:\n* Addressed comments\n* split headers to ease the updating of aarch64_system_registers_defs.h\n  independently from the code\n* constify declarations where appropriate\n* removed empty declarations where not needed\n* fixed register writes\n* fixed missing check on target being halted\n* made bit-by-bit decoding optional]\nSigned-off-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"NOT_READY","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"NEED"}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"UNSATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"]}}]}