)]}'
{"tcl/board/st_nucleo_h747zi.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"40693c4b3919bb62e00e075b1a366a767ce99cc4","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# This is an ST NUCLEO-H747ZI-Q board with single STM32H747ZI-Q chip."},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"# Hint: ST-Link firwmware onboard supports stlink-dap interface"},{"line_number":4,"context_line":"# once merged, it is recommended to use it in order to debug the Cortex-M4 using ST-Link"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"# source [find interface/stlink-dap.cfg]"},{"line_number":7,"context_line":"# transport select dapdirect_swd"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"source [find interface/stlink.cfg]"},{"line_number":10,"context_line":"transport select hla_swd"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_add615f5","line":7,"range":{"start_line":3,"start_character":0,"end_line":7,"end_character":32},"updated":"2019-04-25 18:21:16.000000000","message":"I see no point in merging this file before dapdirect support and updating it afterwards","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"5fe7e8e6ed15094df0827484f6a0240381254bd5","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# This is an ST NUCLEO-H747ZI-Q board with single STM32H747ZI-Q chip."},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"# Hint: ST-Link firwmware onboard supports stlink-dap interface"},{"line_number":4,"context_line":"# once merged, it is recommended to use it in order to debug the Cortex-M4 using ST-Link"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"# source [find interface/stlink-dap.cfg]"},{"line_number":7,"context_line":"# transport select dapdirect_swd"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"source [find interface/stlink.cfg]"},{"line_number":10,"context_line":"transport select hla_swd"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_6db8fd74","line":7,"range":{"start_line":3,"start_character":0,"end_line":7,"end_character":32},"in_reply_to":"ee703fc5_add615f5","updated":"2019-04-29 08:23:53.000000000","message":"OK, I will remove it","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"}],"tcl/target/stm32h7x.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"ebdf85b8d6ce67dd334a4e22f69ab6e37802a81c","unresolved":false,"context_lines":[{"line_number":42,"context_line":""},{"line_number":43,"context_line":"if {![using_hla]} {"},{"line_number":44,"context_line":"\ttarget create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0"},{"line_number":45,"context_line":"\ttarget create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":46,"context_line":"\ttarget create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":47,"context_line":"} else {"},{"line_number":48,"context_line":"\t# multi AP is not supported using hla"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_edeacdd6","line":45,"updated":"2019-04-23 21:02:26.000000000","message":"Isn’t it confusing (to the user) for this target to show up even on parts where there isn’t a second processor? I’m not sure whether it might make more sense for these parts to have a separate config file or perhaps a variant selector passed in via a variable, rather than just always creating both CPUs and then one of them not working on some parts.","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":42,"context_line":""},{"line_number":43,"context_line":"if {![using_hla]} {"},{"line_number":44,"context_line":"\ttarget create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0"},{"line_number":45,"context_line":"\ttarget create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":46,"context_line":"\ttarget create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":47,"context_line":"} else {"},{"line_number":48,"context_line":"\t# multi AP is not supported using hla"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_08404fa7","line":45,"in_reply_to":"ee703fc5_edeacdd6","updated":"2019-05-08 14:36:13.000000000","message":"Done","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"6c1ff407305ae25427837dbaca860a79b436d391","unresolved":false,"context_lines":[{"line_number":42,"context_line":""},{"line_number":43,"context_line":"if {![using_hla]} {"},{"line_number":44,"context_line":"\ttarget create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0"},{"line_number":45,"context_line":"\ttarget create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":46,"context_line":"\ttarget create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":47,"context_line":"} else {"},{"line_number":48,"context_line":"\t# multi AP is not supported using hla"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_0dcf0184","line":45,"in_reply_to":"ee703fc5_edeacdd6","updated":"2019-04-23 21:52:10.000000000","message":"I though that keeping it in non examined state will be less confusing.\nso in single core devices the bit 16 of @0x58000500, is zero, so the cpu1 will remain non-examined.","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"ebdf85b8d6ce67dd334a4e22f69ab6e37802a81c","unresolved":false,"context_lines":[{"line_number":109,"context_line":"\t# Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":110,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"},{"line_number":111,"context_line":"\tmmw 0x580244F4 0x00000002 0"},{"line_number":112,"context_line":"\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"},{"line_number":113,"context_line":"\tif {$chip_options(0) \u0026 0x10000} {"},{"line_number":114,"context_line":"\t\tif {![using_hla]} {"},{"line_number":115,"context_line":"\t\t\t$_CHIPNAME.cpu1 arp_examine"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_4de65915","line":112,"updated":"2019-04-23 21:02:26.000000000","message":"In the STM32H743 reference manual, offset 0x100 into the SYSCFG block is documented as being reserved, with no designated reset value. Are you certain it’s OK to read that register and, furthermore, that the value in bit 16 will remain zero even on all variants and revisions?","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":109,"context_line":"\t# Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":110,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"},{"line_number":111,"context_line":"\tmmw 0x580244F4 0x00000002 0"},{"line_number":112,"context_line":"\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"},{"line_number":113,"context_line":"\tif {$chip_options(0) \u0026 0x10000} {"},{"line_number":114,"context_line":"\t\tif {![using_hla]} {"},{"line_number":115,"context_line":"\t\t\t$_CHIPNAME.cpu1 arp_examine"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_a84cc3e5","line":112,"in_reply_to":"ee703fc5_4de65915","updated":"2019-05-08 14:36:13.000000000","message":"Done","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"6c1ff407305ae25427837dbaca860a79b436d391","unresolved":false,"context_lines":[{"line_number":109,"context_line":"\t# Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":110,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"},{"line_number":111,"context_line":"\tmmw 0x580244F4 0x00000002 0"},{"line_number":112,"context_line":"\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"},{"line_number":113,"context_line":"\tif {$chip_options(0) \u0026 0x10000} {"},{"line_number":114,"context_line":"\t\tif {![using_hla]} {"},{"line_number":115,"context_line":"\t\t\t$_CHIPNAME.cpu1 arp_examine"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ee703fc5_edd16d28","line":112,"in_reply_to":"ee703fc5_4de65915","updated":"2019-04-23 21:52:10.000000000","message":"yes I\u0027m quite sure. this information is correct for all h7 devices and revisions.\nand this will be documented in the next reference manual revision for h7x7 and h7x5 variants.","commit_id":"3d43aabf69757bce61b0f6faaaf06c9f70e883f5"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"40693c4b3919bb62e00e075b1a366a767ce99cc4","unresolved":false,"context_lines":[{"line_number":46,"context_line":" swj_newdap $_CHIPNAME bs -irlen 5"},{"line_number":47,"context_line":"}"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if {![using_hla]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_6d00fd6d","line":49,"range":{"start_line":49,"start_character":14,"end_line":49,"end_character":29},"updated":"2019-04-25 18:21:16.000000000","message":"I would not drop _TARGETNAME, as cpu0 seems to be the main one and _TARGETNAME is used for event handling and flash programming.","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"5fe7e8e6ed15094df0827484f6a0240381254bd5","unresolved":false,"context_lines":[{"line_number":46,"context_line":" swj_newdap $_CHIPNAME bs -irlen 5"},{"line_number":47,"context_line":"}"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if {![using_hla]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_ed840db8","line":49,"range":{"start_line":49,"start_character":14,"end_line":49,"end_character":29},"in_reply_to":"ee703fc5_6d00fd6d","updated":"2019-04-29 08:23:53.000000000","message":"then, you suggest to :\nset _TARGETNAME $_CHIPNAME.cpu0\nand keep the _TARGETNAME usage as it is, instead of using $_CHIPNAME.cpu0 explicitly","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"40693c4b3919bb62e00e075b1a366a767ce99cc4","unresolved":false,"context_lines":[{"line_number":50,"context_line":""},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if {![using_hla]} {"},{"line_number":53,"context_line":"  target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":54,"context_line":"  if {$_DUAL_CORE} {"},{"line_number":55,"context_line":"    target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":56,"context_line":"  }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_cdd34904","line":53,"updated":"2019-04-25 18:21:16.000000000","message":"A comment please what is the mem_ap used for","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":50,"context_line":""},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if {![using_hla]} {"},{"line_number":53,"context_line":"  target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":54,"context_line":"  if {$_DUAL_CORE} {"},{"line_number":55,"context_line":"    target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":56,"context_line":"  }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_c849f7d4","line":53,"in_reply_to":"ee703fc5_cdd34904","updated":"2019-05-08 14:36:13.000000000","message":"Done","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"5fe7e8e6ed15094df0827484f6a0240381254bd5","unresolved":false,"context_lines":[{"line_number":50,"context_line":""},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"if {![using_hla]} {"},{"line_number":53,"context_line":"  target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2"},{"line_number":54,"context_line":"  if {$_DUAL_CORE} {"},{"line_number":55,"context_line":"    target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine"},{"line_number":56,"context_line":"  }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_0d82a1a9","line":53,"in_reply_to":"ee703fc5_cdd34904","updated":"2019-04-29 08:23:53.000000000","message":"this mem_ap, allows the access to peripherals, even while the srst is asserted.\nbut since hla as it is does not support access the multiple Access Port. I haven\u0027t used it in the initialization script.\n\nPS : this is also discussed in #4742\n\nThis could be removed if you suggest so !","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"7bc5f7c43b2a8d5b7a5728413d4ec66dad6c493a","unresolved":false,"context_lines":[{"line_number":115,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":116,"context_line":""},{"line_number":117,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":118,"context_line":"\t\t# Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":119,"context_line":"\t\t# RCC_APB4ENR |\u003d SYSCFGEN"},{"line_number":120,"context_line":"\t\tmmw 0x580244F4 0x00000002 0"},{"line_number":121,"context_line":"\t\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_4dff3963","line":118,"updated":"2019-04-25 17:43:33.000000000","message":"If the user already told you they have a dual-core device, why bother autodetect it? I would think either don’t autodetect at all, or check the bit and throw an error if the user was wrong.\n\nAlso, given that the user is now specifying whether the second core exists or not, do you actually need to defer examination of the second core? Is it powered off initially? I don’t have one of these parts to investigate. If it’s available right away, wouldn’t it be simpler to do eager examination rather than deferred examination?","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"5fe7e8e6ed15094df0827484f6a0240381254bd5","unresolved":false,"context_lines":[{"line_number":115,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":116,"context_line":""},{"line_number":117,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":118,"context_line":"\t\t# Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":119,"context_line":"\t\t# RCC_APB4ENR |\u003d SYSCFGEN"},{"line_number":120,"context_line":"\t\tmmw 0x580244F4 0x00000002 0"},{"line_number":121,"context_line":"\t\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_ad8e15d4","line":118,"in_reply_to":"ee703fc5_4dff3963","updated":"2019-04-29 08:23:53.000000000","message":"nice idea, we could use that to throw an error.\nbut the differed examination is mandatory, as the use can disable the cortex-m4 by option bytes or by un-clocking the core itself or disabling the power domain.\nI will check with design team, and add the appropriate examine conditions.","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"40693c4b3919bb62e00e075b1a366a767ce99cc4","unresolved":false,"context_lines":[{"line_number":120,"context_line":"\t\tmmw 0x580244F4 0x00000002 0"},{"line_number":121,"context_line":"\t\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"},{"line_number":122,"context_line":"\t\tif {[expr {$chip_options(0) \u0026 0x10000}] \u0026\u0026 ![using_hla]} {"},{"line_number":123,"context_line":"\t\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":124,"context_line":"\t\t}"},{"line_number":125,"context_line":"\t}"},{"line_number":126,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_0df14192","line":123,"range":{"start_line":123,"start_character":3,"end_line":123,"end_character":30},"updated":"2019-04-25 18:21:16.000000000","message":"STM have not yet released MCU doc for the public, so I\u0027m just speculating:\nIf cpu1 is off after reset and can be switched on/off by firmware running on cpu0 then -defer-examine is correct but arp_examine will generate unwanted errors if cpu1 is off.\n\nMoving the common part (common for both single and dual cores) of the event handler to one proc and dual core stuff to the second proc might help the user to configure the event handler as he wants.","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"5fe7e8e6ed15094df0827484f6a0240381254bd5","unresolved":false,"context_lines":[{"line_number":120,"context_line":"\t\tmmw 0x580244F4 0x00000002 0"},{"line_number":121,"context_line":"\t\t$_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1"},{"line_number":122,"context_line":"\t\tif {[expr {$chip_options(0) \u0026 0x10000}] \u0026\u0026 ![using_hla]} {"},{"line_number":123,"context_line":"\t\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":124,"context_line":"\t\t}"},{"line_number":125,"context_line":"\t}"},{"line_number":126,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ee703fc5_cd8b49c3","line":123,"range":{"start_line":123,"start_character":3,"end_line":123,"end_character":30},"in_reply_to":"ee703fc5_0df14192","updated":"2019-04-29 08:23:53.000000000","message":"the doc will be released this week.\nand your speculation is correct !\nI will isolate the Cortex-M4 part in the next patch set","commit_id":"f4bf3550744a92738672be2360d9ed6564cc03f2"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"1588f307d95d010888e088ff10a09485dbe97d82","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_488ba720","line":128,"updated":"2019-05-07 00:31:28.000000000","message":"This variable might have changed by the time you get here.","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"cf73696690d3ef78c51d500787e1b9e57365af06","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_48e887af","line":128,"in_reply_to":"","updated":"2019-05-07 21:26:50.000000000","message":"Good point, it could be solved by using a dotted.name variable for each chipname.\nWhat do you think?","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_6816abae","line":128,"in_reply_to":"ee703fc5_08ca8f4a","updated":"2019-05-08 14:36:13.000000000","message":"Could you please check the proposal in PS6","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"0194d64dab0c3abbe5035efaba41adf866df2c53","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_a8a84375","line":128,"in_reply_to":"ee703fc5_488ba720","updated":"2019-05-07 20:52:48.000000000","message":"I didn\u0027t get this remark.\n$_DUAL_CORE once set in the beginning of the script, none seems to change it.\nCould please explain ?","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"a6a4a922d479b952386a5cbe9a6d2ee52f52dca7","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_08ca8f4a","line":128,"in_reply_to":"ee703fc5_48e887af","updated":"2019-05-07 21:29:13.000000000","message":"Sure, that sounds fine, if it’s possible. I’m not much of a TCL expert; can you dynamically compute the name of a variable and then get its value? If you can then that would do the job.","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"208f19a892628f28b8c08a35ea8be861c20a8641","unresolved":false,"context_lines":[{"line_number":125,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1"},{"line_number":126,"context_line":"\tmmw 0x5C001054 0x00040000 0"},{"line_number":127,"context_line":""},{"line_number":128,"context_line":"\tif {$_DUAL_CORE} {"},{"line_number":129,"context_line":"\t\tcortex_m4_init"},{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_08c36f3e","line":128,"in_reply_to":"ee703fc5_a8a84375","updated":"2019-05-07 21:01:43.000000000","message":"I meant it could be changed for another chip. If I have a dual-core H7 and a single-core H7 in my JTAG chain, then _DUAL_CORE will be 0 globally after both files have been sourced, even when running the dual-core H7’s examine-end handler.","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"1588f307d95d010888e088ff10a09485dbe97d82","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_8891bf54","line":133,"updated":"2019-05-07 00:31:28.000000000","message":"Isn’t this an awfully generic name for a processor-specific function? It will get into the global namespace.","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"208f19a892628f28b8c08a35ea8be861c20a8641","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_a8bfe3a6","line":133,"in_reply_to":"ee703fc5_089ccf5e","updated":"2019-05-07 21:01:43.000000000","message":"I meant how about “stm32h7x_is_cpu1_alive” or something like that?","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"0194d64dab0c3abbe5035efaba41adf866df2c53","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_089ccf5e","line":133,"in_reply_to":"ee703fc5_8891bf54","updated":"2019-05-07 20:52:48.000000000","message":"changed with \u0027is_cpu1_alive\u0027 in PS5, but I\u0027m open to suggestions","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_881bffd3","line":133,"in_reply_to":"ee703fc5_88de9f13","updated":"2019-05-08 14:36:13.000000000","message":"Done","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"cf73696690d3ef78c51d500787e1b9e57365af06","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\t}"},{"line_number":131,"context_line":"}"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_88de9f13","line":133,"in_reply_to":"ee703fc5_a8bfe3a6","updated":"2019-05-07 21:26:50.000000000","message":"Seems good to me","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"1588f307d95d010888e088ff10a09485dbe97d82","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"\t# Check that Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":138,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_28867319","line":135,"updated":"2019-05-07 00:31:28.000000000","message":"These may have changed by the time this function runs if another target config file also uses them (which plenty do), or if there is a second H7 on the JTAG chain. I think there are some cgets that allow you to get various properties about the current target, which hopefully would be sufficient instead?","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"0194d64dab0c3abbe5035efaba41adf866df2c53","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"\t# Check that Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":138,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_c8a5779c","line":135,"in_reply_to":"ee703fc5_28867319","updated":"2019-05-07 20:52:48.000000000","message":"the cget wont help here.\nwe can get the current target by [target current]\nbut no clue on how to replace the _CHIPNAME.\n\nBTW, the _TARGETNAME is removed is PS5","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"\t# Check that Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":138,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_2810b3ac","line":135,"in_reply_to":"ee703fc5_28e3d3d5","updated":"2019-05-08 14:36:13.000000000","message":"to get the _CHIPNAME from the current target I\u0027ve used this:\nset _CHIPNAME [regsub \".cpu\\\\d$\" [target current] \"\"]","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"208f19a892628f28b8c08a35ea8be861c20a8641","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"\t# Check that Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":138,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_c8bc97b4","line":135,"in_reply_to":"ee703fc5_c8a5779c","updated":"2019-05-07 21:01:43.000000000","message":"For some things, like mem2array, I thought if you didn’t specify a target it automatically used the current target. In the case this is called from an event handler, the current target is temporarily resolved to the target against which the handler is running, so that should solve the invocation from examine-end. If the user chooses to call this function explicitly, I think we can trust them to set the proper target first.\n\nFor computing $_CHIPNAME.cpu1, I’m not sure how to do that. Maybe some string manipulation on [target current]?","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"cf73696690d3ef78c51d500787e1b9e57365af06","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"proc cortex_m4_init {} {"},{"line_number":134,"context_line":"\tglobal _TARGETNAME"},{"line_number":135,"context_line":"\tglobal _CHIPNAME"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"\t# Check that Cortex-M4 is present (bit 16 of chip options register from SYSCFG)"},{"line_number":138,"context_line":"\t# RCC_APB4ENR |\u003d SYSCFGEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"ee703fc5_28e3d3d5","line":135,"in_reply_to":"ee703fc5_c8bc97b4","updated":"2019-05-07 21:26:50.000000000","message":"Yes, I think string manipulation will get the job done","commit_id":"165b661e6f454e1c774db36c95b66438530d13ee"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"b9e4c6dfb9b0db160b1c8584c7a79fc2a245e045","unresolved":false,"context_lines":[{"line_number":136,"context_line":""},{"line_number":137,"context_line":"$_CHIPNAME.cpu0 configure -event examine-end {"},{"line_number":138,"context_line":"\tglobal _DUAL_CORE"},{"line_number":139,"context_line":"\tglobal _CHIPNAME"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"\t# Enable D3 and D1 DBG clocks"},{"line_number":142,"context_line":"\t# DBGMCU_CR |\u003d D3DBGCKEN | D1DBGCKEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"ee703fc5_28ac3384","line":139,"updated":"2019-05-07 19:41:49.000000000","message":"I don’t think you understood my previous comment. Imagine a JTAG chain with chips called foo and bar, both dual-core H7s. You will source this config file twice, once with CHIPNAME set too foo and then again with CHIPNAME set to bar. You will attach this anonymous proc as the examine-end handler to both foo.cpu0 and bar.cpu0. But then, when examination actually ends, you will run the foo.cpu0 examine-end handler, but _CHIPNAME will be bar, not foo, because _CHIPNAME is just an ordinary variable, and the most recent thing it was set too was bar! You want this proc to poke at the target *against which it was invoked*, not the target that *happened to be defined last in the chain*.","commit_id":"04c74c1d7aaae5dfe77782d17b954cb2b2096194"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"8e7cad2c61b60cc4dcaa38d8d7f8e883ee27fcb4","unresolved":false,"context_lines":[{"line_number":136,"context_line":""},{"line_number":137,"context_line":"$_CHIPNAME.cpu0 configure -event examine-end {"},{"line_number":138,"context_line":"\tglobal _DUAL_CORE"},{"line_number":139,"context_line":"\tglobal _CHIPNAME"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"\t# Enable D3 and D1 DBG clocks"},{"line_number":142,"context_line":"\t# DBGMCU_CR |\u003d D3DBGCKEN | D1DBGCKEN"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"ee703fc5_4815e79b","line":139,"in_reply_to":"ee703fc5_28ac3384","updated":"2019-05-08 14:36:13.000000000","message":"Done","commit_id":"04c74c1d7aaae5dfe77782d17b954cb2b2096194"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"4723ff6328302675a941ec6c8a8e79d9c2bd0ccf","unresolved":false,"context_lines":[{"line_number":16,"context_line":"\tset $_CHIPNAME.DUAL_BANK $DUAL_BANK"},{"line_number":17,"context_line":"} else {"},{"line_number":18,"context_line":"\tset $_CHIPNAME.DUAL_BANK 0"},{"line_number":19,"context_line":"}"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"if { [info exists DUAL_CORE] } {"},{"line_number":22,"context_line":"   set $_CHIPNAME.DUAL_CORE $DUAL_CORE"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_68646b46","line":19,"updated":"2019-05-08 17:26:28.000000000","message":"It looks like this file is using a mix of tab and two-space indentation. I’m not sure what the standard is, but your additions also contain examples of both (these blocks here are tab-indented, but the dual-core block just below is two-space-indented).","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":16,"context_line":"\tset $_CHIPNAME.DUAL_BANK $DUAL_BANK"},{"line_number":17,"context_line":"} else {"},{"line_number":18,"context_line":"\tset $_CHIPNAME.DUAL_BANK 0"},{"line_number":19,"context_line":"}"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"if { [info exists DUAL_CORE] } {"},{"line_number":22,"context_line":"   set $_CHIPNAME.DUAL_CORE $DUAL_CORE"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_48e9677a","line":19,"in_reply_to":"ee703fc5_68646b46","updated":"2019-05-09 15:15:10.000000000","message":"indeed the file is using both of spaces and tabs as indent.\nI believe there is no standard in openocd, otherwise tools/checkpatch.sh should raise an error.\nPersonally, I prefer tabs, they use less chars ...\n\u003e\u003e will change it accordingly","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":52,"context_line":"} else {"},{"line_number":53,"context_line":"   if { [using_jtag] } {"},{"line_number":54,"context_line":"\t  set _CPUTAPID 0x6ba00477"},{"line_number":55,"context_line":"   } {"},{"line_number":56,"context_line":"      set _CPUTAPID 0x6ba02477"},{"line_number":57,"context_line":"   }"},{"line_number":58,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_08fb6f45","line":55,"updated":"2019-05-09 15:15:10.000000000","message":"is it missing an \u0027else\u0027 here ?","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"eb1c6ceb9936a56e497ddbaeb38a8895f9aabc08","unresolved":false,"context_lines":[{"line_number":52,"context_line":"} else {"},{"line_number":53,"context_line":"   if { [using_jtag] } {"},{"line_number":54,"context_line":"\t  set _CPUTAPID 0x6ba00477"},{"line_number":55,"context_line":"   } {"},{"line_number":56,"context_line":"      set _CPUTAPID 0x6ba02477"},{"line_number":57,"context_line":"   }"},{"line_number":58,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_a88e03d4","line":55,"in_reply_to":"ee703fc5_08fb6f45","updated":"2019-05-09 17:11:45.000000000","message":"Per the Jimtcl reference manual, “The then and else arguments are optional \"noise words\" to make the command easier to read.” So I guess not.","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"4723ff6328302675a941ec6c8a8e79d9c2bd0ccf","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1 | WDGLSD2"},{"line_number":155,"context_line":"\tmmw 0x5C001054 0x000C0000 0"},{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif {[set $_CHIPNAME.DUAL_CORE] \u0026\u0026 [stm32h7x_is_cpu1_alive]} {"},{"line_number":158,"context_line":"\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":159,"context_line":""},{"line_number":160,"context_line":"\t\tif {[set $_CHIPNAME.USE_CTI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_8869bf1f","line":157,"updated":"2019-05-08 17:26:28.000000000","message":"The stm32h7x_is_cpu1_alive proc does lots of things that probably aren’t possible while SRST is asserted (e.g. accessing RCC, FLASH, and SYSCFG). I would like, eventually, to introduce code that accesses DBGMCU via AP2 instead of AP0 if using a non-HLA, so that you can use connect_assert_srst, which is more reliable. However, I believe RCC, FLASH, and SYSCFG are not accessible via AP2, so calling stm32h7x_is_cpu1_alive at that point would fail. Would it be possible to do this block at reset-deassert-post instead of examine-end?","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1 | WDGLSD2"},{"line_number":155,"context_line":"\tmmw 0x5C001054 0x000C0000 0"},{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif {[set $_CHIPNAME.DUAL_CORE] \u0026\u0026 [stm32h7x_is_cpu1_alive]} {"},{"line_number":158,"context_line":"\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":159,"context_line":""},{"line_number":160,"context_line":"\t\tif {[set $_CHIPNAME.USE_CTI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_289bd31c","line":157,"in_reply_to":"ee703fc5_8869bf1f","updated":"2019-05-09 15:15:10.000000000","message":"I will send a PS7 fixing the other points except this one.\nto solve this I need to push tests further","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"9b9322637eb82efc4a7cba8d568c929d1c5dab6f","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1 | WDGLSD2"},{"line_number":155,"context_line":"\tmmw 0x5C001054 0x000C0000 0"},{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif {[set $_CHIPNAME.DUAL_CORE] \u0026\u0026 [stm32h7x_is_cpu1_alive]} {"},{"line_number":158,"context_line":"\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":159,"context_line":""},{"line_number":160,"context_line":"\t\tif {[set $_CHIPNAME.USE_CTI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_f3ab9019","line":157,"in_reply_to":"ee703fc5_8869bf1f","updated":"2019-05-17 10:33:59.000000000","message":"what if the user changes the reset_config to none, the reset-deassert-post won\u0027t be launched.","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"a113fa71870653cadb6d5d9e083f2c72cdba08d3","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1 | WDGLSD2"},{"line_number":155,"context_line":"\tmmw 0x5C001054 0x000C0000 0"},{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif {[set $_CHIPNAME.DUAL_CORE] \u0026\u0026 [stm32h7x_is_cpu1_alive]} {"},{"line_number":158,"context_line":"\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":159,"context_line":""},{"line_number":160,"context_line":"\t\tif {[set $_CHIPNAME.USE_CTI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_73678023","line":157,"in_reply_to":"ee703fc5_b3a51846","updated":"2019-05-17 13:20:22.000000000","message":"is that checking reset_config (in examine-end) is enough to decide to postpone the H7 configuration to reset-deassert-port or reset-end.\nI\u0027m asking the question because even with \"reset_config srst_only connect_assert_srst\" , the reset events are not called while connecting under reset.\nany hint could be helpful.","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"414d46b2a5966bb985153a0547ea2e1c75247360","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t# DBGMCU_APB4FZ1 |\u003d WDGLSD1 | WDGLSD2"},{"line_number":155,"context_line":"\tmmw 0x5C001054 0x000C0000 0"},{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif {[set $_CHIPNAME.DUAL_CORE] \u0026\u0026 [stm32h7x_is_cpu1_alive]} {"},{"line_number":158,"context_line":"\t\t$_CHIPNAME.cpu1 arp_examine"},{"line_number":159,"context_line":""},{"line_number":160,"context_line":"\t\tif {[set $_CHIPNAME.USE_CTI]} {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_b3a51846","line":157,"in_reply_to":"ee703fc5_f3ab9019","updated":"2019-05-17 11:02:47.000000000","message":"If reset_config is set to none, Cortex-M specific SYSRESETREQ or VECTRESET is used instead of pulsing SRTS. No matter of reset_config any reset command emits all reset-asert-pre|post and reset-deassert-pre|post events.\n\nBut if a reset command is not issued at all, then reset-deassert-post won\u0027t be launched. So H7 configuration using AP0 should be called from examine-end if SRST is not active or postponed to reset-deassert-post if SRST was active during examine.","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"4723ff6328302675a941ec6c8a8e79d9c2bd0ccf","unresolved":false,"context_lines":[{"line_number":233,"context_line":""},{"line_number":234,"context_line":"\t# create CTI instances for both cores"},{"line_number":235,"context_line":"\tcti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000"},{"line_number":236,"context_line":"\tcti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000"},{"line_number":237,"context_line":""},{"line_number":238,"context_line":"\t$_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }"},{"line_number":239,"context_line":"\t$_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_285e737c","line":236,"updated":"2019-05-08 17:26:28.000000000","message":"Is USE_CTI\u003d1, DUAL_CORE\u003d0 legal? If so, this will presumably fail. If not, perhaps a message should be printed accordingly?","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":233,"context_line":""},{"line_number":234,"context_line":"\t# create CTI instances for both cores"},{"line_number":235,"context_line":"\tcti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000"},{"line_number":236,"context_line":"\tcti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000"},{"line_number":237,"context_line":""},{"line_number":238,"context_line":"\t$_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }"},{"line_number":239,"context_line":"\t$_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_a8f7e355","line":236,"in_reply_to":"ee703fc5_285e737c","updated":"2019-05-09 15:15:10.000000000","message":"USE_CTI is set to 0 when DUAL_CORE\u003d0 in Line 33, but without a warning.\nissuing a warning seems correct","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"4723ff6328302675a941ec6c8a8e79d9c2bd0ccf","unresolved":false,"context_lines":[{"line_number":274,"context_line":"\t\t# Acknowlodge EDBGRQ at TRIGOUT0"},{"line_number":275,"context_line":"\t\t$_CHIPNAME.$cti write INACK 0x01"},{"line_number":276,"context_line":"\t\t$_CHIPNAME.$cti write INACK 0x00"},{"line_number":277,"context_line":"\t}"},{"line_number":278,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_4863a73b","line":277,"updated":"2019-05-08 17:26:28.000000000","message":"Should these procs have stm32h7x_ in front of their names?","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":274,"context_line":"\t\t# Acknowlodge EDBGRQ at TRIGOUT0"},{"line_number":275,"context_line":"\t\t$_CHIPNAME.$cti write INACK 0x01"},{"line_number":276,"context_line":"\t\t$_CHIPNAME.$cti write INACK 0x00"},{"line_number":277,"context_line":"\t}"},{"line_number":278,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_e8fddb39","line":277,"in_reply_to":"ee703fc5_4863a73b","updated":"2019-05-09 15:15:10.000000000","message":"agree","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"}],"tcl/target/stm32h7x_dual_bank.cfg":[{"author":{"_account_id":1000716,"name":"Christopher Head","email":"chead@zaber.com","username":"Hawk777"},"change_message_id":"4723ff6328302675a941ec6c8a8e79d9c2bd0ccf","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# script for stm32h7x family (dual flash bank)"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"# STM32H7xxxI 2Mo have a dual bank flash."},{"line_number":4,"context_line":"set DUAL_BANK 1"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"source [find target/stm32h7x.cfg]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_c877b7fc","line":4,"updated":"2019-05-08 17:26:28.000000000","message":"I just thought of something odd. If I write an OpenOCD config file that looks like this:\n\nsource [find target/stm32h7x_dual_bank.cfg]\nsource [find target/stm32h7x.cfg]\n\nthen I will get two dual-bank targets, because nobody clears DUAL_BANK in between the two includes.","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16ddba0c7fdb476400f6c55287e4d8e95b4e697d","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# script for stm32h7x family (dual flash bank)"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"# STM32H7xxxI 2Mo have a dual bank flash."},{"line_number":4,"context_line":"set DUAL_BANK 1"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"source [find target/stm32h7x.cfg]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"ee703fc5_28e433a3","line":4,"in_reply_to":"ee703fc5_c877b7fc","updated":"2019-05-09 15:15:10.000000000","message":"yeah, true.\nAnd this is applicable also on DUAL_CORE and USE_CTI","commit_id":"50518487500c5fd00e7ec4bf1ebe6de0b38a7633"}]}