)]}'
{"configure.ac":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"132e8ab0206d1c286c3ff552c2eeae6ae0ab4bcb","unresolved":false,"context_lines":[{"line_number":330,"context_line":"    ])"},{"line_number":331,"context_line":""},{"line_number":332,"context_line":"    AS_IF([test \"x$build_xlnx_pcie_xvc\" \u003d \"xyes\"], ["},{"line_number":333,"context_line":"      AC_MSG_ERROR([xlnx_pcie_xvc is only availabe on linux])"},{"line_number":334,"context_line":"    ])"},{"line_number":335,"context_line":"])"},{"line_number":336,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":4,"id":"8e7fc396_d0be84fa","line":333,"updated":"2019-10-04 08:17:59.000000000","message":"typo! s/availabe/available/","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"d05dda6ce8fed4805ed6d607114abb77675df5d6","unresolved":false,"context_lines":[{"line_number":330,"context_line":"    ])"},{"line_number":331,"context_line":""},{"line_number":332,"context_line":"    AS_IF([test \"x$build_xlnx_pcie_xvc\" \u003d \"xyes\"], ["},{"line_number":333,"context_line":"      AC_MSG_ERROR([xlnx_pcie_xvc is only availabe on linux])"},{"line_number":334,"context_line":"    ])"},{"line_number":335,"context_line":"])"},{"line_number":336,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":4,"id":"8e7fc396_106b9c83","line":333,"in_reply_to":"8e7fc396_d0be84fa","updated":"2019-10-04 17:00:24.000000000","message":"Done","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"}],"doc/openocd.texi":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"132e8ab0206d1c286c3ff552c2eeae6ae0ab4bcb","unresolved":false,"context_lines":[{"line_number":3111,"context_line":"exposed via extended capability registers in the PCIe configuration space."},{"line_number":3112,"context_line":""},{"line_number":3113,"context_line":"@deffn {Config Command} {xlnx_pcie_xvc_config} device"},{"line_number":3114,"context_line":"Specifies the PCI express device via parameter @var{device} to use."},{"line_number":3115,"context_line":"@end deffn"},{"line_number":3116,"context_line":"@end deffn"},{"line_number":3117,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"8e7fc396_7033f0c0","line":3114,"updated":"2019-10-04 08:17:59.000000000","message":"Maybe could help describing how a user can find the string for \"device\". The tool \"lspci\" can help, but then I do not know how to explain that \"lspci\" returns something like:\n24:00.2 SD Host controller: bla bla bla...\nand instead here we need to specify \"0000:24:00.2\" !?!\n\nIs there any other method, more user-friendly to find it, maybe even at cost of more complex code to connect to it?","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"d05dda6ce8fed4805ed6d607114abb77675df5d6","unresolved":false,"context_lines":[{"line_number":3111,"context_line":"exposed via extended capability registers in the PCIe configuration space."},{"line_number":3112,"context_line":""},{"line_number":3113,"context_line":"@deffn {Config Command} {xlnx_pcie_xvc_config} device"},{"line_number":3114,"context_line":"Specifies the PCI express device via parameter @var{device} to use."},{"line_number":3115,"context_line":"@end deffn"},{"line_number":3116,"context_line":"@end deffn"},{"line_number":3117,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"8e7fc396_b050a8da","line":3114,"in_reply_to":"8e7fc396_7033f0c0","updated":"2019-10-04 17:00:24.000000000","message":"Yeah I was torn on that one. The leading zeroes are \u0027domain\u0027.  I\u0027ll fix up the documentation with how to get the string.\n\nYou can get the output by:\n\n$lspci -D\n\nMost people will probably only ever have seen 0000 as domain, but I don\u0027t know of a better unique description for a PCI device. I\u0027m open to suggestions, though ... :)","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"}],"src/jtag/drivers/xlnx-pcie-xvc.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"132e8ab0206d1c286c3ff552c2eeae6ae0ab4bcb","unresolved":false,"context_lines":[{"line_number":350,"context_line":"\t}"},{"line_number":351,"context_line":"\tif ((xlnx_pcie_xvc-\u003eoffset \u003e PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||"},{"line_number":352,"context_line":"\t     xlnx_pcie_xvc-\u003eoffset \u003c PCIE_EXT_CAP_LST)"},{"line_number":353,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":354,"context_line":""},{"line_number":355,"context_line":"\tLOG_INFO(\"Found Xilinx XVC/PCIe capability at offset: %x\", xlnx_pcie_xvc-\u003eoffset);"},{"line_number":356,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"8e7fc396_90380c9d","line":353,"updated":"2019-10-04 08:17:59.000000000","message":"maybe close(xlnx_pcie_xvc-\u003efd) before return error?\n\nI think we should left xlnx_pcie_xvc-\u003edevice allocated, in case of a new call to init(), even if this causes a memory leak.","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"d05dda6ce8fed4805ed6d607114abb77675df5d6","unresolved":false,"context_lines":[{"line_number":350,"context_line":"\t}"},{"line_number":351,"context_line":"\tif ((xlnx_pcie_xvc-\u003eoffset \u003e PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||"},{"line_number":352,"context_line":"\t     xlnx_pcie_xvc-\u003eoffset \u003c PCIE_EXT_CAP_LST)"},{"line_number":353,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":354,"context_line":""},{"line_number":355,"context_line":"\tLOG_INFO(\"Found Xilinx XVC/PCIe capability at offset: %x\", xlnx_pcie_xvc-\u003eoffset);"},{"line_number":356,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"8e7fc396_d04d2441","line":353,"in_reply_to":"8e7fc396_90380c9d","updated":"2019-10-04 17:00:24.000000000","message":"Good catch.","commit_id":"8d2992a3c983486ba6810773822837094e1b98ce"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":51,"context_line":""},{"line_number":52,"context_line":"\tret \u003d pread(xlnx_pcie_xvc-\u003efd, \u0026res, sizeof(res),"},{"line_number":53,"context_line":"\t\t    xlnx_pcie_xvc-\u003eoffset + offset);"},{"line_number":54,"context_line":"\tif (ret \u003c 4)"},{"line_number":55,"context_line":"\t\tLOG_ERROR(\"Failed to read offset %x\", offset);"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"\treturn res;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_f0f4e0cd","line":54,"range":{"start_line":54,"start_character":11,"end_line":54,"end_character":12},"updated":"2019-10-05 16:39:10.000000000","message":"Not mandatory, but much more readable if you replace s/4/sizeof(res)/","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":51,"context_line":""},{"line_number":52,"context_line":"\tret \u003d pread(xlnx_pcie_xvc-\u003efd, \u0026res, sizeof(res),"},{"line_number":53,"context_line":"\t\t    xlnx_pcie_xvc-\u003eoffset + offset);"},{"line_number":54,"context_line":"\tif (ret \u003c 4)"},{"line_number":55,"context_line":"\t\tLOG_ERROR(\"Failed to read offset %x\", offset);"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"\treturn res;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_70d77029","line":54,"range":{"start_line":54,"start_character":11,"end_line":54,"end_character":12},"in_reply_to":"8e7fc396_f0f4e0cd","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":54,"context_line":"\tif (ret \u003c 4)"},{"line_number":55,"context_line":"\t\tLOG_ERROR(\"Failed to read offset %x\", offset);"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"\treturn res;"},{"line_number":58,"context_line":"}"},{"line_number":59,"context_line":""},{"line_number":60,"context_line":"static void xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_10f2bcdf","line":57,"updated":"2019-10-05 16:39:10.000000000","message":"What about endianess of host and PCIe device? Is it managed directly in the PCIe controller?","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"89c178f621a56136eb8003990e28e5feb552c71d","unresolved":false,"context_lines":[{"line_number":54,"context_line":"\tif (ret \u003c 4)"},{"line_number":55,"context_line":"\t\tLOG_ERROR(\"Failed to read offset %x\", offset);"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"\treturn res;"},{"line_number":58,"context_line":"}"},{"line_number":59,"context_line":""},{"line_number":60,"context_line":"static void xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_f01b801f","line":57,"in_reply_to":"8e7fc396_10f2bcdf","updated":"2019-10-05 18:45:42.000000000","message":"The sysfs code should go through pci_read_config_dword() or pci_user_read_config_dword() which to my knowledge would deal with the conversion. See LDD3 chapter 12 for example.","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":54,"context_line":"\tif (ret \u003c 4)"},{"line_number":55,"context_line":"\t\tLOG_ERROR(\"Failed to read offset %x\", offset);"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"\treturn res;"},{"line_number":58,"context_line":"}"},{"line_number":59,"context_line":""},{"line_number":60,"context_line":"static void xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_90dc8c4d","line":57,"in_reply_to":"8e7fc396_f01b801f","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":63,"context_line":""},{"line_number":64,"context_line":"\tret \u003d pwrite(xlnx_pcie_xvc-\u003efd, \u0026val, sizeof(val),"},{"line_number":65,"context_line":"\t\t     xlnx_pcie_xvc-\u003eoffset + offset);"},{"line_number":66,"context_line":"\tif (ret \u003c 4)"},{"line_number":67,"context_line":"\t\tLOG_ERROR(\"Failed to write offset: %x with value: %x\","},{"line_number":68,"context_line":"\t\t\t  offset, val);"},{"line_number":69,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_b0fe68aa","line":66,"range":{"start_line":66,"start_character":11,"end_line":66,"end_character":12},"updated":"2019-10-05 16:39:10.000000000","message":"similar as above, s/4/sizeof(val)/","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":63,"context_line":""},{"line_number":64,"context_line":"\tret \u003d pwrite(xlnx_pcie_xvc-\u003efd, \u0026val, sizeof(val),"},{"line_number":65,"context_line":"\t\t     xlnx_pcie_xvc-\u003eoffset + offset);"},{"line_number":66,"context_line":"\tif (ret \u003c 4)"},{"line_number":67,"context_line":"\t\tLOG_ERROR(\"Failed to write offset: %x with value: %x\","},{"line_number":68,"context_line":"\t\t\t  offset, val);"},{"line_number":69,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_d0120401","line":66,"range":{"start_line":66,"start_character":11,"end_line":66,"end_character":12},"in_reply_to":"8e7fc396_b0fe68aa","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":330,"context_line":"\twhile (xlnx_pcie_xvc-\u003eoffset \u003c\u003d PCI_CFG_SPACE_EXP_SIZE - 4 \u0026\u0026"},{"line_number":331,"context_line":"\t       xlnx_pcie_xvc-\u003eoffset \u003e\u003d PCIE_EXT_CAP_LST) {"},{"line_number":332,"context_line":"\t\tcap \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP);"},{"line_number":333,"context_line":"\t\tLOG_DEBUG(\"Checking capability at 0x%x; id\u003d%04x version\u003d%x next\u003d%x\","},{"line_number":334,"context_line":"\t\t\t xlnx_pcie_xvc-\u003eoffset,"},{"line_number":335,"context_line":"\t\t\t PCI_EXT_CAP_ID(cap),"},{"line_number":336,"context_line":"\t\t\t PCI_EXT_CAP_VER(cap),"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_d0fbe4b8","line":333,"updated":"2019-10-05 16:39:10.000000000","message":"Maybe adding 0x in front of all the \"%x\"","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":330,"context_line":"\twhile (xlnx_pcie_xvc-\u003eoffset \u003c\u003d PCI_CFG_SPACE_EXP_SIZE - 4 \u0026\u0026"},{"line_number":331,"context_line":"\t       xlnx_pcie_xvc-\u003eoffset \u003e\u003d PCIE_EXT_CAP_LST) {"},{"line_number":332,"context_line":"\t\tcap \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP);"},{"line_number":333,"context_line":"\t\tLOG_DEBUG(\"Checking capability at 0x%x; id\u003d%04x version\u003d%x next\u003d%x\","},{"line_number":334,"context_line":"\t\t\t xlnx_pcie_xvc-\u003eoffset,"},{"line_number":335,"context_line":"\t\t\t PCI_EXT_CAP_ID(cap),"},{"line_number":336,"context_line":"\t\t\t PCI_EXT_CAP_VER(cap),"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_10e87cdc","line":333,"in_reply_to":"8e7fc396_d0fbe4b8","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":337,"context_line":"\t\t\t PCI_EXT_CAP_NEXT(cap));"},{"line_number":338,"context_line":"\t\tif (PCI_EXT_CAP_ID(cap) \u003d\u003d PCI_EXT_CAP_ID_VNDR) {"},{"line_number":339,"context_line":"\t\t\tvh \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR);"},{"line_number":340,"context_line":"\t\t\tLOG_DEBUG(\"Checking possible match at %x; id: %x; rev: %x; length: %x\","},{"line_number":341,"context_line":"\t\t\t\t xlnx_pcie_xvc-\u003eoffset,"},{"line_number":342,"context_line":"\t\t\t\t PCI_VNDR_HEADER_ID(vh),"},{"line_number":343,"context_line":"\t\t\t\t PCI_VNDR_HEADER_REV(vh),"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_7028d032","line":340,"updated":"2019-10-05 16:39:10.000000000","message":"again 0x in front of %x","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":337,"context_line":"\t\t\t PCI_EXT_CAP_NEXT(cap));"},{"line_number":338,"context_line":"\t\tif (PCI_EXT_CAP_ID(cap) \u003d\u003d PCI_EXT_CAP_ID_VNDR) {"},{"line_number":339,"context_line":"\t\t\tvh \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR);"},{"line_number":340,"context_line":"\t\t\tLOG_DEBUG(\"Checking possible match at %x; id: %x; rev: %x; length: %x\","},{"line_number":341,"context_line":"\t\t\t\t xlnx_pcie_xvc-\u003eoffset,"},{"line_number":342,"context_line":"\t\t\t\t PCI_VNDR_HEADER_ID(vh),"},{"line_number":343,"context_line":"\t\t\t\t PCI_VNDR_HEADER_REV(vh),"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_b0f428bb","line":340,"in_reply_to":"8e7fc396_7028d032","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":354,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":355,"context_line":"\t}"},{"line_number":356,"context_line":""},{"line_number":357,"context_line":"\tLOG_INFO(\"Found Xilinx XVC/PCIe capability at offset: %x\", xlnx_pcie_xvc-\u003eoffset);"},{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\treturn ERROR_OK;"},{"line_number":360,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_902d6c44","line":357,"updated":"2019-10-05 16:39:10.000000000","message":"again 0x in front of %x","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"0ad6317c4e8313874f8d91d22882b7251b657862","unresolved":false,"context_lines":[{"line_number":354,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":355,"context_line":"\t}"},{"line_number":356,"context_line":""},{"line_number":357,"context_line":"\tLOG_INFO(\"Found Xilinx XVC/PCIe capability at offset: %x\", xlnx_pcie_xvc-\u003eoffset);"},{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\treturn ERROR_OK;"},{"line_number":360,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_d0f1a4c9","line":357,"in_reply_to":"8e7fc396_902d6c44","updated":"2019-10-05 19:29:19.000000000","message":"Done","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4bb9cdf674b1d7d311e16ec70d84b1bc46e50e7f","unresolved":false,"context_lines":[{"line_number":375,"context_line":"\tif (CMD_ARGC \u003c 1)"},{"line_number":376,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":377,"context_line":""},{"line_number":378,"context_line":"\txlnx_pcie_xvc-\u003edevice \u003d strdup(CMD_ARGV[0]);"},{"line_number":379,"context_line":"\treturn ERROR_OK;"},{"line_number":380,"context_line":"}"},{"line_number":381,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_30225851","line":378,"updated":"2019-10-05 16:39:10.000000000","message":"we do not have a way to safely free() this string so, for the time being, we have to live with this memory leak.\nBut to avoid excessive leaks in case this command get called over and over, before the assignment you should add\nif (xlnx_pcie_xvc-\u003edevice)\n    free(xlnx_pcie_xvc-\u003edevice);","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"89c178f621a56136eb8003990e28e5feb552c71d","unresolved":false,"context_lines":[{"line_number":375,"context_line":"\tif (CMD_ARGC \u003c 1)"},{"line_number":376,"context_line":"\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":377,"context_line":""},{"line_number":378,"context_line":"\txlnx_pcie_xvc-\u003edevice \u003d strdup(CMD_ARGV[0]);"},{"line_number":379,"context_line":"\treturn ERROR_OK;"},{"line_number":380,"context_line":"}"},{"line_number":381,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"8e7fc396_10195c27","line":378,"in_reply_to":"8e7fc396_30225851","updated":"2019-10-05 18:45:42.000000000","message":"That\u0027s a good suggestion. Will do. Thanks!","commit_id":"53d1acc915de9293172ecb80cbbe74e0deb4798f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"10b5dc2f4b4f5006a604b9b1a23e3e37ab548d7e","unresolved":false,"context_lines":[{"line_number":208,"context_line":"\t\telse if (path[i] \u003d\u003d tap_state_transition(tap_get_state(), true))"},{"line_number":209,"context_line":"\t\t\terr \u003d xlnx_pcie_xvc_transact(1, 0, 0, NULL);"},{"line_number":210,"context_line":"\t\telse"},{"line_number":211,"context_line":"\t\t\tLOG_ERROR(\"BUG: %s -\u003e %s isn\u0027t a valid TAP transition.\","},{"line_number":212,"context_line":"\t\t\t\t  tap_state_name(tap_get_state()),"},{"line_number":213,"context_line":"\t\t\t\t  tap_state_name(path[i]));"},{"line_number":214,"context_line":"\t\tif (err !\u003d ERROR_OK)"},{"line_number":215,"context_line":"\t\t\treturn err;"},{"line_number":216,"context_line":"\t\ttap_set_state(path[i]);"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"8e7fc396_d08be4c2","line":213,"range":{"start_line":211,"start_character":0,"end_line":213,"end_character":31},"updated":"2019-10-18 10:06:58.000000000","message":"should this case return error too?","commit_id":"cf445b6d77991e8dd209fd76c3c850731d22e367"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"f6b09a2d0c18470cf8a1c96e3fdfb9ec41d9d11e","unresolved":false,"context_lines":[{"line_number":208,"context_line":"\t\telse if (path[i] \u003d\u003d tap_state_transition(tap_get_state(), true))"},{"line_number":209,"context_line":"\t\t\terr \u003d xlnx_pcie_xvc_transact(1, 0, 0, NULL);"},{"line_number":210,"context_line":"\t\telse"},{"line_number":211,"context_line":"\t\t\tLOG_ERROR(\"BUG: %s -\u003e %s isn\u0027t a valid TAP transition.\","},{"line_number":212,"context_line":"\t\t\t\t  tap_state_name(tap_get_state()),"},{"line_number":213,"context_line":"\t\t\t\t  tap_state_name(path[i]));"},{"line_number":214,"context_line":"\t\tif (err !\u003d ERROR_OK)"},{"line_number":215,"context_line":"\t\t\treturn err;"},{"line_number":216,"context_line":"\t\ttap_set_state(path[i]);"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"8e7fc396_70677023","line":213,"range":{"start_line":211,"start_character":0,"end_line":213,"end_character":31},"in_reply_to":"8e7fc396_d08be4c2","updated":"2019-10-18 16:42:56.000000000","message":"Done","commit_id":"cf445b6d77991e8dd209fd76c3c850731d22e367"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#define XLNX_XVC_EXT_CAP\t0x00"},{"line_number":26,"context_line":"#define XLNX_XVC_VSEC_HDR\t0x04"},{"line_number":27,"context_line":"#define XLNX_XVC_VERSION\t0x08"},{"line_number":28,"context_line":"#define XLNX_XVC_LEN_REG\t0x0C"},{"line_number":29,"context_line":"#define XLNX_XVC_TMS_REG\t0x10"},{"line_number":30,"context_line":"#define XLNX_XVC_TDx_REG\t0x14"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_4b588535","line":27,"updated":"2019-10-24 05:48:05.000000000","message":"Please, remove unused defines","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"510ccf3319d034281139a64db70f9ff709548097","unresolved":false,"context_lines":[{"line_number":24,"context_line":""},{"line_number":25,"context_line":"#define XLNX_XVC_EXT_CAP\t0x00"},{"line_number":26,"context_line":"#define XLNX_XVC_VSEC_HDR\t0x04"},{"line_number":27,"context_line":"#define XLNX_XVC_VERSION\t0x08"},{"line_number":28,"context_line":"#define XLNX_XVC_LEN_REG\t0x0C"},{"line_number":29,"context_line":"#define XLNX_XVC_TMS_REG\t0x10"},{"line_number":30,"context_line":"#define XLNX_XVC_TDx_REG\t0x14"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_4bae45e6","line":27,"in_reply_to":"8e7fc396_4b588535","updated":"2019-10-24 15:46:21.000000000","message":"Done","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":28,"context_line":"#define XLNX_XVC_LEN_REG\t0x0C"},{"line_number":29,"context_line":"#define XLNX_XVC_TMS_REG\t0x10"},{"line_number":30,"context_line":"#define XLNX_XVC_TDx_REG\t0x14"},{"line_number":31,"context_line":"#define XLNX_XVC_STS_REG\t0x1c"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"#define XLNX_XVC_CAP_SIZE\t0x20"},{"line_number":34,"context_line":"#define XLNX_XVC_VSEC_ID\t0x8"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_eb3cf1be","line":31,"updated":"2019-10-24 05:48:05.000000000","message":"remove unused define","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"510ccf3319d034281139a64db70f9ff709548097","unresolved":false,"context_lines":[{"line_number":28,"context_line":"#define XLNX_XVC_LEN_REG\t0x0C"},{"line_number":29,"context_line":"#define XLNX_XVC_TMS_REG\t0x10"},{"line_number":30,"context_line":"#define XLNX_XVC_TDx_REG\t0x14"},{"line_number":31,"context_line":"#define XLNX_XVC_STS_REG\t0x1c"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"#define XLNX_XVC_CAP_SIZE\t0x20"},{"line_number":34,"context_line":"#define XLNX_XVC_VSEC_ID\t0x8"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_ebb2b147","line":31,"in_reply_to":"8e7fc396_eb3cf1be","updated":"2019-10-24 15:46:21.000000000","message":"Done","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":293,"context_line":"static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)"},{"line_number":294,"context_line":"{"},{"line_number":295,"context_line":"\tLOG_DEBUG(\"reset trst: %i srst: %i\", cmd-\u003ecmd.reset-\u003etrst,"},{"line_number":296,"context_line":"\t\t  cmd-\u003ecmd.reset-\u003esrst);"},{"line_number":297,"context_line":"}"},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_8b753d95","line":296,"updated":"2019-10-24 05:48:05.000000000","message":"Are there any reason why proper reset can\u0027t be implemented?","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"5f477cf95687e85639cddfcce0573c66078a8975","unresolved":false,"context_lines":[{"line_number":293,"context_line":"static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)"},{"line_number":294,"context_line":"{"},{"line_number":295,"context_line":"\tLOG_DEBUG(\"reset trst: %i srst: %i\", cmd-\u003ecmd.reset-\u003etrst,"},{"line_number":296,"context_line":"\t\t  cmd-\u003ecmd.reset-\u003esrst);"},{"line_number":297,"context_line":"}"},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_eb6391d8","line":296,"in_reply_to":"8e7fc396_8b753d95","updated":"2019-10-24 06:48:16.000000000","message":"It\u0027s not wired up in HW, so I don\u0027t really know how?","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":315,"context_line":"\twhile (left) {"},{"line_number":316,"context_line":"\t\twrite \u003d MIN(XLNX_XVC_MAX_BITS, left);"},{"line_number":317,"context_line":"\t\ttms \u003d buf_get_u32(bits, 0, write);"},{"line_number":318,"context_line":"\t\txlnx_pcie_xvc_transact(write, tms, 0, NULL);"},{"line_number":319,"context_line":"\t\tleft -\u003d write;"},{"line_number":320,"context_line":"\t\tbits +\u003d 4;"},{"line_number":321,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_0b3a8dc0","line":318,"updated":"2019-10-24 05:48:05.000000000","message":"this function may return an error","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"5f477cf95687e85639cddfcce0573c66078a8975","unresolved":false,"context_lines":[{"line_number":315,"context_line":"\twhile (left) {"},{"line_number":316,"context_line":"\t\twrite \u003d MIN(XLNX_XVC_MAX_BITS, left);"},{"line_number":317,"context_line":"\t\ttms \u003d buf_get_u32(bits, 0, write);"},{"line_number":318,"context_line":"\t\txlnx_pcie_xvc_transact(write, tms, 0, NULL);"},{"line_number":319,"context_line":"\t\tleft -\u003d write;"},{"line_number":320,"context_line":"\t\tbits +\u003d 4;"},{"line_number":321,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_0b612dd0","line":318,"in_reply_to":"8e7fc396_0b3a8dc0","updated":"2019-10-24 06:48:16.000000000","message":"Good catch, thanks!","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"510ccf3319d034281139a64db70f9ff709548097","unresolved":false,"context_lines":[{"line_number":315,"context_line":"\twhile (left) {"},{"line_number":316,"context_line":"\t\twrite \u003d MIN(XLNX_XVC_MAX_BITS, left);"},{"line_number":317,"context_line":"\t\ttms \u003d buf_get_u32(bits, 0, write);"},{"line_number":318,"context_line":"\t\txlnx_pcie_xvc_transact(write, tms, 0, NULL);"},{"line_number":319,"context_line":"\t\tleft -\u003d write;"},{"line_number":320,"context_line":"\t\tbits +\u003d 4;"},{"line_number":321,"context_line":"\t};"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_0bb04d3d","line":318,"in_reply_to":"8e7fc396_0b612dd0","updated":"2019-10-24 15:46:21.000000000","message":"Done","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":379,"context_line":"\tint err;"},{"line_number":380,"context_line":""},{"line_number":381,"context_line":"\tsnprintf(filename, PATH_MAX, \"/sys/bus/pci/devices/%s/config\","},{"line_number":382,"context_line":"\t\t xlnx_pcie_xvc-\u003edevice);"},{"line_number":383,"context_line":"\txlnx_pcie_xvc-\u003efd \u003d open(filename, O_RDWR | O_SYNC);"},{"line_number":384,"context_line":"\tif (xlnx_pcie_xvc-\u003efd \u003c 0) {"},{"line_number":385,"context_line":"\t\tLOG_ERROR(\"Failed to open device: %s\", filename);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_2b6ae9b1","line":382,"updated":"2019-10-24 05:48:05.000000000","message":"How do we get a proper permission here? This files are writable only for root.","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"5f477cf95687e85639cddfcce0573c66078a8975","unresolved":false,"context_lines":[{"line_number":379,"context_line":"\tint err;"},{"line_number":380,"context_line":""},{"line_number":381,"context_line":"\tsnprintf(filename, PATH_MAX, \"/sys/bus/pci/devices/%s/config\","},{"line_number":382,"context_line":"\t\t xlnx_pcie_xvc-\u003edevice);"},{"line_number":383,"context_line":"\txlnx_pcie_xvc-\u003efd \u003d open(filename, O_RDWR | O_SYNC);"},{"line_number":384,"context_line":"\tif (xlnx_pcie_xvc-\u003efd \u003c 0) {"},{"line_number":385,"context_line":"\t\tLOG_ERROR(\"Failed to open device: %s\", filename);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_6b9f81ba","line":382,"in_reply_to":"8e7fc396_2b6ae9b1","updated":"2019-10-24 06:48:16.000000000","message":"Tbh, haven\u0027t looked at that much, yet. I figured if people wanna run this  it\u0027s for debugging purposes and using root is most likely ok in a development setup. Any ideas?","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a6904e71624c6a731d95ee622e7b082ca09354c6","unresolved":false,"context_lines":[{"line_number":379,"context_line":"\tint err;"},{"line_number":380,"context_line":""},{"line_number":381,"context_line":"\tsnprintf(filename, PATH_MAX, \"/sys/bus/pci/devices/%s/config\","},{"line_number":382,"context_line":"\t\t xlnx_pcie_xvc-\u003edevice);"},{"line_number":383,"context_line":"\txlnx_pcie_xvc-\u003efd \u003d open(filename, O_RDWR | O_SYNC);"},{"line_number":384,"context_line":"\tif (xlnx_pcie_xvc-\u003efd \u003c 0) {"},{"line_number":385,"context_line":"\t\tLOG_ERROR(\"Failed to open device: %s\", filename);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_0bde0d71","line":382,"in_reply_to":"8e7fc396_6b9f81ba","updated":"2019-10-26 20:51:34.000000000","message":"\"sudo chown\" or \"sudo chmod\" helps running openocd as normal user. Eventually inside a boot script.\n\nUsually I \"abuse\" of udev rules for this kind of cases, as I wrote in the commit message of\nhttp://openocd.zylin.com/5302\nbut I just figured-out that there is another method\nhttps://unix.stackexchange.com/questions/312103/udev-for-sys-file-not-working\n\nI don\u0027t think that a tmpfiles.d rule for all the files \"/sys/bus/pci/devices/*/config\" could be a good idea.\nIf there is no way to detect the right file with tmpfiles.d, then udev rules give more flexibility.","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":391,"context_line":"\t/* Parse the PCIe extended capability list and try to find"},{"line_number":392,"context_line":"\t * vendor specific header */"},{"line_number":393,"context_line":"\txlnx_pcie_xvc-\u003eoffset \u003d PCIE_EXT_CAP_LST;"},{"line_number":394,"context_line":"\twhile (xlnx_pcie_xvc-\u003eoffset \u003c\u003d PCI_CFG_SPACE_EXP_SIZE - 4 \u0026\u0026"},{"line_number":395,"context_line":"\t       xlnx_pcie_xvc-\u003eoffset \u003e\u003d PCIE_EXT_CAP_LST) {"},{"line_number":396,"context_line":"\t\terr \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, \u0026cap);"},{"line_number":397,"context_line":"\t\tif (err !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_cb433542","line":394,"updated":"2019-10-24 05:48:05.000000000","message":"What is the meaning of 4","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"5f477cf95687e85639cddfcce0573c66078a8975","unresolved":false,"context_lines":[{"line_number":391,"context_line":"\t/* Parse the PCIe extended capability list and try to find"},{"line_number":392,"context_line":"\t * vendor specific header */"},{"line_number":393,"context_line":"\txlnx_pcie_xvc-\u003eoffset \u003d PCIE_EXT_CAP_LST;"},{"line_number":394,"context_line":"\twhile (xlnx_pcie_xvc-\u003eoffset \u003c\u003d PCI_CFG_SPACE_EXP_SIZE - 4 \u0026\u0026"},{"line_number":395,"context_line":"\t       xlnx_pcie_xvc-\u003eoffset \u003e\u003d PCIE_EXT_CAP_LST) {"},{"line_number":396,"context_line":"\t\terr \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, \u0026cap);"},{"line_number":397,"context_line":"\t\tif (err !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_cb5a5522","line":394,"in_reply_to":"8e7fc396_cb433542","updated":"2019-10-24 06:48:16.000000000","message":"sizeof(cap) would probably be clearer. Thanks","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"510ccf3319d034281139a64db70f9ff709548097","unresolved":false,"context_lines":[{"line_number":391,"context_line":"\t/* Parse the PCIe extended capability list and try to find"},{"line_number":392,"context_line":"\t * vendor specific header */"},{"line_number":393,"context_line":"\txlnx_pcie_xvc-\u003eoffset \u003d PCIE_EXT_CAP_LST;"},{"line_number":394,"context_line":"\twhile (xlnx_pcie_xvc-\u003eoffset \u003c\u003d PCI_CFG_SPACE_EXP_SIZE - 4 \u0026\u0026"},{"line_number":395,"context_line":"\t       xlnx_pcie_xvc-\u003eoffset \u003e\u003d PCIE_EXT_CAP_LST) {"},{"line_number":396,"context_line":"\t\terr \u003d xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, \u0026cap);"},{"line_number":397,"context_line":"\t\tif (err !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_abbcb91b","line":394,"in_reply_to":"8e7fc396_cb5a5522","updated":"2019-10-24 15:46:21.000000000","message":"Done","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"6edf297b54026384e73f1345d4c5ebe6955e846a","unresolved":false,"context_lines":[{"line_number":418,"context_line":"\t}"},{"line_number":419,"context_line":"\tif ((xlnx_pcie_xvc-\u003eoffset \u003e PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||"},{"line_number":420,"context_line":"\t     xlnx_pcie_xvc-\u003eoffset \u003c PCIE_EXT_CAP_LST) {"},{"line_number":421,"context_line":"\t\tclose(xlnx_pcie_xvc-\u003efd);"},{"line_number":422,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":423,"context_line":"\t}"},{"line_number":424,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_ab46f952","line":421,"updated":"2019-10-24 05:48:05.000000000","message":"close can return error","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"5f477cf95687e85639cddfcce0573c66078a8975","unresolved":false,"context_lines":[{"line_number":418,"context_line":"\t}"},{"line_number":419,"context_line":"\tif ((xlnx_pcie_xvc-\u003eoffset \u003e PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||"},{"line_number":420,"context_line":"\t     xlnx_pcie_xvc-\u003eoffset \u003c PCIE_EXT_CAP_LST) {"},{"line_number":421,"context_line":"\t\tclose(xlnx_pcie_xvc-\u003efd);"},{"line_number":422,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":423,"context_line":"\t}"},{"line_number":424,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_ab5d991c","line":421,"in_reply_to":"8e7fc396_ab46f952","updated":"2019-10-24 06:48:16.000000000","message":"Good catch, will fix.","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"},{"author":{"_account_id":1001700,"name":"Moritz Fischer","email":"moritzf@google.com","username":"moritzf"},"change_message_id":"510ccf3319d034281139a64db70f9ff709548097","unresolved":false,"context_lines":[{"line_number":418,"context_line":"\t}"},{"line_number":419,"context_line":"\tif ((xlnx_pcie_xvc-\u003eoffset \u003e PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||"},{"line_number":420,"context_line":"\t     xlnx_pcie_xvc-\u003eoffset \u003c PCIE_EXT_CAP_LST) {"},{"line_number":421,"context_line":"\t\tclose(xlnx_pcie_xvc-\u003efd);"},{"line_number":422,"context_line":"\t\treturn ERROR_JTAG_INIT_FAILED;"},{"line_number":423,"context_line":"\t}"},{"line_number":424,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":13,"id":"8e7fc396_cbb9f52a","line":421,"in_reply_to":"8e7fc396_ab5d991c","updated":"2019-10-24 15:46:21.000000000","message":"On second look. This is already the error case and I\u0027m returning an error.","commit_id":"c95db5797ba6e8c178899fde0a29a7b4c8385c84"}]}