)]}'
{"src/target/cortex_m.c":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"e153fca1e4bcf38966414fd2292f5db0f38f3967","unresolved":false,"context_lines":[{"line_number":93,"context_line":"\t\tkeep_alive();"},{"line_number":94,"context_line":"\t}"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"\tretval \u003d mem_ap_read_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, value);"},{"line_number":97,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":98,"context_line":"\t\treturn retval;"},{"line_number":99,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8e7fc396_30957836","line":96,"updated":"2019-10-15 12:06:03.000000000","message":"Please move the read of DCRDR inside the loop so that once S_REGRDY is set, we don\u0027t need to do another atomic transfer to get the result even if no delay were needed.\n\nOf course the DHCSR read must be made queued also.","commit_id":"4d8b639f9f7f2a785ea626219680777e00ccfdb3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c7522d53cffafe811878dc6138303ee60ecd8626","unresolved":false,"context_lines":[{"line_number":93,"context_line":"\t\tkeep_alive();"},{"line_number":94,"context_line":"\t}"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"\tretval \u003d mem_ap_read_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, value);"},{"line_number":97,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":98,"context_line":"\t\treturn retval;"},{"line_number":99,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8e7fc396_f09e2059","line":96,"in_reply_to":"8e7fc396_30957836","updated":"2019-10-15 14:38:47.000000000","message":"What you say is correct. I will send a V2.\n\nBut I was planning to create an inline function similar to dap_dp_poll_register() for polling the AP registers. The function would replace the loop above with great improvement in code readability. Moving the read of DCRDR inside the loop breaks this simple case.\n\nMaybe this would be one of the few cases where the polling function would not apply!","commit_id":"4d8b639f9f7f2a785ea626219680777e00ccfdb3"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"ee89f011143c74980c6daa208404765ee7beba81","unresolved":false,"context_lines":[{"line_number":93,"context_line":"\t\tkeep_alive();"},{"line_number":94,"context_line":"\t}"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"\tretval \u003d mem_ap_read_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, value);"},{"line_number":97,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":98,"context_line":"\t\treturn retval;"},{"line_number":99,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8e7fc396_f0c5c042","line":96,"in_reply_to":"8e7fc396_f09e2059","updated":"2019-10-15 15:59:31.000000000","message":"Actually, it\u0027s a bug to read DCB_DHCSR in arbitrary places. All reads should go through a single place to be able to react to flags that auto-clear on read (e.g. S_RESET_ST) or that signal that actions needs to be taken (e.g. S_SLEEP).","commit_id":"4d8b639f9f7f2a785ea626219680777e00ccfdb3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3653e36580acff2c7c887762309af5efa0b15754","unresolved":false,"context_lines":[{"line_number":93,"context_line":"\t\tkeep_alive();"},{"line_number":94,"context_line":"\t}"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"\tretval \u003d mem_ap_read_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, value);"},{"line_number":97,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":98,"context_line":"\t\treturn retval;"},{"line_number":99,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8e7fc396_b0bf48a7","line":96,"in_reply_to":"8e7fc396_f0c5c042","updated":"2019-10-15 16:32:44.000000000","message":"The bits that get reset by a read are only the ST(icky) bits S_RESET_ST and S_RETIRE_ST. They are today supposed to be handled exclusively in poll().\nSome management is required.\nHere we need to keep the status of the sticky bits, then test and clear such status in poll().\n\nI disagree that S_SLEEP should be taken in consideration here, since we suppose to be already in a halted state.\nAnyway the S_SLEEP doesn\u0027t change after a read, so can be read again.","commit_id":"4d8b639f9f7f2a785ea626219680777e00ccfdb3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e1766d944bbc1d1ff4901fbf87a3d6dd57851f2","unresolved":false,"context_lines":[{"line_number":1651,"context_line":""},{"line_number":1652,"context_line":"\t\tcase ARMV7M_FPSCR:"},{"line_number":1653,"context_line":"\t\t\t/* Floating-point Status and Registers */"},{"line_number":1654,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRSR, 0x21);"},{"line_number":1655,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1656,"context_line":"\t\t\t\treturn retval;"},{"line_number":1657,"context_line":"\t\t\tretval \u003d target_read_u32(target, DCB_DCRDR, value);"},{"line_number":1658,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1659,"context_line":"\t\t\t\treturn retval;"},{"line_number":1660,"context_line":"\t\t\tLOG_DEBUG(\"load from FPSCR  value 0x%\" PRIx32, *value);"},{"line_number":1661,"context_line":"\t\t\tbreak;"},{"line_number":1662,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8e7fc396_30b25893","line":1659,"range":{"start_line":1654,"start_character":3,"end_line":1659,"end_character":18},"updated":"2019-10-18 16:34:35.000000000","message":"cortexm_dap_read_coreregister_u32() is not used here for unknown reason, so no S_REGRDY polling for FPSCR","commit_id":"95edf570075441d2404404e30082eedf6a0f8372"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e1766d944bbc1d1ff4901fbf87a3d6dd57851f2","unresolved":false,"context_lines":[{"line_number":1662,"context_line":""},{"line_number":1663,"context_line":"\t\tcase ARMV7M_S0 ... ARMV7M_S31:"},{"line_number":1664,"context_line":"\t\t\t/* Floating-point Status and Registers */"},{"line_number":1665,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);"},{"line_number":1666,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1667,"context_line":"\t\t\t\treturn retval;"},{"line_number":1668,"context_line":"\t\t\tretval \u003d target_read_u32(target, DCB_DCRDR, value);"},{"line_number":1669,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1670,"context_line":"\t\t\t\treturn retval;"},{"line_number":1671,"context_line":"\t\t\tLOG_DEBUG(\"load from FPU reg S%d  value 0x%\" PRIx32,"},{"line_number":1672,"context_line":"\t\t\t\t  (int)(num - ARMV7M_S0), *value);"},{"line_number":1673,"context_line":"\t\t\tbreak;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8e7fc396_50b7d481","line":1670,"range":{"start_line":1665,"start_character":3,"end_line":1670,"end_character":18},"updated":"2019-10-18 16:34:35.000000000","message":"and for all S0..31 regs no polling as well","commit_id":"95edf570075441d2404404e30082eedf6a0f8372"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e1766d944bbc1d1ff4901fbf87a3d6dd57851f2","unresolved":false,"context_lines":[{"line_number":1737,"context_line":""},{"line_number":1738,"context_line":"\t\tcase ARMV7M_FPSCR:"},{"line_number":1739,"context_line":"\t\t\t/* Floating-point Status and Registers */"},{"line_number":1740,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRDR, value);"},{"line_number":1741,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1742,"context_line":"\t\t\t\treturn retval;"},{"line_number":1743,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRSR, 0x21 | (1\u003c\u003c16));"},{"line_number":1744,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1745,"context_line":"\t\t\t\treturn retval;"},{"line_number":1746,"context_line":"\t\t\tLOG_DEBUG(\"write FPSCR value 0x%\" PRIx32, value);"},{"line_number":1747,"context_line":"\t\t\tbreak;"},{"line_number":1748,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8e7fc396_f0ab8019","line":1745,"range":{"start_line":1740,"start_character":3,"end_line":1745,"end_character":18},"updated":"2019-10-18 16:34:35.000000000","message":"Similar crap here...","commit_id":"95edf570075441d2404404e30082eedf6a0f8372"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e1766d944bbc1d1ff4901fbf87a3d6dd57851f2","unresolved":false,"context_lines":[{"line_number":1748,"context_line":""},{"line_number":1749,"context_line":"\t\tcase ARMV7M_S0 ... ARMV7M_S31:"},{"line_number":1750,"context_line":"\t\t\t/* Floating-point Status and Registers */"},{"line_number":1751,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRDR, value);"},{"line_number":1752,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1753,"context_line":"\t\t\t\treturn retval;"},{"line_number":1754,"context_line":"\t\t\tretval \u003d target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1\u003c\u003c16));"},{"line_number":1755,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1756,"context_line":"\t\t\t\treturn retval;"},{"line_number":1757,"context_line":"\t\t\tLOG_DEBUG(\"write FPU reg S%d  value 0x%\" PRIx32,"},{"line_number":1758,"context_line":"\t\t\t\t  (int)(num - ARMV7M_S0), value);"},{"line_number":1759,"context_line":"\t\t\tbreak;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8e7fc396_10a95c21","line":1756,"range":{"start_line":1751,"start_character":3,"end_line":1756,"end_character":18},"updated":"2019-10-18 16:34:35.000000000","message":"and here as well","commit_id":"95edf570075441d2404404e30082eedf6a0f8372"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"eef9be9a196695f43e80274fbfaf881f2b1bc90b","unresolved":false,"context_lines":[{"line_number":101,"context_line":"\t\t\treturn retval;"},{"line_number":102,"context_line":"\t\tif (cortex_m-\u003edcb_dhcsr \u0026 S_REGRDY)"},{"line_number":103,"context_line":"\t\t\tbreak;"},{"line_number":104,"context_line":"\t\tif (timeval_ms() \u003e then + 500) {"},{"line_number":105,"context_line":"\t\t\tLOG_ERROR(\"Timeout waiting for DCRDR transfer ready\");"},{"line_number":106,"context_line":"\t\t\treturn ERROR_TIMEOUT_REACHED;"},{"line_number":107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aedf27f1_38e9ed7b","line":104,"range":{"start_line":104,"start_character":28,"end_line":104,"end_character":31},"updated":"2021-05-01 22:53:52.000000000","message":"why not moving this magic value to a define, kind of DHCSR_S_REGRDY_TIMEOUT","commit_id":"33a23497fc5453b25de2bdac6b26098a46504608"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c8b37555910826b232b925009dd6c3d262efcbc7","unresolved":false,"context_lines":[{"line_number":101,"context_line":"\t\t\treturn retval;"},{"line_number":102,"context_line":"\t\tif (cortex_m-\u003edcb_dhcsr \u0026 S_REGRDY)"},{"line_number":103,"context_line":"\t\t\tbreak;"},{"line_number":104,"context_line":"\t\tif (timeval_ms() \u003e then + 500) {"},{"line_number":105,"context_line":"\t\t\tLOG_ERROR(\"Timeout waiting for DCRDR transfer ready\");"},{"line_number":106,"context_line":"\t\t\treturn ERROR_TIMEOUT_REACHED;"},{"line_number":107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aedf27f1_233d428b","line":104,"range":{"start_line":104,"start_character":28,"end_line":104,"end_character":31},"in_reply_to":"aedf27f1_38e9ed7b","updated":"2021-05-05 22:56:21.000000000","message":"Done","commit_id":"33a23497fc5453b25de2bdac6b26098a46504608"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"eef9be9a196695f43e80274fbfaf881f2b1bc90b","unresolved":false,"context_lines":[{"line_number":154,"context_line":"\t\t\treturn retval;"},{"line_number":155,"context_line":"\t\tif (cortex_m-\u003edcb_dhcsr \u0026 S_REGRDY)"},{"line_number":156,"context_line":"\t\t\tbreak;"},{"line_number":157,"context_line":"\t\tif (timeval_ms() \u003e then + 500) {"},{"line_number":158,"context_line":"\t\t\tLOG_ERROR(\"Timeout waiting for DCRDR transfer ready\");"},{"line_number":159,"context_line":"\t\t\treturn ERROR_TIMEOUT_REACHED;"},{"line_number":160,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aedf27f1_589151fa","line":157,"range":{"start_line":157,"start_character":28,"end_line":157,"end_character":31},"updated":"2021-05-01 22:53:52.000000000","message":"idem","commit_id":"33a23497fc5453b25de2bdac6b26098a46504608"}]}