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Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 09:53:22.000000000","message":"Patch Set 1: Code-Review+1","accounts_in_message":[],"_revision_number":1},{"id":"e153fca1e4bcf38966414fd2292f5db0f38f3967","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2019-10-15 12:06:03.000000000","message":"Patch Set 1:\n\n(1 comment)\n\nWe don\u0027t want to slow down the case where this isn\u0027t needed. Keeping the number of transfers down to a minimum is crucial.","accounts_in_message":[],"_revision_number":1},{"id":"96a9f65538ef5789486587e220e4b40eab22e47c","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 14:34:30.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"c7522d53cffafe811878dc6138303ee60ecd8626","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 14:38:47.000000000","message":"Patch Set 1:\n\n(1 comment)","accounts_in_message":[],"_revision_number":1},{"id":"3e4d141bf950f6f03f88fd24fd1516602d26e2ad","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 14:46:38.000000000","message":"Patch Set 2:\n\nMaybe I should send a V3.\nIn case of timeout, instead of returning ERROR_FAIL I should return ERROR_TIMEOUT_REACHED.","accounts_in_message":[],"_revision_number":2},{"id":"1430d76092700c476c22dbec26d1c398ff6d2757","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 14:50:04.000000000","message":"Uploaded patch set 3.","accounts_in_message":[],"_revision_number":3},{"id":"a511f3893dd389e51abf5ccdd433ccceca2829ba","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-10-15 14:50:05.000000000","message":"Patch Set 2: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/11451/ : ABORTED\n\nhttp://build.openocd.org/job/openocd-gerrit/12143/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"00bb070c0124a5f3f416298fa26e77875256344a","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2019-10-15 15:09:28.000000000","message":"Patch Set 3: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/12144/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/11452/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"39eee1687f1e292d257c0b483092f61f8d8b87fb","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 15:12:15.000000000","message":"Patch Set 3: Code-Review+1","accounts_in_message":[],"_revision_number":3},{"id":"ee89f011143c74980c6daa208404765ee7beba81","author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"real_author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"date":"2019-10-15 15:59:31.000000000","message":"Patch Set 1:\n\n(1 comment)","accounts_in_message":[],"_revision_number":1},{"id":"3653e36580acff2c7c887762309af5efa0b15754","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 16:32:44.000000000","message":"Patch Set 1:\n\n(1 comment)","accounts_in_message":[],"_revision_number":1},{"id":"de605e3701bf308894a061677f40dc862879c5db","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-15 16:32:52.000000000","message":"Patch Set 3: Code-Review-1","accounts_in_message":[],"_revision_number":3},{"id":"cbb24af67be3d2d845ea2b7f63f72e8206d5be92","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2019-10-16 15:18:43.000000000","message":"Patch Set 3:\n\nAntonio, it\u0027s nice that testing S_REGRDY does not require an extra atomic transfer. Unfortunately in the case of cortex_m_debug_entry()\nwhere all registers are read, the time seems me quite long anyway\n(183 ms on Cortex-M4F). I remembered a change sleeping almost a year in my git. I uploaded it now (my bad), please see http://openocd.zylin.com/5321\nTesting S_REGRDY would be much more complicated then.\n\nRegarding sticky bits of DHCSR: we should introduce an inline\ncortex_m_process_dhcsr_sticky() which accumulates (logic or) the values read from DHCSR. This will not prevent non-atomic ops and\ncortex_m_poll() can take an accumulated value.","accounts_in_message":[],"_revision_number":3},{"id":"d425bc74d8615ba893ee8f413a0d61496c9a1f03","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2019-10-16 15:28:52.000000000","message":"Patch Set 3:\n\n\u003e ... please see\n \u003e http://openocd.zylin.com/5321\n \u003e Testing S_REGRDY would be much more complicated then.\n\nNot much more complicated, but my idea to have something simple as dap_dp_poll_register() will not work there either.\n\n \u003e Regarding sticky bits of DHCSR: we should introduce an inline\n \u003e cortex_m_process_dhcsr_sticky() which accumulates (logic or) the\n \u003e values read from DHCSR. This will not prevent non-atomic ops and\n \u003e cortex_m_poll() can take an accumulated value.\n\nYes, it\u0027s what I\u0027m trying to do. Only the sticky bits should be accumulated, and would be responsibility of the code that use the sticky to clear them.","accounts_in_message":[],"_revision_number":3},{"id":"5e1766d944bbc1d1ff4901fbf87a3d6dd57851f2","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2019-10-18 16:34:35.000000000","message":"Patch Set 3:\n\n(4 comments)","accounts_in_message":[],"_revision_number":3},{"id":"f98de7cb707654c0b103ffa2c8cc4fb5044720ae","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2021-04-22 19:07:55.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"7332a1f14bcd47b06138af691215f4220eeb9fe6","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2021-04-22 19:13:03.000000000","message":"Patch Set 4:\n\nAdded a call to cortex_m_cumulate_dhcsr_sticky() and rebased","accounts_in_message":[],"_revision_number":4},{"id":"abe189dcf3f2fe66b80c59df7bad0610c395889a","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-04-22 19:39:49.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14405/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13659/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"eef9be9a196695f43e80274fbfaf881f2b1bc90b","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-05-01 22:53:52.000000000","message":"Patch Set 4:\n\n(2 comments)","accounts_in_message":[],"_revision_number":4},{"id":"3a7b5fd6bf4de0c8c2f64bcc4a1d24ea938997d4","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2021-05-02 03:41:48.000000000","message":"Patch Set 4:\n\n\u003e (2 comments)\n \u003e why not moving this magic value to a define, kind of DHCSR_S_REGRDY_TIMEOUT\n\nMakes sense.\nAntonio, do you want to address this? It\u0027s your patch anyway ;-)","accounts_in_message":[],"_revision_number":4},{"id":"afbb878eaf5fb2cf7618c69bfddcaa5f629865b7","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-05-05 22:55:10.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"c8b37555910826b232b925009dd6c3d262efcbc7","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-05-05 22:56:21.000000000","message":"Patch Set 4:\n\n(1 comment)\n\nI have also added two calls to cortex_m_cumulate_dhcsr_sticky()","accounts_in_message":[],"_revision_number":4},{"id":"1b07deae3b4e3f61b3a491a2c7964244850db61e","author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"real_author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"date":"2021-05-05 23:14:07.000000000","message":"Patch Set 4:\n\n\u003e (1 comment)\n \u003e \n \u003e I have also added two calls to cortex_m_cumulate_dhcsr_sticky()\n\nOpps, I probably submitted PS 4 as a pure rebase and these calls got lost... or was it mr Alzheimer?","accounts_in_message":[],"_revision_number":4},{"id":"ebfe7bef6645f8ae5ddf88445b216ca8f07c7a4b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-05-05 23:26:33.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14461/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13715/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"fcf5d3a0de7471981929c4b2b4f7e01525d5badc","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-05-06 21:42:49.000000000","message":"Patch Set 5: Code-Review+1","accounts_in_message":[],"_revision_number":5},{"id":"04288c9c01ddc39c16f72a3b3855989ef59f6b6e","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-05-07 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causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\n"}},"2bdf1769d31ffb11c205a0493bf37f8743a3d145":{"kind":"REWORK","_number":5,"created":"2021-05-05 22:55:10.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/19/5319/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/5 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e0abf4015f4bce67dc5ca3275d472fd6b24f00a7","subject":"target/cortex_m: cumulate DHCSR sticky bits"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2021-05-05 22:47:39.000000000","tz":120},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\n"}},"835dde8b99359f00aba077e75f790b7eaec05bb1":{"kind":"REWORK","_number":6,"created":"2021-11-08 16:02:57.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/19/5319/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/6 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"fc71bf0108d29c3b8bd07b3a193076a8f0f35ecf","subject":"target/cortex_m: cumulate DHCSR sticky bits"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2021-11-08 15:59:23.000000000","tz":60},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\n"}},"65d7629183288595177301ce262dac4ba716618b":{"kind":"REWORK","_number":7,"created":"2021-11-18 21:08:37.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/19/5319/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/7 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"0dcf95c7171b702d70ec326f8c1a63cbc9255b6f","subject":"target/cortex_m: cumulate DHCSR sticky bits"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2021-11-18 21:08:37.000000000","tz":0},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\nReviewed-on: https://review.openocd.org/c/openocd/+/5319\nTested-by: jenkins\nReviewed-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"4d8b639f9f7f2a785ea626219680777e00ccfdb3":{"kind":"REWORK","_number":1,"created":"2019-10-15 09:28:51.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/19/5319/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/1 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"3a50bb46dc084999f6f7aee8913858ccced49db4","subject":"Update FTDI C232HM cfg, and add two new cfgs from cable modem research"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-15 09:23:41.000000000","tz":120},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\n"}},"b5cd860dc4a101d5116313da065054d20216b05e":{"kind":"REWORK","_number":2,"created":"2019-10-15 14:34:30.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/19/5319/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/2 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"3a50bb46dc084999f6f7aee8913858ccced49db4","subject":"Update FTDI C232HM cfg, and add two new cfgs from cable modem research"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-15 14:31:41.000000000","tz":120},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\n"}},"95edf570075441d2404404e30082eedf6a0f8372":{"kind":"REWORK","_number":3,"created":"2019-10-15 14:50:04.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/19/5319/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/19/5319/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/3 \u0026\u0026 git checkout -b change-5319 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/19/5319/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/19/5319/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"3a50bb46dc084999f6f7aee8913858ccced49db4","subject":"Update FTDI C232HM cfg, and add two new cfgs from cable modem research"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-14 17:03:48.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2019-10-15 14:47:32.000000000","tz":120},"subject":"cortex_m: poll S_REGRDY on register r/w","message":"cortex_m: poll S_REGRDY on register r/w\n\nAccordingly to arm documentation [1], chapter C1.6.4, the\noperation to read/write from/to core registers can require time,\nand the specific flag DHCSR.S_REGRDY has to be polled to verify\nthat the operation has been completed.\nThe lack of check on S_REGRDY causes OpenOCD to fail handling\ncorrectly the core registers on a Cortex-M4 emulated in a slow\nFPGA, and it could also fail on devices clocked at very low speed\nwhile using a fast adapter.\n\nPoll S_REGRDY as specified in [1] while either reading or writing\nthe core registers.\nA timeout of 0.5s is added. This could still be too small in some\nextremely slow cases, but at least now we log the timeout event,\nwhich can help tracking down such odd issue.\nDuring register read include in the polling loop the read of DCRSR\nand to flush the JTAG queue only once.\nDuring register write, relax the write in DCRSR by removing the\natomicity that is now useless since followed by the atomic read to\nS_REGRDY.\nDuring register read include the read of DCRSR inside the polling\nloop to relax the read of S_REGRDY since followed by the atomic\nread to DCRSR.\n\nThis change has the drawback of adding other transfers to the\nadapter while reading/writing the registers, so it is expected to\nintroduce some speed degradation during step-by-step.\n\n[1] DDI0403E - \"ARMv7-M Architecture Reference Manual\"\n\nChange-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\n"}}},"requirements":[],"submit_records":[{"status":"CLOSED","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dCustom-Rule","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dCustom-Rule"],"failing_atoms":[]}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dCustom-Rule","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dCustom-Rule"],"failing_atoms":[]}}]}
