)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"7e90c1f4f397db79666cbe43a40e50f200e4d7d3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"efac36dd_de9c34df","updated":"2021-11-08 09:26:08.000000000","message":"is there any chance to continue working on this ?","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"035621bbf5414a07450243693cbbb6aa927978f6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"be81f5ff_0dd2c053","in_reply_to":"efac36dd_de9c34df","updated":"2021-11-08 16:06:49.000000000","message":"Definitely YES 😊\nPlease test the new series.\nI tested just very quickly... but code changes were marginal.","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"3813bd18bd77898fa751b0f6124c430529b3820d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"de471246_9da0fcb9","updated":"2021-11-08 17:41:58.000000000","message":"Seems to work fine and shaves 6-7 ms off each debug entry in my case.\n\nSee my followup 6678 for adaptive slow/fast selection, even though I\u0027m not sure it\u0027s particularly likely that someone will end up in the slow path in the first place (has someone managed to provoke a target to actually read S_REGRDY\u003d\u003d0?).","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7068998dddc1f8fe96326d2767686fc477c69c51","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"637d0e4a_3b78121a","in_reply_to":"de471246_9da0fcb9","updated":"2021-11-08 19:42:21.000000000","message":"IMO there is no chance to get S_REGRDY \u003d\u003d 0 on normal Cortex-M3,4,7,33: I was trying hard with very slow CPU clk and got just SWD WAIT and never S_REGRDY. So if the timeout is possible at all it can happen on such special hw like Cortex-M1","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"}],"src/target/cortex_m.c":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"574467a2c51a6b62728eb4bd3e4490420be9be7c","unresolved":false,"context_lines":[{"line_number":115,"context_line":"\tARMV7M_CONTROL_FAULTMASK_BASEPRI_PRIMASK \u003d 0x14,"},{"line_number":116,"context_line":"\tARMV7M_REGSEL_FPSCR \u003d 0x21,"},{"line_number":117,"context_line":"\tARMV7M_REGSEL_S0 \u003d 0x40,"},{"line_number":118,"context_line":"};"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"static int cortex_m_dap_queue_reg_read(struct target *target, int regnum,"},{"line_number":121,"context_line":"\t\tuint32_t *reg_value, uint32_t *dhcsr)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_f042a0b1","line":118,"updated":"2019-10-17 08:17:32.000000000","message":"This duplicates the register-to-selector mapping which surely must be available somewhere else in OpenOCD as well?","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c1e0be8c9f29c912a49866b6c332899718bcccf1","unresolved":false,"context_lines":[{"line_number":115,"context_line":"\tARMV7M_CONTROL_FAULTMASK_BASEPRI_PRIMASK \u003d 0x14,"},{"line_number":116,"context_line":"\tARMV7M_REGSEL_FPSCR \u003d 0x21,"},{"line_number":117,"context_line":"\tARMV7M_REGSEL_S0 \u003d 0x40,"},{"line_number":118,"context_line":"};"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"static int cortex_m_dap_queue_reg_read(struct target *target, int regnum,"},{"line_number":121,"context_line":"\t\tuint32_t *reg_value, uint32_t *dhcsr)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"aedf27f1_f554d058","line":118,"in_reply_to":"8e7fc396_106e3c2b","updated":"2021-04-23 07:10:05.000000000","message":"Done","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":115,"context_line":"\tARMV7M_CONTROL_FAULTMASK_BASEPRI_PRIMASK \u003d 0x14,"},{"line_number":116,"context_line":"\tARMV7M_REGSEL_FPSCR \u003d 0x21,"},{"line_number":117,"context_line":"\tARMV7M_REGSEL_S0 \u003d 0x40,"},{"line_number":118,"context_line":"};"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"static int cortex_m_dap_queue_reg_read(struct target *target, int regnum,"},{"line_number":121,"context_line":"\t\tuint32_t *reg_value, uint32_t *dhcsr)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_106e3c2b","line":118,"in_reply_to":"8e7fc396_f042a0b1","updated":"2019-10-17 21:08:10.000000000","message":"The mapping is in cortex_m_load_core_reg_u32() and cortex_m_store_core_reg_u32() as magic numbers in the switch/case. I\u0027m planning to use the newly defined selectors there as well, but not in this patch.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"574467a2c51a6b62728eb4bd3e4490420be9be7c","unresolved":false,"context_lines":[{"line_number":185,"context_line":"\t\t\t\t\u0026fpscr, \u0026dhcsr[dhcsr_idx++]);"},{"line_number":186,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":187,"context_line":"\t\t\treturn retval;"},{"line_number":188,"context_line":"\t}"},{"line_number":189,"context_line":""},{"line_number":190,"context_line":"\tassert(dhcsr_idx \u003c\u003d ARRAY_SIZE(dhcsr));"},{"line_number":191,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_90348c48","line":188,"updated":"2019-10-17 08:17:32.000000000","message":"Can\u0027t we keep everything in one loop? The reads are all the same, would probably be clearer if we have just one loop over a single data structure that keeps track of each register; its index (reg pointer?); its selector; the value read and the corresponding dhcsr.\n\nReally, that data structure shouldn\u0027t need to be duplicated here, it should be part of the armv7m struct instead of using the misfit that is the \"generic ARM register list\". And populated at examine time with the exact features that are available, FP regs only if they exist etc. Well, room for improvement.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":185,"context_line":"\t\t\t\t\u0026fpscr, \u0026dhcsr[dhcsr_idx++]);"},{"line_number":186,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":187,"context_line":"\t\t\treturn retval;"},{"line_number":188,"context_line":"\t}"},{"line_number":189,"context_line":""},{"line_number":190,"context_line":"\tassert(dhcsr_idx \u003c\u003d ARRAY_SIZE(dhcsr));"},{"line_number":191,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_b07ae8e5","line":188,"in_reply_to":"8e7fc396_90348c48","updated":"2019-10-17 21:08:10.000000000","message":"One loop? Sure we can. But to achieve this we need a register list with 1:1 transformation to accessible registers. Now we have 4 8-bit registers Control/Faultmask/Basepri/Primask in the list and we read/write it as 1 word. Similarly we need to convert S0..32 FP registers to D0..16 reg in the list.\n\nThe existing register list is exposed to gdb, so I don\u0027t think there is \"room for improvement\"","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c1e0be8c9f29c912a49866b6c332899718bcccf1","unresolved":false,"context_lines":[{"line_number":185,"context_line":"\t\t\t\t\u0026fpscr, \u0026dhcsr[dhcsr_idx++]);"},{"line_number":186,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":187,"context_line":"\t\t\treturn retval;"},{"line_number":188,"context_line":"\t}"},{"line_number":189,"context_line":""},{"line_number":190,"context_line":"\tassert(dhcsr_idx \u003c\u003d ARRAY_SIZE(dhcsr));"},{"line_number":191,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":2,"id":"aedf27f1_9551c467","line":188,"in_reply_to":"8e7fc396_b07ae8e5","updated":"2021-04-23 07:10:05.000000000","message":"Done","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"574467a2c51a6b62728eb4bd3e4490420be9be7c","unresolved":false,"context_lines":[{"line_number":203,"context_line":""},{"line_number":204,"context_line":"\tbool not_ready \u003d false;"},{"line_number":205,"context_line":"\tfor (i \u003d 0; i \u003c dhcsr_idx; i++) {"},{"line_number":206,"context_line":"\t\tif ((dhcsr[i] \u0026 S_REGRDY) \u003d\u003d 0) {"},{"line_number":207,"context_line":"\t\t\tnot_ready \u003d true;"},{"line_number":208,"context_line":"\t\t\tLOG_DEBUG(\"Register %u was not ready during fast read\", i);"},{"line_number":209,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_503ef427","line":206,"updated":"2019-10-17 08:17:32.000000000","message":"Would need to dispatch any \"Read once\" flags set here to some common handling.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":203,"context_line":""},{"line_number":204,"context_line":"\tbool not_ready \u003d false;"},{"line_number":205,"context_line":"\tfor (i \u003d 0; i \u003c dhcsr_idx; i++) {"},{"line_number":206,"context_line":"\t\tif ((dhcsr[i] \u0026 S_REGRDY) \u003d\u003d 0) {"},{"line_number":207,"context_line":"\t\t\tnot_ready \u003d true;"},{"line_number":208,"context_line":"\t\t\tLOG_DEBUG(\"Register %u was not ready during fast read\", i);"},{"line_number":209,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_d07764fc","line":206,"in_reply_to":"8e7fc396_503ef427","updated":"2019-10-17 21:08:10.000000000","message":"Yes, I\u0027m aware of it.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c1e0be8c9f29c912a49866b6c332899718bcccf1","unresolved":false,"context_lines":[{"line_number":203,"context_line":""},{"line_number":204,"context_line":"\tbool not_ready \u003d false;"},{"line_number":205,"context_line":"\tfor (i \u003d 0; i \u003c dhcsr_idx; i++) {"},{"line_number":206,"context_line":"\t\tif ((dhcsr[i] \u0026 S_REGRDY) \u003d\u003d 0) {"},{"line_number":207,"context_line":"\t\t\tnot_ready \u003d true;"},{"line_number":208,"context_line":"\t\t\tLOG_DEBUG(\"Register %u was not ready during fast read\", i);"},{"line_number":209,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"aedf27f1_b54e48c3","line":206,"in_reply_to":"8e7fc396_d07764fc","updated":"2021-04-23 07:10:05.000000000","message":"Done","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"574467a2c51a6b62728eb4bd3e4490420be9be7c","unresolved":false,"context_lines":[{"line_number":211,"context_line":""},{"line_number":212,"context_line":"\tif (not_ready) {"},{"line_number":213,"context_line":"\t\t/* Any register was not ready,"},{"line_number":214,"context_line":"\t\t * fall back to slow read with S_REGRDY polling */"},{"line_number":215,"context_line":"\t\treturn ERROR_TIMEOUT_REACHED;"},{"line_number":216,"context_line":"\t}"},{"line_number":217,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_3039f83e","line":214,"updated":"2019-10-17 08:17:32.000000000","message":"Some registers may have been read, maybe not throw that data away? Maybe not so relevant since this will as it stands only fail once per target. But checking dhcsr could be integrated in the loop(s) below that sets valid if OK, otherwise returns. Again, would be easier if we could actually have one \"loop over all registers\"; as of now this idea doesn\u0027t make much sense.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":211,"context_line":""},{"line_number":212,"context_line":"\tif (not_ready) {"},{"line_number":213,"context_line":"\t\t/* Any register was not ready,"},{"line_number":214,"context_line":"\t\t * fall back to slow read with S_REGRDY polling */"},{"line_number":215,"context_line":"\t\treturn ERROR_TIMEOUT_REACHED;"},{"line_number":216,"context_line":"\t}"},{"line_number":217,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_70645046","line":214,"in_reply_to":"8e7fc396_3039f83e","updated":"2019-10-17 21:08:10.000000000","message":"Oh yes, maybe some hw can read all but FP regs or so. But honestly I think the register not ready case is very very rare. OpenOCD has been running for years without the check...","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"8dea5685f8e430d17f797e75cab10f82eec7bef2","unresolved":false,"context_lines":[{"line_number":697,"context_line":""},{"line_number":698,"context_line":"\t\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":699,"context_line":"\t\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":700,"context_line":"\t\t\tif (!r-\u003evalid)"},{"line_number":701,"context_line":"\t\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":702,"context_line":"\t\t}"},{"line_number":703,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_b04c28e6","line":700,"updated":"2019-10-17 08:26:35.000000000","message":"By the way, why is the current loop checking valid? Shouldn\u0027t *all* register caches be invalid upon debug entry? Any register may have changed?","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c1e0be8c9f29c912a49866b6c332899718bcccf1","unresolved":false,"context_lines":[{"line_number":697,"context_line":""},{"line_number":698,"context_line":"\t\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":699,"context_line":"\t\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":700,"context_line":"\t\t\tif (!r-\u003evalid)"},{"line_number":701,"context_line":"\t\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":702,"context_line":"\t\t}"},{"line_number":703,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"aedf27f1_55c35c0a","line":700,"in_reply_to":"8e7fc396_305ed87c","updated":"2021-04-23 07:10:05.000000000","message":"Done","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":697,"context_line":""},{"line_number":698,"context_line":"\t\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":699,"context_line":"\t\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":700,"context_line":"\t\t\tif (!r-\u003evalid)"},{"line_number":701,"context_line":"\t\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":702,"context_line":"\t\t}"},{"line_number":703,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_305ed87c","line":700,"in_reply_to":"8e7fc396_b04c28e6","updated":"2019-10-17 21:08:10.000000000","message":"Good point. This part is copied from original code, this is the only reason. I do not see any meaningful usecase of the valid reg cache on debug entry. I\u0027ll change it to unconditional read to fit fast read","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b00e988190d5e5aeb848ec62c92714f78393002a","unresolved":false,"context_lines":[{"line_number":683,"context_line":"\t\treturn retval;"},{"line_number":684,"context_line":""},{"line_number":685,"context_line":""},{"line_number":686,"context_line":"\tif (!cortex_m-\u003eslow_register_read) {"},{"line_number":687,"context_line":"\t\tretval \u003d cortex_m_dap_read_all_regs(target);"},{"line_number":688,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":689,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":690,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":691,"context_line":"\t\t}"},{"line_number":692,"context_line":"\t}"},{"line_number":693,"context_line":""},{"line_number":694,"context_line":"\tif (cortex_m-\u003eslow_register_read) {"},{"line_number":695,"context_line":"\t\tint num_regs \u003d arm-\u003ecore_cache-\u003enum_regs;"},{"line_number":696,"context_line":"\t\tint i;"},{"line_number":697,"context_line":""},{"line_number":698,"context_line":"\t\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":699,"context_line":"\t\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":700,"context_line":"\t\t\tif (!r-\u003evalid)"},{"line_number":701,"context_line":"\t\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":702,"context_line":"\t\t}"},{"line_number":703,"context_line":"\t}"},{"line_number":704,"context_line":""},{"line_number":705,"context_line":"\tr \u003d arm-\u003ecpsr;"},{"line_number":706,"context_line":"\txPSR \u003d buf_get_u32(r-\u003evalue, 0, 32);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_701690ae","line":703,"range":{"start_line":686,"start_character":0,"end_line":703,"end_character":2},"updated":"2019-10-17 09:35:07.000000000","message":"All the lines 686-703 could be moved inside cortex_m_da_read_all_regs().\nI mean, the selection slow/fast and the different way to read regs should be fully contained in one function, not expanded here.\nHere only call the function and check return error code.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f61285adb61f9575f345654bf3c741bf0634b00","unresolved":false,"context_lines":[{"line_number":683,"context_line":"\t\treturn retval;"},{"line_number":684,"context_line":""},{"line_number":685,"context_line":""},{"line_number":686,"context_line":"\tif (!cortex_m-\u003eslow_register_read) {"},{"line_number":687,"context_line":"\t\tretval \u003d cortex_m_dap_read_all_regs(target);"},{"line_number":688,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":689,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":690,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":691,"context_line":"\t\t}"},{"line_number":692,"context_line":"\t}"},{"line_number":693,"context_line":""},{"line_number":694,"context_line":"\tif (cortex_m-\u003eslow_register_read) {"},{"line_number":695,"context_line":"\t\tint num_regs \u003d arm-\u003ecore_cache-\u003enum_regs;"},{"line_number":696,"context_line":"\t\tint i;"},{"line_number":697,"context_line":""},{"line_number":698,"context_line":"\t\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":699,"context_line":"\t\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":700,"context_line":"\t\t\tif (!r-\u003evalid)"},{"line_number":701,"context_line":"\t\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":702,"context_line":"\t\t}"},{"line_number":703,"context_line":"\t}"},{"line_number":704,"context_line":""},{"line_number":705,"context_line":"\tr \u003d arm-\u003ecpsr;"},{"line_number":706,"context_line":"\txPSR \u003d buf_get_u32(r-\u003evalue, 0, 32);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_5063543b","line":703,"range":{"start_line":686,"start_character":0,"end_line":703,"end_character":2},"in_reply_to":"8e7fc396_701690ae","updated":"2019-10-17 21:08:10.000000000","message":"Ok, I\u0027ll rename cortex_m_dap_read_all_regs() to cortex_m_fast_read_all_regs(). And lines 698-702 is the original code so I didn\u0027t refactor it to keep the change minimal.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"766a589bcc9c5808adbcf52707b9b83663571964","unresolved":false,"context_lines":[{"line_number":571,"context_line":""},{"line_number":572,"context_line":"\t/* Examine target state and mode"},{"line_number":573,"context_line":"\t * First load register accessible through core debug port */"},{"line_number":574,"context_line":"\tint num_regs \u003d arm-\u003ecore_cache-\u003enum_regs;"},{"line_number":575,"context_line":""},{"line_number":576,"context_line":"\tfor (i \u003d 0; i \u003c num_regs; i++) {"},{"line_number":577,"context_line":"\t\tr \u003d \u0026armv7m-\u003earm.core_cache-\u003ereg_list[i];"},{"line_number":578,"context_line":"\t\tif (!r-\u003evalid)"},{"line_number":579,"context_line":"\t\t\tarm-\u003eread_core_reg(target, r, i, ARM_MODE_ANY);"},{"line_number":580,"context_line":"\t}"},{"line_number":581,"context_line":""},{"line_number":582,"context_line":"\tr \u003d arm-\u003ecpsr;"},{"line_number":583,"context_line":"\txPSR \u003d buf_get_u32(r-\u003evalue, 0, 32);"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"aedf27f1_a379322c","side":"PARENT","line":580,"range":{"start_line":574,"start_character":1,"end_line":580,"end_character":2},"updated":"2021-05-07 11:14:29.000000000","message":"BTW, a minor rebase is needed due to line 578.\nI was wondering why we are not checking if the register is still valid before reading it, in both slow and fast methods.\nno harm, but it may introduce unnecessary reads ...","commit_id":"33a23497fc5453b25de2bdac6b26098a46504608"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"43150fc8cee87218089061777527e00f6a7b713e","unresolved":false,"context_lines":[{"line_number":732,"context_line":"\t\tretval \u003d cortex_m_fast_read_all_regs(target);"},{"line_number":733,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":734,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":735,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":736,"context_line":"\t\t}"},{"line_number":737,"context_line":"\t}"},{"line_number":738,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":5,"id":"aedf27f1_a3c13285","line":735,"updated":"2021-05-05 22:34:38.000000000","message":"This could be a LOG_WARNING() with a more informative message.\nYour adapter is running too fast for the current CPU speed.\nWe can suggest user to decrease the JTAG/SWD speed to avoid being too fast in the read and \"hopefully\" being able to use the fast mode. A crap tradeoff!\nBut no way to reset the flag, openocd has to be restarted!","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c100dbc3594726a1cfe38d535c9572d3ea3ba0be","unresolved":false,"context_lines":[{"line_number":732,"context_line":"\t\tretval \u003d cortex_m_fast_read_all_regs(target);"},{"line_number":733,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":734,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":735,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":736,"context_line":"\t\t}"},{"line_number":737,"context_line":"\t}"},{"line_number":738,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":5,"id":"aedf27f1_63010ab9","line":735,"in_reply_to":"aedf27f1_835f4ee8","updated":"2021-05-06 04:40:22.000000000","message":"Well to be precise 5319 does not add latency on adapters capable of queuing at least 1 write and 2 reads if the communication turnaround is the timing bottleneck (typical on USB FS). On the other hand the impact to a local bitbang could be huge - and no speed gained from this change! Considering this I admit we need an option to tune register reading, including possibility to drop S_REGRDY polling at all.\nYes, let\u0027s merge this one as is.","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"fc1d93044669112718fb70368d414da9c802df60","unresolved":false,"context_lines":[{"line_number":732,"context_line":"\t\tretval \u003d cortex_m_fast_read_all_regs(target);"},{"line_number":733,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":734,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":735,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":736,"context_line":"\t\t}"},{"line_number":737,"context_line":"\t}"},{"line_number":738,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":5,"id":"aedf27f1_e3465a26","line":735,"in_reply_to":"aedf27f1_a3c13285","updated":"2021-05-05 23:03:52.000000000","message":"We should not forget that \"slow register read\" has been a standard since OpenOCD origin and nobody complained (except me).\nAlso AFIAK there is no chance to get S_REGRDY \u003d\u003d 0 on normal Cortex-M: I was trying hard and got just SWD WAIT and never S_REGRDY. So if the timeout is possible on such specialities like Cortex-M1 then we can take it easy.","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"96aa61f83bf3d28203989e5bae7ba10df721d18f","unresolved":false,"context_lines":[{"line_number":732,"context_line":"\t\tretval \u003d cortex_m_fast_read_all_regs(target);"},{"line_number":733,"context_line":"\t\tif (retval \u003d\u003d ERROR_TIMEOUT_REACHED) {"},{"line_number":734,"context_line":"\t\t\tcortex_m-\u003eslow_register_read \u003d true;"},{"line_number":735,"context_line":"\t\t\tLOG_DEBUG(\"Switched to slow register read\");"},{"line_number":736,"context_line":"\t\t}"},{"line_number":737,"context_line":"\t}"},{"line_number":738,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":5,"id":"aedf27f1_835f4ee8","line":735,"in_reply_to":"aedf27f1_e3465a26","updated":"2021-05-05 23:20:10.000000000","message":"yes, but the new polling in 5319 adds extra latency.\nLet\u0027s go with this for the moment.","commit_id":"d1a0b13a0d3473c1764db004be86efa9bcdde2b5"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"6300ad1a777d69189f9374fcfce3af4bcfa77971","unresolved":true,"context_lines":[{"line_number":299,"context_line":""},{"line_number":300,"context_line":"\tif (target-\u003edbg_msg_enabled) {"},{"line_number":301,"context_line":"\t\t/* restore DCB_DCRDR - this needs to be in a separate"},{"line_number":302,"context_line":"\t\t * transaction otherwise the emulated DCC channel breaks */"},{"line_number":303,"context_line":"\t\tretval \u003d mem_ap_write_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, dcrdr);"},{"line_number":304,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":305,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"dd89c2fa_4713c757","line":302,"updated":"2021-11-08 22:15:45.000000000","message":"why \"needs to be in a separate transfer\"?\nBecause dap_run() above can return error before last operation that set DCRDR and then left it dirty?\nIf that is the reason, then we can add it non-atomic in the former big transfer, and if dap_run() return error we run this atomic again for safety","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1dc87da35485995be2e73fa86f8cf9fb865724c9","unresolved":false,"context_lines":[{"line_number":299,"context_line":""},{"line_number":300,"context_line":"\tif (target-\u003edbg_msg_enabled) {"},{"line_number":301,"context_line":"\t\t/* restore DCB_DCRDR - this needs to be in a separate"},{"line_number":302,"context_line":"\t\t * transaction otherwise the emulated DCC channel breaks */"},{"line_number":303,"context_line":"\t\tretval \u003d mem_ap_write_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, dcrdr);"},{"line_number":304,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":305,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8b066d05_669946e8","line":302,"in_reply_to":"7b769ea3_4bd01831","updated":"2021-11-10 17:46:27.000000000","message":"Seems to be clear:\n\nhttps://review.openocd.org/gitweb?p\u003dopenocd.git;a\u003dblobdiff;f\u003dsrc/target/cortex_m3.c;h\u003d5f5287ade5f0af94b53ed8607a1e60f2a2ae8ecc;hp\u003ddf00fc19e9ec4fb3e9f64d3b9603311ea58c3b94;hb\u003dfbf775c0b72fcc212962f725525673ab253a0883;hpb\u003da41725c788c21acac563e9512b00f4226cb8214b\n\nBefore this change both\n  mem_ap_read_u32(swjdp, DCB_DCRDR, \u0026dcrdr);\n\nand\n  mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);\n\nwere serviced in (possibly) one queue run. So dcrdr value was set *after* mem_ap_write and therefore mem_ap_write queued an uninitialised value.\n\nIMO no further optimization possible.","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0cc1ff5a213f66c5b2d53df319fe123a9834acbe","unresolved":true,"context_lines":[{"line_number":299,"context_line":""},{"line_number":300,"context_line":"\tif (target-\u003edbg_msg_enabled) {"},{"line_number":301,"context_line":"\t\t/* restore DCB_DCRDR - this needs to be in a separate"},{"line_number":302,"context_line":"\t\t * transaction otherwise the emulated DCC channel breaks */"},{"line_number":303,"context_line":"\t\tretval \u003d mem_ap_write_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, dcrdr);"},{"line_number":304,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":305,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"7b769ea3_4bd01831","line":302,"in_reply_to":"8570b4e6_c1404ed4","updated":"2021-11-10 16:58:08.000000000","message":"Origin of the comment is even older,\nhttps://review.openocd.org/gitweb?p\u003dopenocd.git;a\u003dcommitdiff;h\u003d0fe2a5435a78ac32eddc2398cc95759c2211ea04\nfile src/target/cortex_swjdp.c line 616\n\nCode was added here\nhttps://review.openocd.org/gitweb?p\u003dopenocd.git;a\u003dcommitdiff;h\u003d68b97e4b5c40a70b42dc2a970f1b90b9a3e9f13d\nbut commit message doesn\u0027t say anything\n\nI propose to keep this patch as is, then with a separate patch merge the optimization. If there is a regression, the second patch can be reverted","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"24e37933cd7628312c0472564e9f103aa3834b30","unresolved":true,"context_lines":[{"line_number":299,"context_line":""},{"line_number":300,"context_line":"\tif (target-\u003edbg_msg_enabled) {"},{"line_number":301,"context_line":"\t\t/* restore DCB_DCRDR - this needs to be in a separate"},{"line_number":302,"context_line":"\t\t * transaction otherwise the emulated DCC channel breaks */"},{"line_number":303,"context_line":"\t\tretval \u003d mem_ap_write_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, dcrdr);"},{"line_number":304,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":305,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8570b4e6_c1404ed4","line":302,"in_reply_to":"b05c737f_9ddbc2b3","updated":"2021-11-10 10:04:34.000000000","message":"The code incl. the comment is not changed by 1848, just reorganized. The origin seems to be 178b5d072e2bd2038fc9065b9722da296e6f5e16 and I have no idea why that would be necessary.","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1387154f244f56e46dca6ce09dbf50b24b64d33b","unresolved":true,"context_lines":[{"line_number":299,"context_line":""},{"line_number":300,"context_line":"\tif (target-\u003edbg_msg_enabled) {"},{"line_number":301,"context_line":"\t\t/* restore DCB_DCRDR - this needs to be in a separate"},{"line_number":302,"context_line":"\t\t * transaction otherwise the emulated DCC channel breaks */"},{"line_number":303,"context_line":"\t\tretval \u003d mem_ap_write_atomic_u32(armv7m-\u003edebug_ap, DCB_DCRDR, dcrdr);"},{"line_number":304,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":305,"context_line":"\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"b05c737f_9ddbc2b3","line":302,"in_reply_to":"dd89c2fa_4713c757","updated":"2021-11-09 09:24:09.000000000","message":"This comment is from original code, I just believed without digging into depth.\nhttps://review.openocd.org/c/openocd/+/1848\n\nAndreas, can you give us more details?\n\nWhatever the reason is this change just preserves the old DCC code so we can eventually address it in a new patch.","commit_id":"8234a01c4014bcbfb5d171645797b167bef4567f"}],"src/target/cortex_m.h":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b00e988190d5e5aeb848ec62c92714f78393002a","unresolved":false,"context_lines":[{"line_number":202,"context_line":"\tstruct armv7m_common armv7m;"},{"line_number":203,"context_line":""},{"line_number":204,"context_line":"\tbool slow_register_read;\t/* A register has not been ready, poll S_REGRDY */"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tint apsel;"},{"line_number":207,"context_line":""},{"line_number":208,"context_line":"\t/* Whether this target has the erratum that makes C_MASKINTS not apply to"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_901b2cd4","line":205,"updated":"2019-10-17 09:35:07.000000000","message":"There could be cases where the fast read fails because CPU is clocked at low speed. Then we change the CPU speed and we want go back to fast read.\nI propose a target configure flag. It could be implemented in a separate patch.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"964144f758661431373e8526546fd3b62c2c954a","unresolved":false,"context_lines":[{"line_number":202,"context_line":"\tstruct armv7m_common armv7m;"},{"line_number":203,"context_line":""},{"line_number":204,"context_line":"\tbool slow_register_read;\t/* A register has not been ready, poll S_REGRDY */"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tint apsel;"},{"line_number":207,"context_line":""},{"line_number":208,"context_line":"\t/* Whether this target has the erratum that makes C_MASKINTS not apply to"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8e7fc396_5015949b","line":205,"in_reply_to":"8e7fc396_901b2cd4","updated":"2019-10-17 13:09:42.000000000","message":"I don\u0027t like the idea of adding configuration options to something that could be expected to be handled internally. Just give me the registers, as fast as you can. I don\u0027t want to bother with selecting between internal implementations of the same thing based on who-knows-what.\n\nThe selection could easily be done automatically and dynamically by noticing if all registers at some point suddenly are available in the first atomic read (no additional poll needed), and then switch back to the full read in one transfer for the next go.\n\nI also think this could be integrated in the same function.","commit_id":"b5b05c0b604b72a7c75d89e5e106e49f743a7025"}]}