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07:40:57.000000000","message":"Patch Set 2:\n\nanother trial to fix the same issue\nhttp://openocd.zylin.com/#/c/6052/","accounts_in_message":[],"_revision_number":2},{"id":"e8820b17b30d51ef8803d3cab13f6a99df4c01d7","author":{"_account_id":1001853,"name":"Weijie Gao","email":"hackpascal@gmail.com","username":"hackpascal"},"real_author":{"_account_id":1001853,"name":"Weijie Gao","email":"hackpascal@gmail.com","username":"hackpascal"},"date":"2021-02-22 14:50:22.000000000","message":"Patch Set 2: Code-Review+1","accounts_in_message":[],"_revision_number":2},{"id":"020d3f01cd0ff8eea0c5d803cd2bd8792e397dbb","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-09 14:22:17.000000000","message":"Patch Set 2:\n\nI would like to have this reviewed/upstreamed","accounts_in_message":[],"_revision_number":2},{"id":"f49af24e838166325de244b0d6ac9d66933390d4","author":{"_account_id":1001765,"name":"Kevin Yang","email":"kangyang@google.com","username":"kangyang_google"},"real_author":{"_account_id":1001765,"name":"Kevin Yang","email":"kangyang@google.com","username":"kangyang_google"},"date":"2021-03-09 19:36:04.000000000","message":"Patch Set 2: Code-Review+1","accounts_in_message":[],"_revision_number":2},{"id":"336ed169cdeba8cd016f06835a11cbed2ee917b1","author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"real_author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"date":"2021-03-10 17:16:06.000000000","message":"Patch Set 2: Code-Review-1\n\nThe intention to have an ERROR_FAIL here was to catch access to the register since its existence in AARCH32 mode was unclear. \n\nThe actual question is: why is something accessing the register in AARCH32 mode, and what happens to e.g. the register cache, if the read now returns uninitialized memory. Can this clobber the AARCH64 register state?","accounts_in_message":[],"_revision_number":2},{"id":"ca7a4103f2a9732fdc8db23acf859a4b9da61023","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-10 17:32:36.000000000","message":"Patch Set 2:\n\n\u003e The intention to have an ERROR_FAIL here was to catch access to the\n \u003e register since its existence in AARCH32 mode was unclear.\n \u003e \n \u003e The actual question is: why is something accessing the register in\n \u003e AARCH32 mode, and what happens to e.g. the register cache, if the\n \u003e read now returns uninitialized memory. Can this clobber the AARCH64\n \u003e register state?\n\nmy understanding is that there is two separate caches, one for 32 bit state and another for 64 state, so it shouldn\u0027t clobber the 64 state cache, unless I\u0027m missing stgh","accounts_in_message":[],"_revision_number":2},{"id":"c4d3f55cc5041edd5b74cafca96f806ba2d9db48","author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"real_author":{"_account_id":1001013,"name":"Matthias Welwarsky","email":"matthias@welwarsky.de","username":"thinkfat"},"date":"2021-03-10 20:07:49.000000000","message":"Patch Set 2:\n\nThe cache is actually shared between modes. That might be inconsequential, though, since I don\u0027t think we have a possibility (yet) to switch between modes without exiting debug state. But as it stands, IMO this is architecturally the wrong place for the fix. It\u0027d be much better to find out where the access originates, and why, because this register should not be in the list we transfer to gdb and the only other place is armv8_dpm_read_current_registers() in armv8_dpm.c This function already contains code for reading registers based on availability in a certain EL or core mode and a special case handling for SPSR_EL1 which is not always available. I suggest putting the fix there instead of down in the low-level access functions.","accounts_in_message":[],"_revision_number":2},{"id":"b42a58823d5c6d9ad249f3b8173a8c708e7e860a","tag":"autogenerated:gerrit:setWorkInProgress","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-09-02 12:38:17.000000000","message":"Set Work In Progress","accounts_in_message":[],"_revision_number":2},{"id":"062132ee1b345f2c53242063e33468a580943d43","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2023-09-07 11:49:54.000000000","message":"Patch Set 2: Code-Review-1\n\n(1 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BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2020-03-13 11:25:03.000000000","tz":60},"subject":"armv8: don\u0027t throw an error for unsupported ESR_EL3 access in AArch32 state","message":"armv8: don\u0027t throw an error for unsupported ESR_EL3 access in AArch32 state\n\nIn ARMv8-A ARM (DDI 0487F.a), chapters D13.2.36 to D13.2.38:\nESR_EL1 and ESR_EL2 are mapper respectively to DFSR and HSR\nbut there is no mention if ESR_EL3 are mapped to an AArch32 register\nwhich explain the current situation/\n\nIn this change we added a warning logged for each access to ESR_EL3\nand avoided to report an error in order to avoid failure in polling\ncausing to reexamine the target and re-execute examine-start and -end\nwithout real need.\n\nNote: some ARMv8-A processors TRM (like A53 and A35) indicates that\nESR_EL1 is mapped to DFSR(NS) and ESR_EL3 is mapped to DFSR(S)\nbut we don\u0027t know if this applies to all ARMv8-A processors.\na support case is opened with ARM and we are waiting for their help.\n\nChange-Id: I9e0367bd9a26c5b4cbb23ff9c64abbe79f0cbd62\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"3953061d9b1229579228e5af7f85c67bb0a26088":{"kind":"REWORK","_number":2,"created":"2021-02-11 14:31:41.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/17/5517/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/17/5517/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/17/5517/2 \u0026\u0026 git checkout -b change-5517 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/17/5517/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/17/5517/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/17/5517/2 \u0026\u0026 git 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