)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"5c27e32957567030fd9802833cee74aa5ef9a3b0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"6f1410ed_9700991d","updated":"2021-10-08 20:15:16.000000000","message":"Antonio, the updates you made look good and thanks for them.","commit_id":"aa94e17460344d4a7ecdad33a85eec2ba4295131"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"702aa2ee2ff902a2554416cebb58c47f63539122","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"cd796809_7f49f90b","updated":"2022-06-15 16:28:57.000000000","message":"Daniel, I\u0027m ok with this. Just one comment below, not sure it is relevant.","commit_id":"a7c0117e9fa940bf50c57335a9673a3283fb64f2"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"406cfb6851f622c300457448122e7bab1bbe7d11","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"a7373076_53998887","updated":"2022-06-15 14:42:46.000000000","message":"Minor update for multi-socket configuration support","commit_id":"a7c0117e9fa940bf50c57335a9673a3283fb64f2"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"4286154c2ad4d1b7dfa952a785de4d2f46174fc8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"5299b3ef_5ac701f4","updated":"2022-06-15 22:16:06.000000000","message":"Added description of the SPLITSMP option per code review.","commit_id":"85bb114d3ed84501287fbc1043f8c0e872f8587c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"de80f634d78c05b37629ec99591555ec5ade498d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"a16c9ce6_79c1e1cf","updated":"2022-06-15 22:26:18.000000000","message":"Thanks","commit_id":"85bb114d3ed84501287fbc1043f8c0e872f8587c"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"036d782f5d85c0dfd75975d653e8cd1a1fe2ee47","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"328d009c_34337744","updated":"2022-06-23 13:27:12.000000000","message":"In preparation for the upcoming ADIv6 patch release, fix a misspelled word. This patch (5591) is ready to go.","commit_id":"05966573d2d935cc2a2abe1e82bef7fca173b7c3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"41a7c9a6abc47fc706d4a3ad1e87ec3cb0405678","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"9044bed4_3bd5c491","updated":"2022-06-23 13:54:17.000000000","message":"thanks!","commit_id":"05966573d2d935cc2a2abe1e82bef7fca173b7c3"}],"tcl/target/ampere_qs.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"eac7d3773e71290ee84b71a1c6dfc143972412f6","unresolved":false,"context_lines":[{"line_number":134,"context_line":"# Configure target PMPRO CPU"},{"line_number":135,"context_line":"#"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"eval [format \"target create ${_CHIPNAME}.${_TARGETNAME_PMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_PMPRO} -ap-num ${_AP_PMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":138,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_PMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_PMPRO} -ap-num ${_AP_PMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":139,"context_line":""},{"line_number":140,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_84aaf680","line":137,"range":{"start_line":137,"start_character":0,"end_line":137,"end_character":198},"updated":"2020-11-08 17:18:44.000000000","message":"why do you need such complication? Doesn\u0027t work with:\ntarget create ${_CHIPNAME}.${_TARGETNAME_PMPRO} cortex_m ...\n\nPlus, cortex_m does not use -dbgbase\nPlus, -rtos hwthread is for SMP nodes, and SMP is not applicable in OpenOCD to cortex-M yet.\nPlus -coreid is again for SMP.\nDo you have some special reason to use all these flags?","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c6820a57b98aaa3503cfe06b0825ba076b5c8941","unresolved":false,"context_lines":[{"line_number":134,"context_line":"# Configure target PMPRO CPU"},{"line_number":135,"context_line":"#"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"eval [format \"target create ${_CHIPNAME}.${_TARGETNAME_PMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_PMPRO} -ap-num ${_AP_PMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":138,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_PMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_PMPRO} -ap-num ${_AP_PMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":139,"context_line":""},{"line_number":140,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_3fb473e4","line":137,"range":{"start_line":137,"start_character":0,"end_line":137,"end_character":198},"in_reply_to":"ceda9b01_84aaf680","updated":"2020-11-23 18:57:25.000000000","message":"All good points you raise. Patchset 2 addresses the issues.","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"eac7d3773e71290ee84b71a1c6dfc143972412f6","unresolved":false,"context_lines":[{"line_number":147,"context_line":"# Configure target SMPRO CPU"},{"line_number":148,"context_line":"#"},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"eval [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":151,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":152,"context_line":""},{"line_number":153,"context_line":"# Create the DAP APB-AP MEM-AP target for the ARMV8 cores"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_24af8a93","line":150,"updated":"2020-11-08 17:18:44.000000000","message":"same comments as above","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c6820a57b98aaa3503cfe06b0825ba076b5c8941","unresolved":false,"context_lines":[{"line_number":147,"context_line":"# Configure target SMPRO CPU"},{"line_number":148,"context_line":"#"},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"eval [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":151,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":152,"context_line":""},{"line_number":153,"context_line":"# Create the DAP APB-AP MEM-AP target for the ARMV8 cores"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_df98c77e","line":150,"in_reply_to":"ceda9b01_24af8a93","updated":"2020-11-23 18:57:25.000000000","message":"Thanks for the comment. Patchset 2 addresses the issues.","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"eac7d3773e71290ee84b71a1c6dfc143972412f6","unresolved":false,"context_lines":[{"line_number":151,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":152,"context_line":""},{"line_number":153,"context_line":"# Create the DAP APB-AP MEM-AP target for the ARMV8 cores"},{"line_number":154,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.apb mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -apbase ${_AP_ARMV8_APB_ADDR}"},{"line_number":155,"context_line":""},{"line_number":156,"context_line":"# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores"},{"line_number":157,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.axi mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_AXI} -apbase ${_AP_ARMV8_AXI_ADDR}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_44b40ee5","line":154,"range":{"start_line":154,"start_character":125,"end_line":154,"end_character":134},"updated":"2020-11-08 17:18:44.000000000","message":"-apbase is unknown by OpenOCD.\nThis patch depends from http://openocd.zylin.com/5576/ \nI will switch to review that!","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c6820a57b98aaa3503cfe06b0825ba076b5c8941","unresolved":false,"context_lines":[{"line_number":151,"context_line":"puts [format \"target create ${_CHIPNAME}.${_TARGETNAME_SMPRO} cortex_m -endian ${_ENDIAN} -dap ${_DAPNAME_SMPRO} -ap-num ${_AP_SMPRO_AHB} -dbgbase 0x%08X -rtos hwthread -coreid 0\" [expr 0xE000ED00]]"},{"line_number":152,"context_line":""},{"line_number":153,"context_line":"# Create the DAP APB-AP MEM-AP target for the ARMV8 cores"},{"line_number":154,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.apb mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -apbase ${_AP_ARMV8_APB_ADDR}"},{"line_number":155,"context_line":""},{"line_number":156,"context_line":"# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores"},{"line_number":157,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.axi mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_AXI} -apbase ${_AP_ARMV8_AXI_ADDR}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_bf9f0362","line":154,"range":{"start_line":154,"start_character":125,"end_line":154,"end_character":134},"in_reply_to":"ceda9b01_44b40ee5","updated":"2020-11-23 18:57:25.000000000","message":"Yes, Ampere\u0027s Altra (Quicksilver) server processor uses an ARM Coresight ADIv6 DAP. There are various changes needed to be made to the ADIv5 driver in order to handle the necessary ADIv6 support. ADIv6 uses a 32-bit address to access the Access Ports (APs) instead of an index number (0-255) that ADIv5 uses. To address this, we added an \"-apbase\" argument to the \u0027target create\u0027 command. We are aware the corresponding ADIv6 DAP patch submission is large and are looking into splitting the patch up into smaller, more manageable patches for review.","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"eac7d3773e71290ee84b71a1c6dfc143972412f6","unresolved":false,"context_lines":[{"line_number":181,"context_line":"\t# Create and configure Cross Trigger Interface (CTI) - required for halt and resume"},{"line_number":182,"context_line":"\tset _CTINAME ${_TARGETNAME}.cti"},{"line_number":183,"context_line":"\tset _offset [expr {(0x00100000 * ${_index}) + (0x00200000 * (${_index}\u003e\u003e1))}]"},{"line_number":184,"context_line":"\teval [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":185,"context_line":"\tputs [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":186,"context_line":""},{"line_number":187,"context_line":"\t# Create the target"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_e498a27e","line":184,"range":{"start_line":184,"start_character":0,"end_line":184,"end_character":134},"updated":"2020-11-08 17:18:44.000000000","message":"also here should be ok using\ncti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -ctibase [expr 0xA0220000 + $_offset]","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c6820a57b98aaa3503cfe06b0825ba076b5c8941","unresolved":false,"context_lines":[{"line_number":181,"context_line":"\t# Create and configure Cross Trigger Interface (CTI) - required for halt and resume"},{"line_number":182,"context_line":"\tset _CTINAME ${_TARGETNAME}.cti"},{"line_number":183,"context_line":"\tset _offset [expr {(0x00100000 * ${_index}) + (0x00200000 * (${_index}\u003e\u003e1))}]"},{"line_number":184,"context_line":"\teval [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":185,"context_line":"\tputs [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":186,"context_line":""},{"line_number":187,"context_line":"\t# Create the target"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_ff958b43","line":184,"range":{"start_line":184,"start_character":0,"end_line":184,"end_character":134},"in_reply_to":"ceda9b01_e498a27e","updated":"2020-11-23 18:57:25.000000000","message":"Patchset 2 addresses the issues.","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"eac7d3773e71290ee84b71a1c6dfc143972412f6","unresolved":false,"context_lines":[{"line_number":185,"context_line":"\tputs [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":186,"context_line":""},{"line_number":187,"context_line":"\t# Create the target"},{"line_number":188,"context_line":"\teval [format \"target create ${_TARGETNAME} aarch64 -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -dbgbase 0x%08X -rtos hwthread -cti ${_CTINAME} -coreid %d\" [expr 0xA0210000 + ${_offset}] ${_index}]"},{"line_number":189,"context_line":"\tputs [format \"target create ${_TARGETNAME} aarch64 -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -dbgbase 0x%08X -rtos hwthread -cti ${_CTINAME} -coreid %d\" [expr 0xA0210000 + ${_offset}] ${_index}]"},{"line_number":190,"context_line":"\tset _SMP_STR \"${_SMP_STR} ${_TARGETNAME}\""},{"line_number":191,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_04960650","line":188,"range":{"start_line":188,"start_character":0,"end_line":188,"end_character":220},"updated":"2020-11-08 17:18:44.000000000","message":"and also this can be simplified","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"c6820a57b98aaa3503cfe06b0825ba076b5c8941","unresolved":false,"context_lines":[{"line_number":185,"context_line":"\tputs [format \"cti create ${_CTINAME} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -ctibase 0x%08X\" [expr 0xA0220000 + ${_offset}]]"},{"line_number":186,"context_line":""},{"line_number":187,"context_line":"\t# Create the target"},{"line_number":188,"context_line":"\teval [format \"target create ${_TARGETNAME} aarch64 -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -dbgbase 0x%08X -rtos hwthread -cti ${_CTINAME} -coreid %d\" [expr 0xA0210000 + ${_offset}] ${_index}]"},{"line_number":189,"context_line":"\tputs [format \"target create ${_TARGETNAME} aarch64 -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -dbgbase 0x%08X -rtos hwthread -cti ${_CTINAME} -coreid %d\" [expr 0xA0210000 + ${_offset}] ${_index}]"},{"line_number":190,"context_line":"\tset _SMP_STR \"${_SMP_STR} ${_TARGETNAME}\""},{"line_number":191,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ceda9b01_9fa23fa3","line":188,"range":{"start_line":188,"start_character":0,"end_line":188,"end_character":220},"in_reply_to":"ceda9b01_04960650","updated":"2020-11-23 18:57:25.000000000","message":"Patchset 2 addresses the issues.","commit_id":"931e6f93c29e2c7d36af1c21ce4941b39de7fe31"}],"tcl/target/ampere_qs_mq.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f6b87d34734eb1012a6d7e6f95de63c497c0ab38","unresolved":false,"context_lines":[{"line_number":173,"context_line":"}"},{"line_number":174,"context_line":""},{"line_number":175,"context_line":"# Create the DAP APB-AP MEM-AP target for the ARMV8 cores"},{"line_number":176,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.apb mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_APB} -apbase ${_AP_ARMV8_APB_ADDR}"},{"line_number":177,"context_line":""},{"line_number":178,"context_line":"# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores"},{"line_number":179,"context_line":"target create ${_CHIPNAME}.${_TARGETNAME_ARMV8}.axi mem_ap -endian ${_ENDIAN} -dap ${_DAPNAME_ARMV8} -ap-num ${_AP_ARMV8_AXI} -apbase ${_AP_ARMV8_AXI_ADDR}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ceda9b01_c5f1d8c9","line":176,"range":{"start_line":176,"start_character":126,"end_line":176,"end_character":133},"updated":"2020-12-17 23:51:56.000000000","message":"Do you think it could be acceptable to use the switch name \u0027-baseaddr\u0027 instead of \u0027-apbase\u0027?\n\nThere is a new helper in http://openocd.zylin.com/5857/ to simplify getting the triple (-dap, -ap-num, -baseaddr), which partially overlaps with your adi_jim_configure().\n\nI introduced it for entering the coordinates of a device accessible in one AP, but maybe could be reused here.\nIt could help reducing the size of the patch that adds ADIV6 support.\nIf you think the flag name replacement is acceptable, simply replace s/-apbase/-baseaddr/g everywhere in this patch set so the command API will not be modified later.\nI mean, keep you helper adi_jim_configure() for the time being; no need to use immediately http://openocd.zylin.com/5857/ in your code, but only be ready for the switch without impact on the TCL command.","commit_id":"3e098d2213302523dea3d29e8110bd4de98be21c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"bf68eaea258a5722c7c1c085ce694128a144b44a","unresolved":false,"context_lines":[{"line_number":264,"context_line":""},{"line_number":265,"context_line":"foreach physical_index $_CORELIST {"},{"line_number":266,"context_line":"\tif { [info exists PHYS_IDX] } {"},{"line_number":267,"context_line":"\t\tset logical_index [expr $physical_index + $_CORE_INDEX_OFFSET]"},{"line_number":268,"context_line":"\t}"},{"line_number":269,"context_line":""},{"line_number":270,"context_line":"\t# Format a string to reference which CPU target to use"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"aedf27f1_7e90bd46","line":267,"updated":"2021-05-13 16:15:56.000000000","message":"Pay attention that jimtcl 0.81 restricts the syntax of \u0027expr\u0027 to a single argument! To avoid syntax error when OpenOCD will update jimtcl version, start using a single argument. Preferred is to use curly brackets, but if there is any string concatenation for building a variable name (e.g. $_CHIPNAME.$_TARGETNAME_ARMV8.axi) then use double quote.\nThis line should be written as\nset logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]","commit_id":"f5dc21068daf77b6b34060726eb6daa11428d2a3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"bf68eaea258a5722c7c1c085ce694128a144b44a","unresolved":false,"context_lines":[{"line_number":277,"context_line":"\t# Create and configure Cross Trigger Interface (CTI) - required for halt and resume"},{"line_number":278,"context_line":"\tset _CTINAME $_TARGETNAME.cti"},{"line_number":279,"context_line":"\tset _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index\u003e\u003e1))}]"},{"line_number":280,"context_line":"\tcti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr 0xA0220000 + $_offset]"},{"line_number":281,"context_line":""},{"line_number":282,"context_line":"\t# Create the target"},{"line_number":283,"context_line":"\ttarget create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr 0xA0210000 + $_offset] -rtos hwthread -cti $_CTINAME -coreid $logical_index"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"aedf27f1_1e95f135","line":280,"updated":"2021-05-13 16:15:56.000000000","message":"same here, use [expr {...}]","commit_id":"f5dc21068daf77b6b34060726eb6daa11428d2a3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"bf68eaea258a5722c7c1c085ce694128a144b44a","unresolved":false,"context_lines":[{"line_number":280,"context_line":"\tcti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr 0xA0220000 + $_offset]"},{"line_number":281,"context_line":""},{"line_number":282,"context_line":"\t# Create the target"},{"line_number":283,"context_line":"\ttarget create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr 0xA0210000 + $_offset] -rtos hwthread -cti $_CTINAME -coreid $logical_index"},{"line_number":284,"context_line":""},{"line_number":285,"context_line":"\t# Build string used to enable SMP mode for the ARMv8 CPU cores"},{"line_number":286,"context_line":"\tset _SMP_STR \"$_SMP_STR $_TARGETNAME\""}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"aedf27f1_3e9a3567","line":283,"updated":"2021-05-13 16:15:56.000000000","message":"here too!","commit_id":"f5dc21068daf77b6b34060726eb6daa11428d2a3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"702aa2ee2ff902a2554416cebb58c47f63539122","unresolved":true,"context_lines":[{"line_number":7,"context_line":""},{"line_number":8,"context_line":"# Command Line Argument Description"},{"line_number":9,"context_line":"#"},{"line_number":10,"context_line":"# SMP_STR"},{"line_number":11,"context_line":"# If not specified, defaults to SMP core grouping defined per chip"},{"line_number":12,"context_line":"# SMP_STR\u003d\"\u003cstring\u003e\": SMP core grouping defined in board cfg file"},{"line_number":13,"context_line":"# Used to group dual chips into a single SMP configuration"},{"line_number":14,"context_line":"#"},{"line_number":15,"context_line":"# CHIPNAME"},{"line_number":16,"context_line":"# Specifies the name of the chip."}],"source_content_type":"text/x-ttcn-cfg","patch_set":11,"id":"985d976b_d394fbe2","line":13,"range":{"start_line":10,"start_character":2,"end_line":13,"end_character":7},"updated":"2022-06-15 16:28:57.000000000","message":"Do you plan to add a description of SPLITSMP ?","commit_id":"a7c0117e9fa940bf50c57335a9673a3283fb64f2"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"4286154c2ad4d1b7dfa952a785de4d2f46174fc8","unresolved":false,"context_lines":[{"line_number":7,"context_line":""},{"line_number":8,"context_line":"# Command Line Argument Description"},{"line_number":9,"context_line":"#"},{"line_number":10,"context_line":"# SMP_STR"},{"line_number":11,"context_line":"# If not specified, defaults to SMP core grouping defined per chip"},{"line_number":12,"context_line":"# SMP_STR\u003d\"\u003cstring\u003e\": SMP core grouping defined in board cfg file"},{"line_number":13,"context_line":"# Used to group dual chips into a single SMP configuration"},{"line_number":14,"context_line":"#"},{"line_number":15,"context_line":"# CHIPNAME"},{"line_number":16,"context_line":"# Specifies the name of the chip."}],"source_content_type":"text/x-ttcn-cfg","patch_set":11,"id":"943e2e86_ea77350d","line":13,"range":{"start_line":10,"start_character":2,"end_line":13,"end_character":7},"in_reply_to":"985d976b_d394fbe2","updated":"2022-06-15 22:16:06.000000000","message":"Yes, good catch. I submitted an update to address this oversight.","commit_id":"a7c0117e9fa940bf50c57335a9673a3283fb64f2"}]}