)]}'
{"src/flash/nor/stm32l4x.c":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"c909d332c675cc480ba8c37f5f71259975a64fd0","unresolved":false,"context_lines":[{"line_number":1321,"context_line":""},{"line_number":1322,"context_line":"\tstm32l4_info-\u003eprobed \u003d false;"},{"line_number":1323,"context_line":""},{"line_number":1324,"context_line":"\t/* read stm32 device id registers */"},{"line_number":1325,"context_line":"\tint retval \u003d stm32l4_read_idcode(bank, \u0026stm32l4_info-\u003eidcode);"},{"line_number":1326,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1327,"context_line":"\t\treturn retval;"},{"line_number":1328,"context_line":""},{"line_number":1329,"context_line":"\tdevice_id \u003d stm32l4_info-\u003eidcode \u0026 0xFFF;"},{"line_number":1330,"context_line":""},{"line_number":1331,"context_line":"\tfor (unsigned int n \u003d 0; n \u003c ARRAY_SIZE(stm32l4_parts); n++) {"},{"line_number":1332,"context_line":"\t\tif (device_id \u003d\u003d stm32l4_parts[n].id)"},{"line_number":1333,"context_line":"\t\t\tstm32l4_info-\u003epart_info \u003d \u0026stm32l4_parts[n];"},{"line_number":1334,"context_line":"\t}"},{"line_number":1335,"context_line":""},{"line_number":1336,"context_line":"\tif (!stm32l4_info-\u003epart_info) {"},{"line_number":1337,"context_line":"\t\tLOG_WARNING(\"Cannot identify target as an %s family device.\", device_families);"},{"line_number":1338,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1339,"context_line":"\t}"},{"line_number":1340,"context_line":""},{"line_number":1341,"context_line":"\tpart_info \u003d stm32l4_info-\u003epart_info;"},{"line_number":1342,"context_line":"\tstm32l4_info-\u003eflash_regs \u003d stm32l4_info-\u003epart_info-\u003edefault_flash_regs;"},{"line_number":1343,"context_line":""},{"line_number":1344,"context_line":"\tchar device_info[1024];"},{"line_number":1345,"context_line":"\tretval \u003d bank-\u003edriver-\u003einfo(bank, device_info, sizeof(device_info));"},{"line_number":1346,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1347,"context_line":"\t\treturn retval;"},{"line_number":1348,"context_line":""},{"line_number":1349,"context_line":"\tLOG_INFO(\"device idcode \u003d 0x%08\" PRIx32 \" (%s)\", stm32l4_info-\u003eidcode, device_info);"},{"line_number":1350,"context_line":""},{"line_number":1351,"context_line":"\t/* read flash option register */"},{"line_number":1352,"context_line":"\tretval \u003d stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, \u0026stm32l4_info-\u003eoptr);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ceda9b01_6467d223","line":1349,"range":{"start_line":1324,"start_character":0,"end_line":1349,"end_character":85},"updated":"2020-11-12 16:17:27.000000000","message":"probaly this part should/could be skipped in case of re-probing","commit_id":"5b3df545102802a2b21089c411e143c0dcfb0489"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"c909d332c675cc480ba8c37f5f71259975a64fd0","unresolved":false,"context_lines":[{"line_number":1364,"context_line":"\t\t\tstm32l4_info-\u003erdp \u003d\u003d RDP_LEVEL_0 ? \"0\" : stm32l4_info-\u003erdp \u003d\u003d RDP_LEVEL_0_5 ? \"0.5\" : \"1\","},{"line_number":1365,"context_line":"\t\t\tstm32l4_info-\u003erdp);"},{"line_number":1366,"context_line":""},{"line_number":1367,"context_line":"\tif (stm32l4_is_otp(bank)) {"},{"line_number":1368,"context_line":"\t\tbank-\u003esize \u003d part_info-\u003eotp_size;"},{"line_number":1369,"context_line":""},{"line_number":1370,"context_line":"\t\tLOG_INFO(\"OTP size is %d bytes, base address is \" TARGET_ADDR_FMT, bank-\u003esize, bank-\u003ebase);"},{"line_number":1371,"context_line":""},{"line_number":1372,"context_line":"\t\t/* OTP memory is considered as one sector */"},{"line_number":1373,"context_line":"\t\tfree(bank-\u003esectors);"},{"line_number":1374,"context_line":"\t\tbank-\u003enum_sectors \u003d 1;"},{"line_number":1375,"context_line":"\t\tbank-\u003esectors \u003d alloc_block_array(0, part_info-\u003eotp_size, 1);"},{"line_number":1376,"context_line":""},{"line_number":1377,"context_line":"\t\tif (!bank-\u003esectors) {"},{"line_number":1378,"context_line":"\t\t\tLOG_ERROR(\"failed to allocate bank sectors\");"},{"line_number":1379,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1380,"context_line":"\t\t}"},{"line_number":1381,"context_line":""},{"line_number":1382,"context_line":"\t\tstm32l4_info-\u003eprobed \u003d true;"},{"line_number":1383,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1384,"context_line":"\t} else if (bank-\u003ebase !\u003d STM32_FLASH_BANK_BASE) {"},{"line_number":1385,"context_line":"\t\tLOG_ERROR(\"invalid bank base address\");"},{"line_number":1386,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1387,"context_line":"\t}"},{"line_number":1388,"context_line":""},{"line_number":1389,"context_line":"\t/* get flash size from target. */"},{"line_number":1390,"context_line":"\tretval \u003d target_read_u16(target, part_info-\u003efsize_addr, \u0026flash_size_kb);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ceda9b01_846c3607","line":1387,"range":{"start_line":1367,"start_character":0,"end_line":1387,"end_character":2},"updated":"2020-11-12 16:17:27.000000000","message":"maybe this too","commit_id":"5b3df545102802a2b21089c411e143c0dcfb0489"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"c909d332c675cc480ba8c37f5f71259975a64fd0","unresolved":false,"context_lines":[{"line_number":1386,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1387,"context_line":"\t}"},{"line_number":1388,"context_line":""},{"line_number":1389,"context_line":"\t/* get flash size from target. */"},{"line_number":1390,"context_line":"\tretval \u003d target_read_u16(target, part_info-\u003efsize_addr, \u0026flash_size_kb);"},{"line_number":1391,"context_line":""},{"line_number":1392,"context_line":"\t/* failed reading flash size or flash size invalid (early silicon),"},{"line_number":1393,"context_line":"\t * default to max target family */"},{"line_number":1394,"context_line":"\tif (retval !\u003d ERROR_OK || flash_size_kb \u003d\u003d 0xffff || flash_size_kb \u003d\u003d 0"},{"line_number":1395,"context_line":"\t\t\t|| flash_size_kb \u003e part_info-\u003emax_flash_size_kb) {"},{"line_number":1396,"context_line":"\t\tLOG_WARNING(\"STM32 flash size failed, probe inaccurate - assuming %dk flash\","},{"line_number":1397,"context_line":"\t\t\tpart_info-\u003emax_flash_size_kb);"},{"line_number":1398,"context_line":"\t\tflash_size_kb \u003d part_info-\u003emax_flash_size_kb;"},{"line_number":1399,"context_line":"\t}"},{"line_number":1400,"context_line":""},{"line_number":1401,"context_line":"\t/* if the user sets the size manually then ignore the probed value"},{"line_number":1402,"context_line":"\t * this allows us to work around devices that have a invalid flash size register value */"},{"line_number":1403,"context_line":"\tif (stm32l4_info-\u003euser_bank_size) {"},{"line_number":1404,"context_line":"\t\tLOG_WARNING(\"overriding size register by configured bank size - MAY CAUSE TROUBLE\");"},{"line_number":1405,"context_line":"\t\tflash_size_kb \u003d stm32l4_info-\u003euser_bank_size / 1024;"},{"line_number":1406,"context_line":"\t}"},{"line_number":1407,"context_line":""},{"line_number":1408,"context_line":"\tLOG_INFO(\"flash size \u003d %dkbytes\", flash_size_kb);"},{"line_number":1409,"context_line":""},{"line_number":1410,"context_line":"\t/* did we assign a flash size? */"},{"line_number":1411,"context_line":"\tassert((flash_size_kb !\u003d 0xffff) \u0026\u0026 flash_size_kb);"},{"line_number":1412,"context_line":""},{"line_number":1413,"context_line":"\tstm32l4_info-\u003ebank1_sectors \u003d 0;"},{"line_number":1414,"context_line":"\tstm32l4_info-\u003ehole_sectors \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ceda9b01_2471cadd","line":1411,"range":{"start_line":1389,"start_character":0,"end_line":1411,"end_character":52},"updated":"2020-11-12 16:17:27.000000000","message":"maybe this too","commit_id":"5b3df545102802a2b21089c411e143c0dcfb0489"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b10cb2a11e522dd3b557b23d5550b1ebb819f0e5","unresolved":true,"context_lines":[{"line_number":1664,"context_line":"\t\tuint32_t optr_cur;"},{"line_number":1665,"context_line":""},{"line_number":1666,"context_line":"\t\t/* read flash option register and re-probe if optr value is changed */"},{"line_number":1667,"context_line":"\t\tint retval \u003d stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, \u0026optr_cur);"},{"line_number":1668,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1669,"context_line":"\t\t\treturn retval;"},{"line_number":1670,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"f237dfcd_110fc36a","line":1667,"range":{"start_line":1667,"start_character":2,"end_line":1667,"end_character":88},"updated":"2021-12-15 11:50:47.000000000","message":"This turned out to a very annoying bug on STM32L5/U5\nThe device was probed probably in secure mode, stopped in non-secure mode and gdb disconnected. Now you want to connect gdb again. This read returns error and gdb connection is refused although \u0027flash probe 0/1/2\u0027 normally works!\n\nI did not search for the cause. Just changed the test to continue with stm32l4_probe() in case of error and it worked for me.","commit_id":"80d323c6e82b0256da4a671b1acbdceb54de9a82"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"71a0d59de7e5a1c16b43301dd7abaf31bd6a03be","unresolved":true,"context_lines":[{"line_number":1664,"context_line":"\t\tuint32_t optr_cur;"},{"line_number":1665,"context_line":""},{"line_number":1666,"context_line":"\t\t/* read flash option register and re-probe if optr value is changed */"},{"line_number":1667,"context_line":"\t\tint retval \u003d stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, \u0026optr_cur);"},{"line_number":1668,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1669,"context_line":"\t\t\treturn retval;"},{"line_number":1670,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"ff65c1a6_40044446","line":1667,"range":{"start_line":1667,"start_character":2,"end_line":1667,"end_character":88},"in_reply_to":"2fee44ba_e50892dd","updated":"2022-03-02 09:41:00.000000000","message":"Thanks Tomas,\nI have pushed, https://review.openocd.org/c/openocd/+/6864\nthis should solve the issue you have mentionned, but I will more confident if you can test in your side.","commit_id":"80d323c6e82b0256da4a671b1acbdceb54de9a82"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"de4218846a598a8416fdda0d540902d5aa2d7271","unresolved":true,"context_lines":[{"line_number":1664,"context_line":"\t\tuint32_t optr_cur;"},{"line_number":1665,"context_line":""},{"line_number":1666,"context_line":"\t\t/* read flash option register and re-probe if optr value is changed */"},{"line_number":1667,"context_line":"\t\tint retval \u003d stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, \u0026optr_cur);"},{"line_number":1668,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1669,"context_line":"\t\t\treturn retval;"},{"line_number":1670,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"f7a42dd0_c08b5eab","line":1667,"range":{"start_line":1667,"start_character":2,"end_line":1667,"end_character":88},"in_reply_to":"f237dfcd_110fc36a","updated":"2022-02-25 11:13:23.000000000","message":"Hi Tomas, just guessing, this could be related to the fact that OPTR is read as zero under reset\ncould you please check, and provide a log ?\nmeanwhile, I will try to reproduce (BTW I have alread have sthg in the pipe related the this zero OPTR but limited the target cfg, please check https://review.openocd.org/c/openocd/+/6558/3/tcl/target/stm32x5x_common.cfg#152 )","commit_id":"80d323c6e82b0256da4a671b1acbdceb54de9a82"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"63217689f35be05917f968e2787a532f49758600","unresolved":true,"context_lines":[{"line_number":1664,"context_line":"\t\tuint32_t optr_cur;"},{"line_number":1665,"context_line":""},{"line_number":1666,"context_line":"\t\t/* read flash option register and re-probe if optr value is changed */"},{"line_number":1667,"context_line":"\t\tint retval \u003d stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, \u0026optr_cur);"},{"line_number":1668,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":1669,"context_line":"\t\t\treturn retval;"},{"line_number":1670,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"2fee44ba_e50892dd","line":1667,"range":{"start_line":1667,"start_character":2,"end_line":1667,"end_character":88},"in_reply_to":"f7a42dd0_c08b5eab","updated":"2022-02-27 15:02:59.000000000","message":"Sorry for really poor description.\n\nSteps to reproduce the problem:\n\nSTM32L522, TZEN \u003d 1, RDP level 0, firmware like GPIO_IOToggle_TrustZone loaded\n\nConnect OpenOCD and probe the flash\n- because TZEN \u003d 1 \u0026\u0026 RDP level 0, stm32l4_probe() sets stm32l4_info-\u003eflash_regs_base |\u003d STM32L5_REGS_SEC_OFFSET\n\nSet RDP level to 0.5 and use option_load or nrst\n\nNow stm32l4_auto_probe() fails reading OPTR @ remembered 0x50022040, see the log from gdb connect:\n\nInfo : 392 161318 server.c:101 add_connection(): accepting \u0027gdb\u0027 connection on tcp/3333\nDebug: 393 161320 breakpoints.c:374 breakpoint_clear_target_internal(): Delete all breakpoints for target: stm32l5x.cpu\nDebug: 394 161320 breakpoints.c:554 watchpoint_clear_target(): Delete all watchpoints for target: stm32l5x.cpu\nDebug: 395 161342 target.c:1849 target_call_event_callbacks(): target event 22 (gdb-attach) for core stm32l5x.cpu\nDebug: 396 161343 target.c:4833 target_handle_event(): target(0): stm32l5x.cpu (cortex_m) event: 22 (gdb-attach) action: halt 1000\nDebug: 397 161343 command.c:166 script_debug(): command - halt 1000\nDebug: 398 161347 target.c:3308 handle_halt_command(): -\nDebug: 399 161347 cortex_m.c:988 cortex_m_halt(): target-\u003estate: halted\nDebug: 400 161347 cortex_m.c:991 cortex_m_halt(): target was already halted\nDebug: 401 161354 target.c:2633 target_read_u32(): address: 0x40022040, value: 0xffeff855\nDebug: 402 161358 stlink_usb.c:1113 stlink_usb_error_check(): STLINK_SWD_AP_WDATA_ERROR\nError: 403 161361 arm_adi_v5.c:561 mem_ap_read(): Failed to read memory at 0x50022040\nDebug: 404 161363 target.c:2637 target_read_u32(): address: 0x50022040 failed\nError: 405 161363 core.c:302 get_flash_bank_by_num(): auto_probe failed\nError: 406 161364 gdb_server.c:1047 gdb_new_connection(): Connect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use \u0027gdb_memory_map disable\u0027.\nError: 407 161366 server.c:105 add_connection(): attempted \u0027gdb\u0027 connection rejected\n\nIf there were no error, 3 OPTR reads was done (one for each bank).\nStrange is that the first read used 0x40022040 and the second failed @ 0x50022040.\n\nOn the other hand stm32l4_probe() works normally as it reads OPTR @ 0x40022040\nand sets stm32l4_info-\u003eflash_regs_base without STM32L5_REGS_SEC_OFFSET","commit_id":"80d323c6e82b0256da4a671b1acbdceb54de9a82"}]}