)]}'
{"id":"openocd~master~Ifb6e291bf97f814f0b9987b2c40f3037959f7af4","project":"openocd","branch":"master","attention_set":{},"removed_from_attention_set":{"1000410":{"account":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"last_update":"2021-08-26 13:11:13.000000000","reason":"removed on reply"},"1000863":{"account":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"last_update":"2021-08-26 13:13:02.000000000","reason":"Change was submitted"}},"hashtags":[],"change_id":"Ifb6e291bf97f814f0b9987b2c40f3037959f7af4","subject":"flash/stm32l4x: add support of STM32WL5x dual core","status":"MERGED","created":"2021-02-05 08:29:02.000000000","updated":"2021-08-26 13:13:02.000000000","submitted":"2021-08-26 13:13:02.000000000","submitter":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"total_comment_count":6,"unresolved_comment_count":0,"has_review_started":true,"submission_id":"6050","meta_rev_id":"0fdd999d6bd8ea3de6bf095a5e46a8f5f868455c","_number":6050,"owner":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"actions":{},"labels":{"Verified":{"approved":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"value":0,"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},{"value":0,"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},{"value":0,"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},{"tag":"autogenerated:gerrit:merged","value":1,"date":"2021-08-26 13:13:02.000000000","permitted_voting_range":{"min":1,"max":1},"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}],"values":{"-1":"Fails"," 0":"No score","+1":"Verified"},"description":"","default_value":0},"Code-Review":{"approved":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"all":[{"value":0,"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},{"tag":"autogenerated:gerrit:merged","value":2,"date":"2021-08-26 13:13:02.000000000","permitted_voting_range":{"min":2,"max":2},"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},{"value":0,"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},{"value":0,"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}],"values":{"-2":"This shall not be merged","-1":"I would prefer this is not merged as is"," 0":"No score","+1":"Looks good to me, but someone else must approve","+2":"Looks good to me, approved"},"description":"","default_value":0}},"removable_reviewers":[],"reviewers":{"REVIEWER":[{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"}]},"pending_reviewers":{},"reviewer_updates":[{"updated":"2021-08-16 17:52:20.000000000","updated_by":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"reviewer":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"state":"REVIEWER"},{"updated":"2021-08-16 22:04:39.000000000","updated_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"reviewer":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"state":"REVIEWER"},{"updated":"2021-08-26 06:50:33.000000000","updated_by":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"reviewer":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"state":"CC"},{"updated":"2021-08-26 12:52:01.000000000","updated_by":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"reviewer":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"state":"REVIEWER"}],"messages":[{"id":"be92a02632a315c1cbcba033b3683ed081cd3402","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-02-05 08:29:02.000000000","message":"Uploaded patch set 1.","accounts_in_message":[],"_revision_number":1},{"id":"7feebe55d5c174fb10401dd8d520d8bc449092b8","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-02-05 08:29:49.000000000","message":"Patch Set 1: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit/13975/ : FAILURE\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13240/ : FAILURE","accounts_in_message":[],"_revision_number":1},{"id":"eb562ba16f6b42b145a13708e3ad53eefbca0aec","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-02-05 08:35:49.000000000","message":"Uploaded patch set 2.","accounts_in_message":[],"_revision_number":2},{"id":"f57c7f89b6b6d26587fd4f6453df65f5384a3677","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-02-05 08:46:26.000000000","message":"Uploaded patch set 3: Commit message was updated.","accounts_in_message":[],"_revision_number":3},{"id":"86ec54226fd7360a8caea297c32f360df95d7599","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-02-05 08:46:27.000000000","message":"Patch Set 2: Verified-1\n\nBuild Failed \n\nhttp://build.openocd.org/job/openocd-gerrit-build/13241/ : ABORTED\n\nhttp://build.openocd.org/job/openocd-gerrit/13976/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"c037152f655292f7ff130d776eb62fd64cff2b76","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-02-05 09:17:39.000000000","message":"Patch Set 3: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/13977/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13242/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"23eac743f526e575df070d77ae1e74cee6c45d3d","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-02-14 21:20:19.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"a28b632eca5d4a469051d582b2346b42cf1bd0c2","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-02-14 21:54:48.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14007/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13271/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"f05b5d5dbb63b8c779747b3fcb985631637c5681","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-02-19 15:47:08.000000000","message":"Patch Set 4: Code-Review+1","accounts_in_message":[],"_revision_number":4},{"id":"24f2a96d04f31d0a61bb3c90880de4f8f3a060fd","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-16 02:25:12.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"8e2c416a5c092d80d987291cdd4392748555229a","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-03-16 07:12:10.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14150/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13412/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"a866c63fa478d984b6582b1a353bd7cd116cb2c6","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-16 11:04:13.000000000","message":"Uploaded patch set 6: Patch Set 5 was rebased.","accounts_in_message":[],"_revision_number":6},{"id":"207744157260b75e48882127b972170c477858c2","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-16 15:33:46.000000000","message":"Patch Set 6: Code-Review+1","accounts_in_message":[],"_revision_number":6},{"id":"223473e72f9b1677e5fd4b64cdbb7c548a6bfe02","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-03-16 17:05:47.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14161/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13423/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"34c15340ad0859933da4dcae37c5ccfe75683077","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-16 22:50:41.000000000","message":"Uploaded patch set 7: Patch Set 6 was rebased.","accounts_in_message":[],"_revision_number":7},{"id":"c0e6a18710fde34283a933c2d81947acc87b8443","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-03-17 04:07:47.000000000","message":"Patch Set 7: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14173/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13435/ : SUCCESS","accounts_in_message":[],"_revision_number":7},{"id":"c77068d160a41f1ae8d5d3d384282a6f85d845bc","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-03-17 12:31:48.000000000","message":"Uploaded patch set 8: Patch Set 7 was rebased.","accounts_in_message":[],"_revision_number":8},{"id":"4bec69539e17b2a03ff9c857d0f9a9ae579cb77c","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-03-17 17:53:03.000000000","message":"Patch Set 8: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14186/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13448/ : SUCCESS","accounts_in_message":[],"_revision_number":8},{"id":"bbb02dd49c925f29f6f8a3c46c0c004a78ab35c8","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-13 23:42:53.000000000","message":"Uploaded patch set 9.","accounts_in_message":[],"_revision_number":9},{"id":"bacd5980a8ea911662eb3fb0da6ff50c1e37277c","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-14 02:57:37.000000000","message":"Patch Set 9: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15011/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14245/ : SUCCESS","accounts_in_message":[],"_revision_number":9},{"id":"556e727052a6ca8a145ab772c288e4d2e0bf922a","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-14 13:39:41.000000000","message":"Uploaded patch set 10: Patch Set 9 was rebased.","accounts_in_message":[],"_revision_number":10},{"id":"f39b7d314b8ad46aa9f89871295570aaf259d56e","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-14 18:01:43.000000000","message":"Patch Set 10: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15023/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14257/ : SUCCESS","accounts_in_message":[],"_revision_number":10},{"id":"adab6c46bb8bcfe3a94efc14eb8381ea0fbd84bf","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-15 22:54:38.000000000","message":"Uploaded patch set 11: Patch Set 10 was rebased.","accounts_in_message":[],"_revision_number":11},{"id":"4bf7cefe06322c1e6274ea82b29fb7b41b0c771b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-16 00:45:30.000000000","message":"Patch Set 11: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15032/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14266/ : SUCCESS","accounts_in_message":[],"_revision_number":11},{"id":"4fcded1850d7fe815007f36c07402959bb039a0c","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-16 09:53:12.000000000","message":"Patch Set 11: Code-Review-1\n\n(1 comment)","accounts_in_message":[],"_revision_number":11},{"id":"66c184df862a00c1ce8c134ae086edad71f6d0de","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 15:43:00.000000000","message":"Uploaded patch set 12.","accounts_in_message":[],"_revision_number":12},{"id":"727e62acce5eaef5ebd211e7a2ea40e09557eae3","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-16 16:20:37.000000000","message":"Patch Set 12: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15046/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14280/ : SUCCESS","accounts_in_message":[],"_revision_number":12},{"id":"27a0917e5d7325dcb51f1129bcc1f0ea5d49b563","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 16:22:07.000000000","message":"Patch Set 12:\n\n(2 comments)","accounts_in_message":[],"_revision_number":12},{"id":"c4ef10113f73c5884c2ebd5f7afb93e49e866fa9","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-16 17:52:20.000000000","message":"Patch Set 12: Code-Review+1","accounts_in_message":[],"_revision_number":12},{"id":"3dee4c9aa0a916a30f70545b9ebaa88b0a4c22a7","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 19:50:17.000000000","message":"Patch Set 12: Code-Review+1","accounts_in_message":[],"_revision_number":12},{"id":"ed03bcf18fa5641a027e0a85f9a82ec1d148be0f","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 19:55:15.000000000","message":"Patch Set 12: -Code-Review\n\n(1 comment)","accounts_in_message":[],"_revision_number":12},{"id":"c59084e898c5c0ab74fae128740ea349185eeb8f","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 20:23:21.000000000","message":"Uploaded patch set 13.","accounts_in_message":[],"_revision_number":13},{"id":"3fe2e77b0dc978a766e9d007a38e7d139c0311b4","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-16 21:00:54.000000000","message":"Patch Set 13: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15054/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14286/ : SUCCESS","accounts_in_message":[],"_revision_number":13},{"id":"947b1108f74895366d68f83deb6047749e14a9b3","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 21:26:03.000000000","message":"Uploaded patch set 14.","accounts_in_message":[],"_revision_number":14},{"id":"5fdf90e7ab89018af9cb0b36993f2746f175500e","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-16 21:26:27.000000000","message":"Patch Set 14: Code-Review+1","accounts_in_message":[],"_revision_number":14},{"id":"7b5be244885a90241fe4f7fa530f0ad45cc59b4d","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-16 22:04:39.000000000","message":"Patch Set 14: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/15059/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14288/ : SUCCESS","accounts_in_message":[],"_revision_number":14},{"id":"1d4e0a742ead8471513ad58dc9ba1a341c7aeece","author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"real_author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"date":"2021-08-26 06:50:33.000000000","message":"Patch Set 14:\n\n(1 comment)","accounts_in_message":[],"_revision_number":14},{"id":"47e24f53fffb44f76c2d40a2a81d7a672ce3dcac","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-26 12:50:13.000000000","message":"Uploaded patch set 15.","accounts_in_message":[],"_revision_number":15},{"id":"1a68c910a7996027f82a5e9e4d2099dae68e2943","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-08-26 12:52:01.000000000","message":"Patch Set 15:\n\n(1 comment)","accounts_in_message":[],"_revision_number":15},{"id":"c448089488142254953a27fda9455bd245be33ff","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-08-26 13:02:35.000000000","message":"Patch Set 15: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/15140/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/14365/ : SUCCESS","accounts_in_message":[],"_revision_number":15},{"id":"5d1aa6efc391d51a9a525debbcfbf232973d9e27","author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"real_author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"date":"2021-08-26 13:11:13.000000000","message":"Patch Set 15: Code-Review+2","accounts_in_message":[],"_revision_number":15},{"id":"0fdd999d6bd8ea3de6bf095a5e46a8f5f868455c","tag":"autogenerated:gerrit:merged","author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"real_author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"date":"2021-08-26 13:13:02.000000000","message":"Change has been successfully cherry-picked as 6c1e1a212a8c044ae778c526851fe909bf219e90","accounts_in_message":[],"_revision_number":16}],"current_revision":"6c1e1a212a8c044ae778c526851fe909bf219e90","revisions":{"6c1e1a212a8c044ae778c526851fe909bf219e90":{"kind":"NO_CODE_CHANGE","_number":16,"created":"2021-08-26 13:13:02.000000000","uploader":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"ref":"refs/changes/50/6050/16","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/16","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/16 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/16 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/16 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/16 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/16","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/16 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"64fbd607874bbe9726cf1d09c2cbf547bd9d804c","subject":"flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Oleksij Rempel","email":"linux@rempel-privat.de","date":"2021-08-26 13:13:02.000000000","tz":0},"subject":"flash/stm32l4x: add support of STM32WL5x dual core","message":"flash/stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,\nto solve this read the UID64 (IEEE 64-bit unique device ID register)\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\nReviewed-on: https://review.openocd.org/c/openocd/+/6050\nTested-by: jenkins\nReviewed-by: Oleksij Rempel \u003clinux@rempel-privat.de\u003e\n"}},"be42da031a55390223ae3f74459d87b9570a9e4a":{"kind":"REWORK","_number":13,"created":"2021-08-16 20:23:21.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/13","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/13","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/13 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/13 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/13 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/13 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/13","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/13 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e011a78672a8f4ec02b3dedc3b03fc1e79ce884b","subject":"flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-16 20:19:34.000000000","tz":60},"subject":"flash/stm32l4x: add support of STM32WL5x dual core","message":"flash/stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,\nto solve this read the UID64 (IEEE 64-bit unique device ID register)\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"92bc04103fd9746e4e7176e2ceded1ab0927c644":{"kind":"REWORK","_number":12,"created":"2021-08-16 15:43:00.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/12","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/12","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/12 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/12 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/12 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/12 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/12","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/12 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e011a78672a8f4ec02b3dedc3b03fc1e79ce884b","subject":"flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-16 15:41:41.000000000","tz":60},"subject":"flash/stm32l4x: add support of STM32WL5x dual core","message":"flash/stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,\nto solve this read the UID64 (IEEE 64-bit unique device ID register)\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"233cd2c1ab39d3f3e3a459c6a0c49e3990010893":{"kind":"REWORK","_number":15,"created":"2021-08-26 12:50:13.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/15","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/15","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/15 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/15 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/15 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/15 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/15","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/15 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"64fbd607874bbe9726cf1d09c2cbf547bd9d804c","subject":"flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-26 12:49:56.000000000","tz":60},"subject":"flash/stm32l4x: add support of STM32WL5x dual core","message":"flash/stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,\nto solve this read the UID64 (IEEE 64-bit unique device ID register)\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"00b9d3049337e2aa06f10f37073ef3e831e1b542":{"kind":"REWORK","_number":14,"created":"2021-08-16 21:26:03.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/14","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/14","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/14 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/14 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/14 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/14 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/14","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/14 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"e011a78672a8f4ec02b3dedc3b03fc1e79ce884b","subject":"flash/stm32l4x: prevent undefined behavior warnings caused by signed integer operations"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-16 21:25:48.000000000","tz":60},"subject":"flash/stm32l4x: add support of STM32WL5x dual core","message":"flash/stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,\nto solve this read the UID64 (IEEE 64-bit unique device ID register)\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"8fbf405c5dfa37547dcf927d8471d89488dacfff":{"kind":"REWORK","_number":9,"created":"2021-08-13 23:42:53.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/9","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/9","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/9 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/9 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/9 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/9 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/9","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/9 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"fb5686f1fd652bfa3fc5e7b9854fc70519a2a34e","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-13 23:42:39.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"9b53d47381440e7bb2426459c656a69148073b97":{"kind":"TRIVIAL_REBASE","_number":8,"created":"2021-03-17 12:31:48.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/8 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"cd4dfcb28c4949d312e7d4f1bb5a6081aca5fdb2","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-03-17 12:22:29.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"168d49298df8221978be4bbfd21740c9f881c7b8":{"kind":"TRIVIAL_REBASE","_number":11,"created":"2021-08-15 22:54:38.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/11","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/11","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/11 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/11 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/11 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/11 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/11","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/11 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"50678fc363949f7745180d671a13659683b55798","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-15 22:53:35.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"59db83f164ae9242ecad33c5789260e3b9932b07":{"kind":"TRIVIAL_REBASE","_number":10,"created":"2021-08-14 13:39:41.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/10","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/10","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/10 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/10 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/10 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/10 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/10","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/10 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6979106f5fe62accae745d0040511977263e1c43","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-08-14 12:59:57.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"6fe11bf7c8b8045feb397268cb4d24b70e04968b":{"kind":"REWORK","_number":5,"created":"2021-03-16 02:25:12.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/5 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"0fed10460a849f33b526db9d8205f1512f925c7b","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-03-16 02:24:23.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"e07a6551a6729743378d421781053829e10f52c1":{"kind":"REWORK","_number":4,"created":"2021-02-14 21:20:19.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/4 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"92ab281543d5fc52743b2d778716153920f211c8","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-14 21:12:18.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@st.com\u003e\n"}},"61977bad64c46e96a39187dd38a3ee38ef65ee9f":{"kind":"TRIVIAL_REBASE","_number":7,"created":"2021-03-16 22:50:41.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/7 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/7 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/7 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/7 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/7","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/7 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"585b79dd516c3683b6bb44b5c51587058b9bbd22","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-03-16 22:50:25.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"6db549b5229e3fbbc4f20af8807c1b6198da524a":{"kind":"TRIVIAL_REBASE","_number":6,"created":"2021-03-16 11:04:13.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/6 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"cd7f735dacc98c52a6ff894b332fb01ee42fc46a","subject":"flash/stm32l4x: add optional flash bank arguments for DBGMCU_IDCODE"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","date":"2021-03-16 10:57:27.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\naccording the RM0453, the second core  have a different Flash CR and SR\nregisters for flash operations (called C2CR and C2SR).\nso we need to a different flash_regs than older L4 devices.\n@see stm32wl_cpu2_flash_regs\n\nthe C2CR register don\u0027t contain LOCK and OPTLOCK bits, and this explain\nthe addition of new register index called STM32_FLASH_CR_WLK_INDEX to\nlook-up the CR with lock, to be used in locking/unlocking the flash.\n\nnote: using the second core (CM0+) on AP1 we can\u0027t read the MCU IDCODE,\nso we pass it in the flash bank creation:\n  flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 0xffff6497\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@gmail.com\u003e\n"}},"acafce3c7c59fe486e30c2f20f9773ca53854ca5":{"kind":"REWORK","_number":1,"created":"2021-02-05 08:29:02.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/1 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1578a3b0394d4f44282ad4447bf353c052ba525d","subject":"flash/stm32l4x: add support of STM32G0Bx/G0Cx devices"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-05 00:19:50.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@st.com\u003e\n"}},"6300e1ba58d191a26ddff99fd2459a26a105a34f":{"kind":"NO_CODE_CHANGE","_number":3,"created":"2021-02-05 08:46:26.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/3 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1578a3b0394d4f44282ad4447bf353c052ba525d","subject":"flash/stm32l4x: add support of STM32G0Bx/G0Cx devices"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-05 08:46:15.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core [WIP]","message":"stm32l4x: add support of STM32WL5x dual core [WIP]\n\nWIP:\nflash probe using cpu1 (Cortex-M0+) will fail because cpu1 can\u0027t read\nDBGMCU registers.\npossible solutions:\n - pass a dummy MCU IDCODE as optional argument to flash banks in cfg files\n   cons: the revision ID could be incorrect\n - pass cpu0 or ap0 (to create in this case) as optional argument to flash\n   banks in cfg files\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@st.com\u003e\n"}},"458dd38a24164dd42791df0a168c94f1b9a8b0ba":{"kind":"REWORK","_number":2,"created":"2021-02-05 08:35:49.000000000","uploader":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"ref":"refs/changes/50/6050/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/50/6050/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/2 \u0026\u0026 git checkout -b change-6050 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/50/6050/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/50/6050/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1578a3b0394d4f44282ad4447bf353c052ba525d","subject":"flash/stm32l4x: add support of STM32G0Bx/G0Cx devices"}],"author":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-04 21:43:52.000000000","tz":60},"committer":{"name":"Tarek BOCHKATI","email":"tarek.bouchkati@st.com","date":"2021-02-05 08:35:35.000000000","tz":60},"subject":"stm32l4x: add support of STM32WL5x dual core","message":"stm32l4x: add support of STM32WL5x dual core\n\nChange-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4\nSigned-off-by: Tarek BOCHKATI \u003ctarek.bouchkati@st.com\u003e\n"}}},"requirements":[],"submit_records":[{"status":"CLOSED","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dCustom-Rule","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dCustom-Rule"],"failing_atoms":[]}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dCustom-Rule","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dCustom-Rule"],"failing_atoms":[]}}]}