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Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-03-05 18:22:39.000000000","message":"Patch Set 3: Code-Review+1","accounts_in_message":[],"_revision_number":3},{"id":"1627ae53d18305f7ee62780764c1b2f9d80daccf","author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"real_author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"date":"2021-03-10 10:57:22.000000000","message":"Patch Set 3: Code-Review-1\n\nYou forgot to clear the SSTICKYORUN bit of CTRL/STAT in case of FAULT response of JTAG","accounts_in_message":[],"_revision_number":3},{"id":"57a10245e05ba91f74bef7c531367be18b5f0b1f","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-03-10 21:49:09.000000000","message":"Patch Set 3: -Code-Review\n\n(2 comments)\n\nSylvain, thanks for the review. For the added changes it\u0027s not clear to me where we forgot to clear the STICKYORUN bit of CTRL/STAT in case of JTAG FAULT response. There are two places identified in code we didn\u0027t modify, but have a patch for that which unfortunately didn\u0027t make it into this review. I\u0027ve identified the lines in question. If those are the two lines you\u0027re referring to, let me know and I\u0027ll bring the bug fix commit into this review. Otherwise you\u0027ll need to point them out to me. Thanks.","accounts_in_message":[],"_revision_number":3},{"id":"5f8d4ae65483a5b9cc7a021ab9d4bbcf4b8f6291","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-03-11 15:14:51.000000000","message":"Patch Set 3:\n\nSylvain - The first patch submitted for ADIv6 was difficult to review due to its size. As a result, we separated unrelated features/bug fixes into separate patches. The SSTICKYORUN bugfix was not deemed specific to the ADIv6 feature since it was also missing in the original ADIv5 support. We do have an unsubmitted patch to address this. Once the SSTICKYORUN bugfix patch is internally approved and submitted upstream, I\u0027ll post a link to it here. If this doesn\u0027t address your concern, please let me know. Thanks.","accounts_in_message":[],"_revision_number":3},{"id":"65c9d5d0cdcd4e01c7b48b665880aa9bf3133c61","author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"real_author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"date":"2021-03-11 15:58:44.000000000","message":"Patch Set 3:\n\nDaniel, correct me if I\u0027m wrong but what I understand from the adi specs is that in v5, overrun happens only on WAIT response, whereas in v6, it can also happen on FAULT response.\nv5 openocd code handles overrun only in WAIT case, not in FAULT, that\u0027s why I think you should add overrun handling for v6 on FAULT case","accounts_in_message":[],"_revision_number":3},{"id":"64c35c0d1cae13b5a6b56d500a8c17498a9431dd","author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"real_author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"date":"2021-03-11 16:02:23.000000000","message":"Patch Set 3:\n\nAnd yes, the two lines you pointed are the ones I was talking about","accounts_in_message":[],"_revision_number":3},{"id":"5ff62f90a0e95235d643719f5db860ac7227825d","author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"real_author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"date":"2021-03-11 23:24:15.000000000","message":"Patch Set 3:\n\nSylvain, Thanks for the review comments. I\u0027m not sure if your concern is with: clearing of the stickyorun bit, checking that it is on, or both. We believe we have a patch for the clearing of the bit which existed in the original ADIv5 code. However, if you are concerned about the checking of the bit, perhaps we are not reading the ARM ADI specification the same way. In the overrun section of the ADIV6 spec under JTAG-DP, it states:\nIf the response to any transaction is not OK, the Sticky Overrun flag,\nCTRL/STAT.STICKYORUN, is set to 0b1.\nThe response to a transaction is WAIT until the previous AP transaction is complete.\nOnce the AP transaction has completed, the response is FAULT. \n\nSo I read this to mean that if we are running in overrun detection mode, we will always see a WAIT response prior to the FAULT response. Is that your interpretation? If so, I believe we are only concerned with clearing the bit rather than checking to see if it\u0027s on (since that is handled in the WAIT checking code). Your additional comments will be appreciated. Thanks.","accounts_in_message":[],"_revision_number":3},{"id":"8fbfcec2d819f82667e15079f978088335d2a9b4","author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"real_author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"date":"2021-03-12 09:27:29.000000000","message":"Patch Set 3:\n\nI understand your point, however in my tests, I\u0027ve got a FAULT response without a preceding WAIT and a STICKYORUN bit set to 1 (Note that I also have SSTICKYERR set to 1, may be this is the key point). The spec is ambiguous because there is the sentence \"If the response to any transaction is not OK, the Sticky Overrun flag,\nCTRL/STAT.STICKYORUN, is set to 0b1 .\" but the rest of the paragraph only talks about WAIT/FAULT stages.","accounts_in_message":[],"_revision_number":3},{"id":"f065bee33ad8b05445246b39e523419ec54a1ed6","author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"real_author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"date":"2021-03-12 15:09:51.000000000","message":"Patch Set 3:\n\nSylvain, Definitely agree that the spec leaves much to the imagination and very ambiguous. I\u0027m hoping you can provide insight on the particular situation you are encountering. \nNote that the ctrl_stat reg is setup with errmode off and overrun detection enabled. Here\u0027s my understanding/interpretation:\nThe ADIv6 spec indicates that stickyorun gets set if any non-ok response (which would be WAIT or FAULT) is encountered. That means the only real overrun condition (where a group of commands gets \u0027stalled\u0027 due to one operation taking an excessive time to complete) is when a WAIT response is encountered. Subsequent FAULT responses following the WAIT are recoverable operations since they really didn\u0027t get exercised). So that\u0027s why function jtagdp_overrun_check is keying off of the WAIT response, not the stickyorun bit. \nIn the case where there is a true FAULT response, the stickyorun bit willalways be set but we are not in an overrun state. There is not much to do other than clear all the sticky bits that are on (provided in a subsequent patch) and either try the failing operation again and/or surface the failure.\nI suspect that in the error condition you encountered, the operation is actually failing (due to a bad address being used, power is not up, etc.) and not recoverable. Is that the case? Is there some code change  you envision that would more cleanly handle the condition you are encountering? Perhaps the clearing of stickyorun for a FAULT response is all you are looking for?","accounts_in_message":[],"_revision_number":3},{"id":"04345a2f466998ebbf0762f7d0917a7001c7367d","author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"real_author":{"_account_id":1001824,"name":"Sylvain Chouleur","email":"sylvain.chouleur@gmail.com","username":"schouleu"},"date":"2021-03-12 16:46:47.000000000","message":"Patch Set 3: Code-Review+1\n\nAlright, I\u0027m ok with a subsequent patch to clear the overrun bit in non-WAIT case","accounts_in_message":[],"_revision_number":3},{"id":"2ad7fd6972cf86bb0c62be72efe8dba03d08cfa7","author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"real_author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"date":"2021-03-22 14:00:03.000000000","message":"Patch Set 3: Code-Review+1\n\nSylvain,\nI took the added step of reaching out to ARM to get their input on FAULT, STICKYORUN, and STICKYERR settings. They confirmed the following: \nIf I receive a FAULT response from a transaction and there was no previous WAIT response encountered, there will be a STICKYORUN bit set along with some other sticky bit (STICKYERR, STICKYCMP, or WDATAERR in the case of SW-DP) that will be on. In other words, seeing \u0027FAULT + STICKYORUN + no other sticky error bit on\u0027 is only possible if a previous WAIT response was generated.","accounts_in_message":[],"_revision_number":3},{"id":"9605a77c2113983e1f0ec8176d5827bd8be0df10","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-03-22 16:57:12.000000000","message":"Patch Set 3: Code-Review+1\n\nPatch http://openocd.zylin.com/#/c/6119/ clears stickyorun in addition to stickyerr when stickyerr is checked and during OpenOCD init. Patch 6119 applies to both ADIv5 and ADIv6 OpenOCD support.","accounts_in_message":[],"_revision_number":3},{"id":"f14068c3c91a53856e8cc38029986eaee1d24dda","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-05-13 13:57:59.000000000","message":"Uploaded patch set 4.","accounts_in_message":[],"_revision_number":4},{"id":"63aed2c28a9c3bd8788fdb59a8919ea7736ea177","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-05-13 16:18:56.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14518/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13772/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"af7831410b0f400e10ad97004541a557526af786","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-05-16 22:59:45.000000000","message":"Patch Set 4:\n\n(4 comments)","accounts_in_message":[],"_revision_number":4},{"id":"380fb9520478b8b5dc7b6818ca6c5b804b492e23","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-05-17 06:34:30.000000000","message":"Patch Set 4:\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"13849be184b9fc28cc69c4d1b6603e3b258f62bd","author":{"_account_id":1001890,"name":"tbauer01","username":"tbauer01"},"real_author":{"_account_id":1001890,"name":"tbauer01","username":"tbauer01"},"date":"2021-05-18 23:15:14.000000000","message":"Patch Set 4:\n\n(2 comments)","accounts_in_message":[],"_revision_number":4},{"id":"092d25dd2f512362ce15879ba06ceaac3cae52ab","author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"real_author":{"_account_id":1001726,"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","username":"kburke-ampere"},"date":"2021-05-24 14:15:55.000000000","message":"Patch Set 4:\n\n(1 comment)\n\nPrototypes were used in an effort to group all new functions at the end of the file.","accounts_in_message":[],"_revision_number":4},{"id":"badcb776ac519c9224d00adbc57d27da44cfac3c","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-05-27 22:33:10.000000000","message":"Uploaded patch set 5.","accounts_in_message":[],"_revision_number":5},{"id":"cf0728d8ccecbe05ca7dfe712b9d41f498f3fcaa","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-05-27 23:03:23.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14655/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13905/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"b361e7e62066852dc674c6c41664976123780766","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-05-27 23:22:07.000000000","message":"Patch Set 4:\n\n(4 comments)\n\nPatchset 5 addresses the AP reg macro readability and dap_instance_init() function call issues.","accounts_in_message":[],"_revision_number":4},{"id":"601bbf7bdc6ff2a7ebb7ce810347f6d4a9159033","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-06-02 22:13:35.000000000","message":"Uploaded patch set 6.","accounts_in_message":[],"_revision_number":6},{"id":"ae97b17b08ebf9f9a8df62401a76656888434395","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-06-02 22:20:53.000000000","message":"Patch Set 6:\n\nUpdated patchset to pick up any ADIv6 updates due to the changes made to the underlying LPAE patch.","accounts_in_message":[],"_revision_number":6},{"id":"b54ddfe0ae83d259c55a5d5f11eeadeabe620e7b","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-06-02 22:46:57.000000000","message":"Patch Set 6: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14672/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/13922/ : SUCCESS","accounts_in_message":[],"_revision_number":6},{"id":"7f0d0d3ff6899a0cae68a88913bf8341d7a803d5","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-06-05 21:59:23.000000000","message":"Patch Set 6:\n\nIn adiv5 we have by design at most 256 AP.\nWith adiv6, each AP is aligned at 4K and SELECT is 64bits, so we have max 2^52 possible AP!\nWith adiv5 we loop on all the AP to perform some autodetection. It becomes prohibitive on adiv6.\nIn this code you stick at the existing 256 dap.ap[] as places to hold AP info, by initializing odd base_addr.\nI cannot find any better way to handle this.\nDo you have any plan to improve this?","accounts_in_message":[],"_revision_number":6},{"id":"0588865bfa1851dc12031eeaab6c983c7f03ea98","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-06-07 19:09:35.000000000","message":"Patch Set 6: Code-Review+1\n\nWe have no plans to change this unless a better idea is proposed. To maintain backwards compatibility with ADIv5 and keep the code changes at a minimum to support ADIv6, our thoughts are that using the existing 256 dap.ap[] array to hold the ADIv6 AP information provides an adequate solution. In the designs we have seen and plan to provide, there is nothing close to 256 APs so 256 seems to be a very reasonable limit for now and in the foreseeable future.","accounts_in_message":[],"_revision_number":6},{"id":"540eb63f469e6e107fb96e44b01418c7504250d0","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-08 15:33:29.000000000","message":"Patch Set 6:\n\n@Antonio: Is there anything you are waiting on from Ampere for the ADIv6 patch? We would prefer to get ADIv6 included in the upcoming OpenOCD 0.12.0 release tagged for October 2021 if possible.","accounts_in_message":[],"_revision_number":6},{"id":"7bf85b44ec5c09750d436905ad7871c5eb67a7c2","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-08 16:23:52.000000000","message":"Patch Set 6:\n\n(1 comment)\n\nLooks like this series is much more complete than my hacked attempts at parsing Class 9 type ROMs:\n\nhttp://openocd.zylin.com/#/c/6359/\nhttp://openocd.zylin.com/#/c/6360/1","accounts_in_message":[],"_revision_number":6},{"id":"4deffd7d383f1171db9c1e92714fc7d6f9734051","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-07-08 16:54:15.000000000","message":"Patch Set 6:\n\n@Daniel: I have got access to an ADIv6 platform for just few hours and I quickly tested this patch. I\u0027m not happy on how ADIv6 AP are managed. AP that are not mem-AP cannot be described. I\u0027m considering other ways, still thinking over ...\nI will get the platform for longer time during August. Let\u0027s see ...\nSure, I\u0027m also willing to get this merged in v0.12.0! \n\n@Florian: I have never found in a single document or source a full list of ARM PIDs. Only info scattered across several documents. Very annoying!\nAny new PID/description you can add to the list is welcome.\nWould be also good adding in a comment, beside the new table entry, where the value comes from: doc XXX revY, scan from device ZZZ, ...","accounts_in_message":[],"_revision_number":6},{"id":"134dfb09ae52161f551679388ebd3870f04c1c4e","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-08 19:32:00.000000000","message":"Patch Set 6:\n\n(1 comment)\n\n@Florian: See posted comment. If it doesn\u0027t address your question, let me know. Thanks.\n\n@Antonio: Thanks for the update and I understand your concern. We don\u0027t have the ability to test other APs besides MEM-APs. We\u0027re not able to code JTAG-AP support since we have no platform to test it on. I\u0027ll review the JTAG-AP section of the ADIv6 spec and see if the current approach for MEM-APs can be extended to support JTAG-APs. If you have any ideas let us know.","accounts_in_message":[],"_revision_number":6},{"id":"d82e4295445ce3edf1af72a9dda03631d05c77b5","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-08 19:34:32.000000000","message":"Patch Set 6:\n\n\u003e (1 comment)\n \u003e \n \u003e @Florian: See posted comment. If it doesn\u0027t address your question,\n \u003e let me know. Thanks.\n\nIt does, I conflated number of entries versus maximum offset, my bad.","accounts_in_message":[],"_revision_number":6},{"id":"b4af9a2ae8439954b55713c336709a812f7de5b3","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-07-09 17:30:16.000000000","message":"Patch Set 6:\n\n@Daniel: I\u0027m not talking about JTAG AP.\nIn openocd ADIv5 we have DAP, APs, and then on APs we can add targets, either mem_ap or cortex_whatever.\nAPs should be usable without the need to add a target.\nThis is important when we \"analyze\" a not fully documented device, and we have no idea about how APs are organized.\nWith current code proposal ADIv6 we loose the AP control (command \u0027\u003cdapname\u003e apreg ...\u0027) if we do not add a target to the AP.\nIn the specific of the SoC I will use, there is a proprietary AP that controls the power management of the soc. In dedicated AP registers (not mem_ap) I can power on/off the cores. Without direct AP access I cannot start a debug, I cannot see the targets, most of the mem_ap are powered down.\nI\u0027m not asking you any action, for the moment. I first want to check better my SoC.","accounts_in_message":[],"_revision_number":6},{"id":"ed75a78d17e49af10eda68c6238075ac4fd6803e","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-13 18:19:33.000000000","message":"Patch Set 6:\n\nI tested this patch with a Cortex-A76 based system and it looks like we still need my patches to do a recursive lookup of the nested ROM tables. With this patch applied, here is the dap info output:\n\n\u003e dap info\nAP ID register 0x24770002\n        Type is MEM-AP APB\nMEM-AP BASE 0x80080003\n        Valid ROM table present\n                Component base address 0x80080000\n                Peripheral ID 0x01000bfa97\n                Designer is 0x1bf, Broadcom\n                Part is 0xa97, Unrecognized\n                Component class is 0x1, ROM table\n                MEMTYPE system memory not present: dedicated debug bus\n        ROMTABLE[0x0] \u003d 0xfff80003\n                Component base address 0x180000000\n                Peripheral ID 0x04007bb4e4\n                Designer is 0x4bb, ARM Ltd\n                Part is 0x4e4, DSU ROM v8 Debug (ROM Table)\n                Component class is 0x9, CoreSight component\n                Type is 0x00, Miscellaneous, other\n        ROMTABLE[0x4] \u003d 0x0\n                End of ROM table\n\n\nwhereas with my patches we have what we expect:\n\n\u003e dap info\nAP ID register 0x24770002\n        Type is MEM-AP APB\nMEM-AP BASE 0x80080003\n        Valid ROM table present\n                Component base address 0x80080000\n                Peripheral ID 0x01000bfa97\n                Designer is 0x1bf, Broadcom\n                Part is 0xa97, Unrecognized\n                Component class is 0x1, ROM table\n                MEMTYPE system memory not present: dedicated debug bus\n        ROMTABLE[0x0] \u003d 0xfff80003\n                Component base address 0x180000000\n                Peripheral ID 0x04007bb4e4\n                Designer is 0x4bb, ARM Ltd\n                Part is 0x4e4, Cortex-A76 ROM (ROM Table)\n                Component class is 0x9, CoreSight component\n                Type is 0x00, Miscellaneous, other\n        [L01] ROMTABLE[0x0] \u003d 0x10003\n                Component base address 0x180010000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x15, Debug Logic, Processor\n        [L01] ROMTABLE[0x4] \u003d 0x20003\n                Component base address 0x180020000\n                Peripheral ID 0x04007bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x14, Debug Control, Trigger Matrix\n        [L01] ROMTABLE[0x8] \u003d 0x30003\n                Component base address 0x180030000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x16, Performance Monitor, Processor\n        [L01] ROMTABLE[0xc] \u003d 0x40003\n                Component base address 0x180040000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x13, Trace Source, Processor\n        [L01] ROMTABLE[0x10] \u003d 0xc0002\n                Component base address 0x1800c0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x14] \u003d 0xd0006\n                Component base address 0x1800d0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x18] \u003d 0xe0006\n                Component base address 0x1800e0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x1c] \u003d 0x110003\n                Component base address 0x180110000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x15, Debug Logic, Processor\n        [L01] ROMTABLE[0x20] \u003d 0x120003\n                Component base address 0x180120000\n                Peripheral ID 0x04007bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x14, Debug Control, Trigger Matrix\n        [L01] ROMTABLE[0x24] \u003d 0x130003\n                Component base address 0x180130000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x16, Performance Monitor, Processor\n        [L01] ROMTABLE[0x28] \u003d 0x140003\n                Component base address 0x180140000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x13, Trace Source, Processor\n        [L01] ROMTABLE[0x2c] \u003d 0x1c0002\n                Component base address 0x1801c0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x30] \u003d 0x210003\n                Component base address 0x180210000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x15, Debug Logic, Processor\n        [L01] ROMTABLE[0x34] \u003d 0x220003\n                Component base address 0x180220000\n                Peripheral ID 0x04007bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x14, Debug Control, Trigger Matrix\n        [L01] ROMTABLE[0x38] \u003d 0x230003\n                Component base address 0x180230000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x16, Performance Monitor, Processor\n        [L01] ROMTABLE[0x3c] \u003d 0x240003\n                Component base address 0x180240000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x13, Trace Source, Processor\n        [L01] ROMTABLE[0x40] \u003d 0x2c0002\n                Component base address 0x1802c0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x44] \u003d 0x310003\n                Component base address 0x180310000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x15, Debug Logic, Processor\n        [L01] ROMTABLE[0x48] \u003d 0x320003\n                Component base address 0x180320000\n                Peripheral ID 0x04007bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x14, Debug Control, Trigger Matrix\n        [L01] ROMTABLE[0x4c] \u003d 0x330003\n                Component base address 0x180330000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x16, Performance Monitor, Processor\n        [L01] ROMTABLE[0x50] \u003d 0x340003\n                Component base address 0x180340000\n                Peripheral ID 0x04005bbd0b\n                Designer is 0x4bb, ARM Ltd\n                Part is 0xd0b, Cortex-A76 Debug (Debug Unit)\n                Component class is 0x9, CoreSight component\n                Type is 0x13, Trace Source, Processor\n        [L01] ROMTABLE[0x54] \u003d 0x3c0002\n                Component base address 0x1803c0000\n                Invalid CID 0x00000000\n        [L01] ROMTABLE[0x58] \u003d 0x0\n        [L01]   End of ROM table\n        ROMTABLE[0x4] \u003d 0x0\n                End of ROM table\n\n\u003e","accounts_in_message":[],"_revision_number":6},{"id":"26e0c80a0cbdcdf0277e65e7d54c8410cde17bfe","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-13 18:46:02.000000000","message":"Patch Set 6:\n\n@Florian: Hello and thanks for your feedback. I\u0027ll look into this further, but to get started I need some clarification on the nested ROM table issue and what the default behavior is expected to be... In your situation are the nested ROM tables located off the same DAP access port? I expect this code patch to recurse all ROM tables located from the same access port, but maybe I\u0027m not doing that correctly or maybe that is not the expected behavior. For ADIv6 in our design, Access Port 0 references the Primary ROM table located inside the DAP. A \"dap info\" command when the current selected AP \u003d 0 will dump only the Primary ROM table. Continuing that trend, a \"dap info\" command when current selected AP \u003d 2 will dump the secondary ROM table contained at AP 2. If the Primary ROM table at AP0 links to a secondary ROM table at AP2, dumping the Primary ROM table with command \"dap info 0\" will only display the Primary ROM table and not the secondary ROM table. To get the Secondary ROM table, command \"dap info 2\" must be used. Let me know if this is not the desired behavior or if you\u0027re experiencing some other issue.","accounts_in_message":[],"_revision_number":6},{"id":"234bfcf65b4d5909b60f2d0b40c33b5ed174fad4","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-13 22:21:29.000000000","message":"Patch Set 6:\n\n@Florian: After thinking about it more, a \"dap info 1\" should display the missing ROM table entries for your scenario. What I\u0027m not sure about is whether a \"dap info 0\" command needs to recursively display linked ROM table entries contained at \"dap info 1\" (AP 1).","accounts_in_message":[],"_revision_number":6},{"id":"63f60eb6309ac9b997531a6924ced0e699405827","author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"real_author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"date":"2021-07-14 09:32:52.000000000","message":"Patch Set 6: Code-Review-1\n\n(12 comments)\n\nPlease make sure your patch follows the C coding style. Probably I didn\u0027t catch everything","accounts_in_message":[],"_revision_number":6},{"id":"fd8bb9d0e57a32332cd7743c589a343144f67115","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-14 16:24:49.000000000","message":"Patch Set 6:\n\n\u003e @Florian: After thinking about it more, a \"dap info 1\" should\n \u003e display the missing ROM table entries for your scenario. What I\u0027m\n \u003e not sure about is whether a \"dap info 0\" command needs to\n \u003e recursively display linked ROM table entries contained at \"dap info\n \u003e 1\" (AP 1).\n\nIt does not appear to work:\n\n\u003e dap info 0\nAP ID register 0x24770002\n        Type is MEM-AP APB\nMEM-AP BASE 0x80080003\n        Valid ROM table present\n                Component base address 0x80080000\n                Peripheral ID 0x01000bfa97\n                Designer is 0x1bf, Broadcom\n                Part is 0xa97, Unrecognized\n                Component class is 0x1, ROM table\n                MEMTYPE system memory not present: dedicated debug bus\n        ROMTABLE[0x0] \u003d 0xfff80003\n                Component base address 0x180000000\n                Peripheral ID 0x04007bb4e4\n                Designer is 0x4bb, ARM Ltd\n                Part is 0x4e4, DSU ROM v8 Debug (ROM Table)\n                Component class is 0x9, CoreSight component\n                Type is 0x00, Miscellaneous, other\n        ROMTABLE[0x4] \u003d 0x0\n                End of ROM table\n\n\u003e dap info 1\nAP ID register 0x00000000\nNo AP found at this ap 0x1\n\u003e","accounts_in_message":[],"_revision_number":6},{"id":"38b3cb111a6165c19905c0a875812b0682757e2f","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-14 17:31:07.000000000","message":"Patch Set 6: -Code-Review\n\n@Florian: Thanks for the update and I see what\u0027s going on. I\u0027ll address the issue soon.","accounts_in_message":[],"_revision_number":6},{"id":"f7a31d7c01d812348a3c1b591cd335d8ad663d9f","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-15 20:17:41.000000000","message":"Patch Set 6:\n\n\u003e @Florian: Thanks for the update and I see what\u0027s going on. I\u0027ll\n \u003e address the issue soon.\n\nNo worries, thanks! FWIW, it looks like ADIv5 is still used on that system.","accounts_in_message":[],"_revision_number":6},{"id":"0bdd6df5d5cc96504dd8c53218efe7acec281099","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-24 03:16:20.000000000","message":"Uploaded patch set 7.","accounts_in_message":[],"_revision_number":7},{"id":"ec381eedf2750f60ea3ad9cd614490239cd187c1","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-24 03:50:40.000000000","message":"Patch Set 7: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14889/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14135/ : SUCCESS","accounts_in_message":[],"_revision_number":7},{"id":"0e98ca12d37bc2784f1f1613012d5b9efebd2785","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-24 04:04:46.000000000","message":"Patch Set 6:\n\n(12 comments)\n\n@Florian: I hope patchset 7 addresses the issue you reported. To provide some background, this patch was originally created to add ARM ADIv6 DAP support and our focus was mainly on ADIv6. At the time Ampere thought it was best to leave as much original OpenOCD ADIv5 implementation as possible untouched and branch off with separate functions for the ADIv6 support. Our concern was that if we implemented ADIv6 support inline with the existing ADIv5 implementation, we could inadvertently break ADIv5 functionality for legacy products. We have limited systems supporting ADIv5 and are unable to test many legacy ADIv5 products. For ADIv6, Ampere implemented support for Class 9 ROM Tables and 64-bit addressable MEM-APs. The existing OpenOCD ADIv5 support misses a few of these features and I think this is the issue you hit. As a result, we revisited our initial decision and decided to change course. Patchset 7 abandons separate ADIv6 routines and folds the ADIv6 support back into the pre-existing ADIv5 implementation. The advantage of this approach is now OpenOCD supports Class 9 ROM table and 64-bit MEM-APs for both ADIv5 and v6 products. The disadvantage is due diligence must be performed to verify ADIv5 support remains fully intact. I tested this patch on two ADIv6 and two ADIv5 systems as documented in the Commit message. Let me know if this patchset resolves the issue you observed.\n\nMarc: Thanks for the code review. I made the fixes you mentioned. I also searched through the code and fixed up the brackets as necessary. Let me know if you see anything else that needs updating.\n\nNote: This patchset uses a newer version of master needed for this patch to properly build.","accounts_in_message":[],"_revision_number":6},{"id":"c8426de4618a9c70708162a0cf54fc0e1379eaec","author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"real_author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"date":"2021-07-24 12:34:08.000000000","message":"Patch Set 7:\n\n(1 comment)\n\nthanks Daniel for this great contribution !","accounts_in_message":[],"_revision_number":7},{"id":"6074f09efaf3180255062666ab12d59f2fb4d222","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-27 12:56:07.000000000","message":"Uploaded patch set 8.","accounts_in_message":[],"_revision_number":8},{"id":"b70855f1e2e297fa36bcc005e89d0f96952c5f7c","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-27 12:59:04.000000000","message":"Patch Set 8:\n\nRebased commit to resolve path conflict.\n\n@Tarek: Thanks for the support. I\u0027ll update doc/openocd.texi in the next patchset.","accounts_in_message":[],"_revision_number":8},{"id":"cd0813195752ec76b6f4dcb18773877f87566581","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2021-07-27 13:29:18.000000000","message":"Patch Set 8: Verified+1\n\nBuild Successful \n\nhttp://build.openocd.org/job/openocd-gerrit/14892/ : SUCCESS\n\nhttp://build.openocd.org/job/openocd-gerrit-build/14138/ : SUCCESS","accounts_in_message":[],"_revision_number":8},{"id":"f6a2f97c52a67aad057bb8238f6d60f065528d35","author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"real_author":{"_account_id":1001651,"name":"Florian Fainelli","email":"f.fainelli@gmail.com","username":"ffainelli"},"date":"2021-07-27 18:15:12.000000000","message":"Patch Set 8: Code-Review+1\n\n@Daniel, thanks this works nicely and the \"dap info\" on my system looks the same as with my hacked up approach.","accounts_in_message":[],"_revision_number":8},{"id":"ad411eb772fae68a433ca8bace29546f5edd3bfb","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-07-31 10:10:52.000000000","message":"Patch Set 8:\n\n\u003e Patchset 7 abandons separate ADIv6 routines and folds the ADIv6\n \u003e support back into the pre-existing ADIv5 implementation. The\n \u003e advantage of this approach is now OpenOCD supports Class 9 ROM\n \u003e table and 64-bit MEM-APs for both ADIv5 and v6 products. The\n \u003e disadvantage is due diligence must be performed to verify ADIv5\n \u003e support remains fully intact.\n\nDaniel,\nthanks for your effort.\nDo you think the class 9 ROM support could be extracted and become an independent patch, possibly to be applied \"before\" this ADIv6 support?\nThis could further reduce the size of this patch, simplifying the review.\n\nIn patch v7 you have split some long line that was not part of the patch itself. E.g.\nhttp://openocd.zylin.com/#/c/6077/6..7/src/target/arm_adi_v5.c@92\nFor OpenOCD coding style the max line length is 120 chars, so no need to add extra unrelated changes to an already big patch.","accounts_in_message":[],"_revision_number":8},{"id":"96f03a2c96832593111e7916afd3c0c38263e12f","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-07-31 17:32:58.000000000","message":"Patch Set 8:\n\n@Antonio: Yes, I\u0027ll extract the Class 9 support into a separate patch. That is a good idea. In terms of line length, I wasn\u0027t sure on the coding guidelines. For the next patch update I\u0027ll revert the line length updates and remove all unrelated changes. Thanks for the suggestions!","accounts_in_message":[],"_revision_number":8},{"id":"8de8115f765e96732a9acef3b533f8ddaa59aa61","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-02 13:38:17.000000000","message":"Patch Set 8:\n\n(3 comments)","accounts_in_message":[],"_revision_number":8},{"id":"c7cf64b3223deb334772a34c477902eb4ffde893","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-04 12:16:10.000000000","message":"Patch Set 8:\n\n(1 comment)","accounts_in_message":[],"_revision_number":8},{"id":"e75c2d68c9cd15ad9959d89158f5b960f9490092","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-08 21:49:12.000000000","message":"Patch Set 8:\n\nFYI\nI have started splitting this huge patch and got already 12 smaller patches, easier to review. Still missing the parsing of the ROM tables.\nOnce ROM tables are in, I plan to push the whole series on gerrit for review and, if possible, test on Ampere devices.\nUnfortunately I have access to the ADIv6 target only during the weekends, and the current one is already over; I wish I could complete it during next weekend.","accounts_in_message":[],"_revision_number":8},{"id":"2ba52a5d72876d4e7636a7741c330247478056d2","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-08-09 13:47:16.000000000","message":"Patch Set 8:\n\nAntonio, I\u0027ll be watching out for the gerrit patch series to review and can provide testing on Ampere devices.","accounts_in_message":[],"_revision_number":8},{"id":"2b879236f6fadfef8095dfaafe83782d2a215ec7","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2021-08-09 20:00:28.000000000","message":"Patch Set 8:\n\n(4 comments)\n\nAntonio, thanks for the review. Let me know if you want me to fix the issues in this patch, or wait until you\u0027ve released the next gerrit patch series (the one planned with 12 smaller patches).","accounts_in_message":[],"_revision_number":8},{"id":"bcac4b9e055849c843f42dcc5efd1f14b3d7546a","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-15 21:04:51.000000000","message":"Patch Set 8:\n\n(1 comment)","accounts_in_message":[],"_revision_number":8},{"id":"114538b79244e1565d980c69db26036cc045751e","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2021-08-22 23:12:18.000000000","message":"Patch Set 8:\n\n(1 comment)","accounts_in_message":[],"_revision_number":8},{"id":"392c12e6e0fd2794786225ba1795b5fe6423dedc","tag":"autogenerated:gerrit:abandon","author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"real_author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"date":"2025-06-04 14:58:40.000000000","message":"Abandoned\n\nOpenOCD supports ADIv6, this patch isn\u0027t needed.","accounts_in_message":[],"_revision_number":8}],"current_revision":"f42d1113dde9a17d3fc103ff5dfb64886f32b7a0","revisions":{"b2e0bfd3a50a1e80364c46b111e3cd3dc1e7ba3f":{"kind":"REWORK","_number":1,"created":"2021-03-03 21:00:49.000000000","uploader":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"ref":"refs/changes/77/6077/1","fetch":{"anonymous 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setting for ADIv6 targets, and\nminimal code changes by making use of existing adiv5\nfunctions where possible.\n\nTested on Ampere emulation and Quicksilver silicon.\n\nChange-Id: Ie948a8ab4fcd647a174400cc5d9fcd58909ca2fd\nSigned-off-by: Kevin Burke \u003ckevinb@os.amperecomputing.com\u003e\nSigned-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e\n"}},"39bf64ee5fd0fa3e4a8112a7fd0f553a6f2b71f2":{"kind":"REWORK","_number":5,"created":"2021-05-27 22:33:10.000000000","uploader":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"ref":"refs/changes/77/6077/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/77/6077/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/77/6077/5 \u0026\u0026 git checkout -b change-6077 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/77/6077/5 \u0026\u0026 git checkout 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-adiv6\nconfiguration overrides in case default IDR reads fail\nto identify the correct ADI version, additonal -apbase\naddress configuration setting for ADIv6 targets, and\nminimal code changes by making use of existing adiv5\nfunctions where possible.\n\nTested on Ampere emulation and Quicksilver silicon.\n\nChange-Id: Ie948a8ab4fcd647a174400cc5d9fcd58909ca2fd\nSigned-off-by: Kevin Burke \u003ckevinb@os.amperecomputing.com\u003e\nSigned-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e\n"}},"ea1f4f2c0f1499ca53c55878f2a34d48750bb37d":{"kind":"REWORK","_number":6,"created":"2021-06-02 22:13:35.000000000","uploader":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"ref":"refs/changes/77/6077/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/77/6077/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/77/6077/6 \u0026\u0026 git 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22:12:32.000000000","tz":-240},"subject":"target/arm: Add ADIv6 Support","message":"target/arm: Add ADIv6 Support\n\nIncludes Class 9 ROM Table, additonal -adiv5 and -adiv6\nconfiguration overrides in case default IDR reads fail\nto identify the correct ADI version, additonal -apbase\naddress configuration setting for ADIv6 targets, and\nminimal code changes by making use of existing adiv5\nfunctions where possible.\n\nTested on Ampere emulation and Quicksilver silicon.\n\nChange-Id: Ie948a8ab4fcd647a174400cc5d9fcd58909ca2fd\nSigned-off-by: Kevin Burke \u003ckevinb@os.amperecomputing.com\u003e\nSigned-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e\n"}},"a092d879a54ad1c6b32da9de3a01eb67a8eeb7dd":{"kind":"REWORK","_number":7,"created":"2021-07-24 03:16:20.000000000","uploader":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"ref":"refs/changes/77/6077/7","fetch":{"anonymous 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refs/changes/77/6077/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/77/6077/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"ae6de2f93d960c7d35e8d4c86d9c17dda17c561e","subject":"arm_adi_v5: Added Cortex-A76 identifiers"}],"author":{"name":"Kevin Burke","email":"kevinb@os.amperecomputing.com","date":"2021-02-09 22:32:51.000000000","tz":-300},"committer":{"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","date":"2021-07-26 14:54:06.000000000","tz":-240},"subject":"target/arm: Add ADIv6 Support","message":"target/arm: Add ADIv6 Support\n\nIncludes Class 9 ROM Table, additonal -adiv5 and -adiv6\nconfiguration overrides in case default IDR reads fail\nto identify the correct ADI version, additonal -apbase\naddress configuration setting for ADIv6 targets, and\nminimal code changes by making use of existing adiv5\nfunctions where possible.\n\nTested on Ampere Altra (ADIv6), Ampere Altra Max (ADIv6),\nAmpere eMAG8180 (ADIv5) and ARM Neoverse N1 (ADIv5).\n\nChange-Id: Ie948a8ab4fcd647a174400cc5d9fcd58909ca2fd\nSigned-off-by: Kevin Burke \u003ckevinb@os.amperecomputing.com\u003e\nSigned-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}