)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000697,"name":"Fredrik Hederstierna","email":"fredrik.hederstierna@gmail.com"},"change_message_id":"781e385d8087d86a82686f9192f280ee670ecfbb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6efa8381_ce8100db","updated":"2021-10-29 08:18:09.000000000","message":"Do you have any updated patch-set which also addresses the halt issue you described aswell? thanks, BR Fredrik","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f2c85c2a3e063f22f5da06e98bc1948b8cf6f915","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1c2f7d4a_9b3c0fb1","updated":"2026-01-25 15:40:40.000000000","message":"FYI series 2 support from silabs:\n9398: flash/efr32-series2: Add support for Silabs Series 2 | https://review.openocd.org/c/openocd/+/9398\nPlease review!","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1001959,"name":"Michael T","username":"knieriem"},"change_message_id":"f5d7a5c612714873b70869105cbe7e2c1051e3d5","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"3f12ae45_26bc54ed","updated":"2022-02-08 23:11:30.000000000","message":"Hi, I also worked with an EFM32 Series 2 MCU, and derived a preliminary driver \"efm32s2\" from efm32.c during last May/June.\nIt can be found at https://github.com/knieriem/openocd-efm32-series2 .\nFlashing works, also in fast mode, since I adjusted the flash write code.\nI decided not to extend efm32.c (which I tried first), but to rather use a separate file, efm32s2.c,\nbecause of quite a few differences. With separate files, it is easy to compare both implementations and see what is different. Page locking probably won\u0027t work yet.\n\nI remember having seen the halt problem, but I don\u0027t know for sure how I solved it. Maybe I solved it by executing just \"init\" and \"halt\", then \"flash\" commands. See \"dist\" directory for scripts I\u0027ve been using.\n\nRegards,\nMichael","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"6588b0e35fc414940cc8c2f8fa15f12016ae9094","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"3bbcb03e_79ac3f83","updated":"2022-03-12 17:46:09.000000000","message":"I\u0027ve tried out Michael/Henrik\u0027s version, and still have the same issues with unable to halt and unable to use \"load\" via gdb.  I\u0027ll be trying out Steve\u0027s version as well, and see what I can pull together into a single version.","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1000697,"name":"Fredrik Hederstierna","email":"fredrik.hederstierna@gmail.com"},"change_message_id":"8c02052f5cd22c11205911c2293ae0d4cc9f9752","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2afac658_4325262b","updated":"2021-11-03 06:42:07.000000000","message":"Ok thanks Karl, did you get Steven Stallions fix for the halt issue, or @Steven/Karl: can you attach them here? Thanks!","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1001127,"name":"Steven Stallion","email":"sstallion@gmail.com","username":"sstallion"},"change_message_id":"78f610dec559bb3e5f512d974e45853325a250e5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"460a736e_7537605f","in_reply_to":"2afac658_4325262b","updated":"2021-11-03 18:12:55.000000000","message":"Gerrit makes it a bit tough to share patches, so I\u0027ll inline it here. These changes add new chip and target scripts, which we use in a repository outside of OpenOCD - they\u0027ll probably need to be massaged a bit.\n\nHTH,\nSteve\n\ndiff --git a/chip/efr32xg22.tcl b/chip/efr32xg22.tcl\nnew file mode 100644\nindex 00000000000..05aafba891b\n--- /dev/null\n+++ b/chip/efr32xg22.tcl\n@@ -0,0 +1,32 @@\n+# Copyright 2021 Square, Inc.\n+\n+# EFR32xG22 Series 2 SoCs provide a secure bootloader, which causes issues\n+# communicating with the DAP on reset. The following workaround uses ARP\n+# commands to poll the SoC prior to halting the core.\n+#\n+# To enable this workaround, add the following to the target configuration:\n+#\n+# proc init_reset { mode } { efr32xg22_reset_mode $mode }\n+#\n+# $_TARGETNAME configure -event reset-deassert-post \"efr32xg22_deassert_post $_TARGETNAME\"\n+\n+proc efr32xg22_reset_mode { mode } {\n+\tset ::efr32xg22_reset_mode $mode\n+}\n+\n+proc efr32xg22_deassert_post { target } {\n+\t$target arp_examine\n+\n+\tif { $::efr32xg22_reset_mode ne \"run\" } {\n+\t\t$target arp_poll\n+\t\t$target arp_poll\n+\n+\t\tif { [$target curstate] eq \"reset\" } {\n+\t\t\tcatch {$target arp_waitstate running 100 }\n+\t\t}\n+\n+\t\tif { [$target curstate] eq \"running\" } {\n+\t\t\t$target arp_halt\n+\t\t}\n+\t}\n+}\ndiff --git a/target/efr32xg22.cfg b/target/efr32xg22.cfg\nnew file mode 100644\nindex 00000000000..e25adcf1508\n--- /dev/null\n+++ b/target/efr32xg22.cfg\n@@ -0,0 +1,23 @@\n+# Copyright 2021 Square, Inc.\n+\n+set CHIPNAME efr32xg22\n+source [find target/efm32.cfg]\n+\n+adapter_khz 1900\n+\n+$_TARGETNAME configure -event gdb-attach {\n+    cortex_m maskisr auto   ;# mask interrupts while stepping\n+}\n+\n+reset_config srst_nogate\n+\n+# EFR32xG22 Series 2 SoCs provide a secure bootloader, which causes issues\n+# communicating with the DAP on reset. The following workaround uses ARP\n+# commands to poll the SoC prior to halting the core.\n+source [find chip/efr32xg22.tcl]\n+\n+proc init_reset { mode } {\n+\tefr32xg22_reset_mode $mode\n+}\n+\n+$_TARGETNAME configure -event reset-deassert-post \"efr32xg22_deassert_post $_TARGETNAME\"","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1002145,"name":"Ben Campbell","username":"benjacam"},"change_message_id":"cbc36054761ae2eef07d1c94f0e48745a7204b5e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"56174071_20e71f07","in_reply_to":"3bbcb03e_79ac3f83","updated":"2023-05-22 11:33:02.000000000","message":"I have been trying Hendrik\u0027s changes. One problem I found is that the code is using secure peripheral addresses (e.g. EFM32_MSC_REGBASE\u003d0x40030000, EFM32_CMU_REGBASE\u003d0x40008000). See section 4.2.4.1 Peripheral Map in the EFM32PG22 reference manual. For me, that appeared to cause the device to lock up when attempting to write to MSC_WRITECTRL.WREN. I changed the addresses above to the _NS (non-secure) variants which have the same offsets but start at 0x50000000 and that appeared to fix the issue for me. Perhaps that is the cause of the halt issue referenced in these comments?","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1000697,"name":"Fredrik Hederstierna","email":"fredrik.hederstierna@gmail.com"},"change_message_id":"d0a41e4c0c6179499ee48cd068b292bce17e1160","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"cd312244_2440f1db","in_reply_to":"3bbcb03e_79ac3f83","updated":"2023-06-08 13:14:34.000000000","message":"I tried with this non secured REGBASE and it works fine for me.\nAdded a pull-request upstream from my fork at\nhttps://github.com/fredrikhederstierna/openocd-efm32-series2\nPlease check it out, and if it could be merged.\n\nMichael, is it possible for you to make an \u0027official\u0027 patch upstream for review on all your great efr32s2-work from \"https://github.com/knieriem/openocd-efm32-series2\"?\n\nHaving a core efr32s2-driver merged upstream, would make it easier to find and fix any further tweaking needed for possible chip variants, new features or funcs required, halting issues etc.","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1001962,"name":"Henrik Persson","email":"henrik.persson@mikrodust.com","username":"mikrodust-henrikp"},"change_message_id":"9bc41a793ec45d58e5070f6b28fa397857496a4c","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"f958735a_fa953d7a","in_reply_to":"3f12ae45_26bc54ed","updated":"2022-03-10 08:20:30.000000000","message":"Hi!\n\nI\u0027ve extended/forked this somewhat to support EFR32FG23 (and maybe others, register map and their bits are a bit different and base address for flash also changes, apparently) and also added support for setting debug lock/unlock via the \"DCI\" interface: https://github.com/mikrodust-henrikp/openocd-efm32-series2\n\nHopefully this might be of some use to someone picking this target up next time.","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"bc8cce7181cc7111bf73ce9945d5e30e5e21562e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"a2224851_dad059b9","in_reply_to":"6efa8381_ce8100db","updated":"2021-10-31 13:30:16.000000000","message":"No, I developed this while evaluating these parts, but we ended up using a different part, so I\u0027ve not done any further work on this.  (And have none scheduled)","commit_id":"60dc0ddee971e5b26b77b6cc195cba259c8cb6e4"}]}