)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2cd77784b3d3b95cb3bda1a33e736bcb7dec299d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"cb84d0d7_5a612dbf","updated":"2021-11-08 11:21:49.000000000","message":"Antonio, I refused universal hla/cortex_m r/w used solely for dhcsr access.\nWhat is your opinion on extending this idea to all r/w ops and introducing cortex_m_hla_read_u32/cortex_m_hla_write_u32 (and eventually atomic versions)?\nPros:\n+ We could use these ops uniformly instead of distinguishing between target_read/write_xx for code common to hla and cortex_m, mem_ap_r/w for cortex_m only code.\n+ We get somewhat faster access on cortex_m in the parts common with hla. These are mainly initialization related, so none of them is really time critical.\n\nCons:\n- Introducing just another set of target mem access routines makes the OpenOCD even more complicated and harder to understand\n- Each access on Cortex-M would have to extract struct armv7m_common pointer from target pointer. IMO this host code penalty is negligible.\n\nWhat do you think?","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c51c6d23cfa8f1fe439e7078869c1df9acf26a0b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"4120164e_6c0c87e3","in_reply_to":"cb84d0d7_5a612dbf","updated":"2021-11-08 22:35:05.000000000","message":"yes, that\u0027s a good idea.\nI was thinking about having in mem_ap_write_u32() and similar the check for hla. But this hla crap is cortex-M specific; let\u0027s keep it in cortex_m.c\nWe would also need a cortex_m_hla_dap_run()","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"}],"src/target/cortex_m.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9695fa23b39c790e7f962594fb306cdf718fc754","unresolved":false,"context_lines":[{"line_number":139,"context_line":"\t\treturn retval;"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"\t/* preserve the two sticky bits */"},{"line_number":142,"context_line":"\tcortex_m-\u003edcb_dhcsr \u003d (cortex_m-\u003edcb_dhcsr \u0026 (S_RESET_ST | S_RETIRE_ST)) | dhcsr;"},{"line_number":143,"context_line":"\treturn ERROR_OK;"},{"line_number":144,"context_line":"}"},{"line_number":145,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"aedf27f1_e3997ac9","line":142,"updated":"2021-05-05 16:35:52.000000000","message":"actually the 16 MSB of DCB_DHCSR contain 6 sticky bits.\nIt would be more general masking 0xffff0000 instead of (S_RESET_ST | S_RETIRE_ST)","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9695fa23b39c790e7f962594fb306cdf718fc754","unresolved":false,"context_lines":[{"line_number":146,"context_line":"static void cortex_m_clear_sticky_dcb_dhcsr(struct cortex_m_common *cortex_m, uint32_t mask)"},{"line_number":147,"context_line":"{"},{"line_number":148,"context_line":"\t/* mask only the two sticky bits */"},{"line_number":149,"context_line":"\tcortex_m-\u003edcb_dhcsr \u0026\u003d ~(mask \u0026 (S_RESET_ST | S_RETIRE_ST));"},{"line_number":150,"context_line":"}"},{"line_number":151,"context_line":""},{"line_number":152,"context_line":"static int cortex_m_write_atomic_dcb_dhcsr_mask(struct target *target,"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"aedf27f1_0397de94","line":149,"updated":"2021-05-05 16:35:52.000000000","message":"here too!","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"5d86f3842fdb7f5628ddc18d2254c9c03c6e1e8c","unresolved":false,"context_lines":[{"line_number":149,"context_line":"\tcortex_m-\u003edcb_dhcsr \u0026\u003d ~(mask \u0026 (S_RESET_ST | S_RETIRE_ST));"},{"line_number":150,"context_line":"}"},{"line_number":151,"context_line":""},{"line_number":152,"context_line":"static int cortex_m_write_atomic_dcb_dhcsr_mask(struct target *target,"},{"line_number":153,"context_line":"\tuint32_t mask_on, uint32_t mask_off)"},{"line_number":154,"context_line":"{"},{"line_number":155,"context_line":"\tstruct cortex_m_common *cortex_m \u003d target_to_cm(target);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"aedf27f1_a39372a5","line":152,"range":{"start_line":152,"start_character":26,"end_line":152,"end_character":32},"updated":"2021-05-05 16:39:27.000000000","message":"Why would the write need to be atomic?","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2cd77784b3d3b95cb3bda1a33e736bcb7dec299d","unresolved":false,"context_lines":[{"line_number":149,"context_line":"\tcortex_m-\u003edcb_dhcsr \u0026\u003d ~(mask \u0026 (S_RESET_ST | S_RETIRE_ST));"},{"line_number":150,"context_line":"}"},{"line_number":151,"context_line":""},{"line_number":152,"context_line":"static int cortex_m_write_atomic_dcb_dhcsr_mask(struct target *target,"},{"line_number":153,"context_line":"\tuint32_t mask_on, uint32_t mask_off)"},{"line_number":154,"context_line":"{"},{"line_number":155,"context_line":"\tstruct cortex_m_common *cortex_m \u003d target_to_cm(target);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"aedf27f1_c3beb6fa","line":152,"range":{"start_line":152,"start_character":26,"end_line":152,"end_character":32},"in_reply_to":"aedf27f1_83f2ee01","updated":"2021-11-08 11:21:49.000000000","message":"At least cortex_m_resume() and cortex_m_halt() require atomic write or manual queue run. On the other hand a non-atomic write would save a lot in cortex_m_step()!\n\n(This text has been long time lost in gerrit as a draft)","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"029033a1fa8cc1413a9e1a9fc83df00d4f5ba0c4","unresolved":false,"context_lines":[{"line_number":149,"context_line":"\tcortex_m-\u003edcb_dhcsr \u0026\u003d ~(mask \u0026 (S_RESET_ST | S_RETIRE_ST));"},{"line_number":150,"context_line":"}"},{"line_number":151,"context_line":""},{"line_number":152,"context_line":"static int cortex_m_write_atomic_dcb_dhcsr_mask(struct target *target,"},{"line_number":153,"context_line":"\tuint32_t mask_on, uint32_t mask_off)"},{"line_number":154,"context_line":"{"},{"line_number":155,"context_line":"\tstruct cortex_m_common *cortex_m \u003d target_to_cm(target);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"aedf27f1_83f2ee01","line":152,"range":{"start_line":152,"start_character":26,"end_line":152,"end_character":32},"in_reply_to":"aedf27f1_a39372a5","updated":"2021-05-05 16:51:55.000000000","message":"Good question!\nIt was already atomic in cortex_m_write_debug_halt_mask() and the other write replaced by calling this function were all atomic too.\nLet\u0027s check if this can relaxed!.","commit_id":"effcf23bd3662950407682d11d36b950a67bba7a"}]}