)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"37beddf55dfa7c51669bc32e936f025c7ec198e1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"a62019f2_d9981ce3","updated":"2021-09-16 13:06:29.000000000","message":"Daniel, the patch order is the one reported in \"Relation chain\" on top-right of the patch page.\nThis 6359 is after 6463 and before 6464.\nby click on the 3 vertical dots in top-right of the page and clink on \"Download patch\" you can checkout the patch with all the dependencies. Doing this on the last patch of the series, you get the whole series.\n\nI have just updated/rebased the first 9 patches of the series only! To avoid too much noise on the mailing list. These are quite independent from adiv6 and I plan to merge them quickly.\n","commit_id":"e9a7c1ffd143d0bcdaeb5cef660e62b1c6dc262b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"f266169f4f1b9172783a5a5e9b6fa25a38cea424","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"381a9004_8ef124e1","updated":"2021-09-16 00:39:58.000000000","message":"I tested the first draft of patches 6446-6454, 6463 and 6359 on an ARM Neoverse N1 system. The \"dap info\" command provided the expected result. The Neoverse N1 is an ideal test system for these patches since it uses an ADIv5 DAP and has CS1 and CS9 ROM tables.\n\nI did need to reorder patch 6359 and 6463 in order to apply cleanly as mentioned below.\n\nI noticed patch updates were submitted a few minutes ago and I haven\u0027t had a chance to test them yet.\n\nBesides the \"dap info\" command, if there are any other commands I should test with patches 6446-6454, 6463 and 6359, please let me know. Everything looks good to me.","commit_id":"e9a7c1ffd143d0bcdaeb5cef660e62b1c6dc262b"}],"src/target/arm_adi_v5.c":[{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"f266169f4f1b9172783a5a5e9b6fa25a38cea424","unresolved":true,"context_lines":[{"line_number":892,"context_line":"\t[0xF] \u003d \"CoreLink, PrimeCell or System component\","},{"line_number":893,"context_line":"};"},{"line_number":894,"context_line":""},{"line_number":895,"context_line":"#define ARCH_ID(architect, archid) ( \\"},{"line_number":896,"context_line":"\t(((architect) \u003c\u003c ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) \u0026 ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \\"},{"line_number":897,"context_line":"\t(((archid) \u003c\u003c ARM_CS_C9_DEVARCH_ARCHID_SHIFT) \u0026 ARM_CS_C9_DEVARCH_ARCHID_MASK) \\"},{"line_number":898,"context_line":")"},{"line_number":899,"context_line":""},{"line_number":900,"context_line":"static const struct {"},{"line_number":901,"context_line":"\tuint32_t arch_id;"},{"line_number":902,"context_line":"\tconst char *description;"},{"line_number":903,"context_line":"} class0x9_devarch[] \u003d {"},{"line_number":904,"context_line":"\t/* keep same unsorted order as in ARM IHI0029E */"},{"line_number":905,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A00), \"RAS architecture\" },"},{"line_number":906,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A01), \"Instrumentation Trace Macrocell (ITM) architecture\" },"},{"line_number":907,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A02), \"DWT architecture\" },"},{"line_number":908,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A03), \"Flash Patch and Breakpoint unit (FPB) architecture\" },"},{"line_number":909,"context_line":"\t{ ARCH_ID(ARM_ID, 0x2A04), \"Processor debug architecture (ARMv8-M)\" },"},{"line_number":910,"context_line":"\t{ ARCH_ID(ARM_ID, 0x6A05), \"Processor debug architecture (ARMv8-R)\" },"},{"line_number":911,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A10), \"PC sample-based profiling\" },"},{"line_number":912,"context_line":"\t{ ARCH_ID(ARM_ID, 0x4A13), \"Embedded Trace Macrocell (ETM) architecture\" },"},{"line_number":913,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A14), \"Cross Trigger Interface (CTI) architecture\" },"},{"line_number":914,"context_line":"\t{ ARCH_ID(ARM_ID, 0x6A15), \"Processor debug architecture (v8.0-A)\" },"},{"line_number":915,"context_line":"\t{ ARCH_ID(ARM_ID, 0x7A15), \"Processor debug architecture (v8.1-A)\" },"},{"line_number":916,"context_line":"\t{ ARCH_ID(ARM_ID, 0x8A15), \"Processor debug architecture (v8.2-A)\" },"},{"line_number":917,"context_line":"\t{ ARCH_ID(ARM_ID, 0x2A16), \"Processor Performance Monitor (PMU) architecture\" },"},{"line_number":918,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A17), \"Memory Access Port v2 architecture\" },"},{"line_number":919,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A27), \"JTAG Access Port v2 architecture\" },"},{"line_number":920,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A31), \"Basic trace router\" },"},{"line_number":921,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A37), \"Power requestor\" },"},{"line_number":922,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A47), \"Unknown Access Port v2 architecture\" },"},{"line_number":923,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A50), \"HSSTP architecture\" },"},{"line_number":924,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A63), \"System Trace Macrocell (STM) architecture\" },"},{"line_number":925,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A75), \"CoreSight ELA architecture\" },"},{"line_number":926,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0AF7), \"CoreSight ROM architecture\" },"},{"line_number":927,"context_line":"};"},{"line_number":928,"context_line":""},{"line_number":929,"context_line":"#define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)"},{"line_number":930,"context_line":"#define DEVARCH_ROM_C_0X9       ARCH_ID(ARM_ID, 0x0AF7)"},{"line_number":931,"context_line":""},{"line_number":932,"context_line":"static const char *class0x9_devarch_description(uint32_t devarch)"},{"line_number":933,"context_line":"{"},{"line_number":934,"context_line":"\tif (!(devarch \u0026 ARM_CS_C9_DEVARCH_PRESENT))"},{"line_number":935,"context_line":"\t\treturn \"not present\";"},{"line_number":936,"context_line":""},{"line_number":937,"context_line":"\tfor (unsigned int i \u003d 0; i \u003c ARRAY_SIZE(class0x9_devarch); i++)"},{"line_number":938,"context_line":"\t\tif ((devarch \u0026 DEVARCH_ID_MASK) \u003d\u003d class0x9_devarch[i].arch_id)"},{"line_number":939,"context_line":"\t\t\treturn class0x9_devarch[i].description;"},{"line_number":940,"context_line":""},{"line_number":941,"context_line":"\treturn \"unknown\";"},{"line_number":942,"context_line":"}"},{"line_number":943,"context_line":""},{"line_number":944,"context_line":"static const struct {"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"fbb43796_a1644d2f","line":941,"range":{"start_line":895,"start_character":0,"end_line":941,"end_character":18},"updated":"2021-09-16 00:39:58.000000000","message":"This section is added in patch 6463 which occurs later in the patchset. For my testing, I placed patch 6463 right before this patch (6359).","commit_id":"e9a7c1ffd143d0bcdaeb5cef660e62b1c6dc262b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"55771117b201e6f4308f7b9c0e91e3acac0aba3d","unresolved":false,"context_lines":[{"line_number":892,"context_line":"\t[0xF] \u003d \"CoreLink, PrimeCell or System component\","},{"line_number":893,"context_line":"};"},{"line_number":894,"context_line":""},{"line_number":895,"context_line":"#define ARCH_ID(architect, archid) ( \\"},{"line_number":896,"context_line":"\t(((architect) \u003c\u003c ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) \u0026 ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \\"},{"line_number":897,"context_line":"\t(((archid) \u003c\u003c ARM_CS_C9_DEVARCH_ARCHID_SHIFT) \u0026 ARM_CS_C9_DEVARCH_ARCHID_MASK) \\"},{"line_number":898,"context_line":")"},{"line_number":899,"context_line":""},{"line_number":900,"context_line":"static const struct {"},{"line_number":901,"context_line":"\tuint32_t arch_id;"},{"line_number":902,"context_line":"\tconst char *description;"},{"line_number":903,"context_line":"} class0x9_devarch[] \u003d {"},{"line_number":904,"context_line":"\t/* keep same unsorted order as in ARM IHI0029E */"},{"line_number":905,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A00), \"RAS architecture\" },"},{"line_number":906,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A01), \"Instrumentation Trace Macrocell (ITM) architecture\" },"},{"line_number":907,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A02), \"DWT architecture\" },"},{"line_number":908,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A03), \"Flash Patch and Breakpoint unit (FPB) architecture\" },"},{"line_number":909,"context_line":"\t{ ARCH_ID(ARM_ID, 0x2A04), \"Processor debug architecture (ARMv8-M)\" },"},{"line_number":910,"context_line":"\t{ ARCH_ID(ARM_ID, 0x6A05), \"Processor debug architecture (ARMv8-R)\" },"},{"line_number":911,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A10), \"PC sample-based profiling\" },"},{"line_number":912,"context_line":"\t{ ARCH_ID(ARM_ID, 0x4A13), \"Embedded Trace Macrocell (ETM) architecture\" },"},{"line_number":913,"context_line":"\t{ ARCH_ID(ARM_ID, 0x1A14), \"Cross Trigger Interface (CTI) architecture\" },"},{"line_number":914,"context_line":"\t{ ARCH_ID(ARM_ID, 0x6A15), \"Processor debug architecture (v8.0-A)\" },"},{"line_number":915,"context_line":"\t{ ARCH_ID(ARM_ID, 0x7A15), \"Processor debug architecture (v8.1-A)\" },"},{"line_number":916,"context_line":"\t{ ARCH_ID(ARM_ID, 0x8A15), \"Processor debug architecture (v8.2-A)\" },"},{"line_number":917,"context_line":"\t{ ARCH_ID(ARM_ID, 0x2A16), \"Processor Performance Monitor (PMU) architecture\" },"},{"line_number":918,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A17), \"Memory Access Port v2 architecture\" },"},{"line_number":919,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A27), \"JTAG Access Port v2 architecture\" },"},{"line_number":920,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A31), \"Basic trace router\" },"},{"line_number":921,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A37), \"Power requestor\" },"},{"line_number":922,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A47), \"Unknown Access Port v2 architecture\" },"},{"line_number":923,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A50), \"HSSTP architecture\" },"},{"line_number":924,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A63), \"System Trace Macrocell (STM) architecture\" },"},{"line_number":925,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0A75), \"CoreSight ELA architecture\" },"},{"line_number":926,"context_line":"\t{ ARCH_ID(ARM_ID, 0x0AF7), \"CoreSight ROM architecture\" },"},{"line_number":927,"context_line":"};"},{"line_number":928,"context_line":""},{"line_number":929,"context_line":"#define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)"},{"line_number":930,"context_line":"#define DEVARCH_ROM_C_0X9       ARCH_ID(ARM_ID, 0x0AF7)"},{"line_number":931,"context_line":""},{"line_number":932,"context_line":"static const char *class0x9_devarch_description(uint32_t devarch)"},{"line_number":933,"context_line":"{"},{"line_number":934,"context_line":"\tif (!(devarch \u0026 ARM_CS_C9_DEVARCH_PRESENT))"},{"line_number":935,"context_line":"\t\treturn \"not present\";"},{"line_number":936,"context_line":""},{"line_number":937,"context_line":"\tfor (unsigned int i \u003d 0; i \u003c ARRAY_SIZE(class0x9_devarch); i++)"},{"line_number":938,"context_line":"\t\tif ((devarch \u0026 DEVARCH_ID_MASK) \u003d\u003d class0x9_devarch[i].arch_id)"},{"line_number":939,"context_line":"\t\t\treturn class0x9_devarch[i].description;"},{"line_number":940,"context_line":""},{"line_number":941,"context_line":"\treturn \"unknown\";"},{"line_number":942,"context_line":"}"},{"line_number":943,"context_line":""},{"line_number":944,"context_line":"static const struct {"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"84acee57_5628f758","line":941,"range":{"start_line":895,"start_character":0,"end_line":941,"end_character":18},"in_reply_to":"fbb43796_a1644d2f","updated":"2021-09-16 14:56:31.000000000","message":"Ack","commit_id":"e9a7c1ffd143d0bcdaeb5cef660e62b1c6dc262b"}]}