)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"b8fd4c04b924cb952d16c527809d1a0e7cc8fafa","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"837c5ddf_76847f76","updated":"2021-10-19 21:30:05.000000000","message":"Comments on extending the memaccess_tck delay...","commit_id":"22ff2c8c7e85dbec83390a272e845744022ac3f3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"e5c6164fdf14472524793e3b008ef644c348d988","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6aa43388_26b44c44","updated":"2021-08-22 23:17:12.000000000","message":"For me this is incorrect.\nCan you please explain why this was in https://review.openocd.org/6077/ ?","commit_id":"22ff2c8c7e85dbec83390a272e845744022ac3f3"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"439a3bd66ce6f3da1e10c9f55256c6d6537f2aaf","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"46beebaf_0c63bde3","updated":"2021-10-07 14:29:35.000000000","message":"From my read of the ADIv5.0 to ADIv5.2 Architecture Specification (IHI0031F) \"Minimum response times\" section, it does not state that only a bus access behind a MEM-AP operation would need the additional TCK delay. My interpretation is that register accesses can also be delayed. In reality it is very likely that the only real delay seen would be on bus access via a MEM-AP, but I don\u0027t see that explicitly stated in the spec. For that reason, the ADIv6 code path includes the TCK delay \u0027unconditionally\u0027 while the ADIv5 code was left untouched since that is legacy code we did not want to change.\n\nFrom the \"Minimum response times\" section in the ADIv5 spec (similar to ADIv6):\n\n\"A DP or AP register access is initiated at the Update-DR state of one DPACC or APACC access, and the result of the access is returned at the Capture-DR state of the following DPACC or APACC access.\"\n\nand\n\n\"In addition, when accessing AP registers, or accessing a connected device through an AP, there might be other variable response delays in the system. A debugger that can adapt to these delays, avoiding wasted WAIT scans, operates more efficiently and provides higher maximum data throughput.\"","commit_id":"22ff2c8c7e85dbec83390a272e845744022ac3f3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"988e355031a36f1ec866d280a4d2aa26258210a6","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"93ad418e_881ebd5e","in_reply_to":"46beebaf_0c63bde3","updated":"2021-10-12 11:53:59.000000000","message":"The last sentence you posted is from ADIv5 IHI0031A, but is still present, revised, in latest IHI0031F as a note in \"Minimum response times\" section:\n\"Accessing AP registers or debug resources in connected device through an AP can be subjected to other variable response delays in the system. A debugger that can adapt to these delays and avoid wasting WAIT scans operates more efficiently and provides higher maximum data throughput.\"\n\nShould this be unconditional for ADIv5 too?","commit_id":"22ff2c8c7e85dbec83390a272e845744022ac3f3"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"b8fd4c04b924cb952d16c527809d1a0e7cc8fafa","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"7662baa6_a45db655","in_reply_to":"93ad418e_881ebd5e","updated":"2021-10-19 21:30:05.000000000","message":"Despite what the spec indicates, we believe and verified on our parts that MEM-AP accesses are the only ones that need the added delay introduced in this code. Perhaps we can have the ADIv6 code match the same checks done in the ADIv5 code.\n\nIf at a later date we find the other (AP/DP register) accesses need a similar delay, another \u0027delay\u0027 configuration control can be included to add delay to those accesses.\n\nWhen testing a setup that extends delay for all accesses (AP/DP regs and MEM-AP), test results incur a 5% time penalty compared to only including the delay for MEM-AP accesses. While either approach is fine, I\u0027m leaning towards using the legacy ADIv5 delay approach for ADIv6.","commit_id":"22ff2c8c7e85dbec83390a272e845744022ac3f3"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"97bcdbe53ce98e422d32fe513e81f19280433780","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"cff0572f_81072cf3","updated":"2021-11-10 10:07:11.000000000","message":"I have modified this to follow ADIv5 documentation. Every AP access is now using memaccess_tck","commit_id":"c91f14084b6a4177f7bdfe76867823c5e9fb5a18"}]}