)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1d7afe2d10d27c64ebe5933e98dfbd53b161e8a3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"0f8a63f0_8a28f952","updated":"2021-09-02 17:52:48.000000000","message":"Flash driver and doc changes looks good.","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000843,"name":"Michael Schwingen","email":"michael@schwingen.org","username":"mschwingen2"},"change_message_id":"28906fdb68934b952abaac5091220403753a3268","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"14b2d047_8db96e54","updated":"2021-09-05 20:36:38.000000000","message":"Mixing STM32 and GD32 part IDs looks messy - and it will get worse as soon as ST also introduces M23 parts.\nI just pushed a different approach at 88c3b55d30f2cbf4dbb05b6ba8a2187c3e1a6d55 (\"add GigaDevice GD32Exxx flash driver\"), by introducing a GD32 flash driver that has separate probe/info functions, but re-uses most of the existing STM32 code.\n","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6845a865_4ae9765b","in_reply_to":"14b2d047_8db96e54","updated":"2021-09-06 17:59:00.000000000","message":"Good idea!\nNeeds to be tested with other GD32 ARM microcontrollers (I can check it on GD32F130 \u0026 GD32F103). Remember about option bits that is different from STM32 and after lock and unlock are changed to unwanted state.\nThey will be more problems with GD32 microcontrollers that works now.\nI think there will not be problems with future M23 microcontroller from ST because used registers are for M23.\nMy patch is simple because was urgent (nowadays problems with microcontrollers ordering).","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"b7536faf_2bdd7dfa","updated":"2021-09-06 17:59:00.000000000","message":"Patchset 2 was uploaded.\nI added to config debug clock enable - in this microcontroller it is required to succesfully disable watchdog during halt.\nI also added name gd32e23x to use instead of stm32f1x in telnet command line.","commit_id":"48f2ac829973a351fcfe4efad10b3e6ffbffc3eb"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"9c583cbc_ea7b9ee9","updated":"2021-11-08 06:51:13.000000000","message":"Andrzej, if you accept my wish to finish this change in favour of being fast enough to catch 0.12 release, please resolve the last 3 unresolved points and I\u0027ll put +2 score.","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"29d806012a3eb8f667b4eb9f166997a5f7ffaa72","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"4ae8e913_35fcc020","updated":"2021-09-14 12:40:29.000000000","message":"I\u0027ve only changed description of adapter speed that doesn\u0027t use JTAG word now.\nI tested using high speed MCU-Link interface that speed value 8MHz works fine. More than 10MHz is reduced by microcontroller to 10MHz as I observe on oscilloscope. Speed 1MHz should work on different interfaces and in different enviroments. Higher value can be set in own board configuration file.\nI am stopping work on this patch because there is better another patch that separates STM32 microcontrollers from the GD32 ones and can be easy upgraded in the future:\nhttps://review.openocd.org/c/openocd/+/6543\nhttps://review.openocd.org/c/openocd/+/6552\n","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"8cc78583_deacc6fb","in_reply_to":"4ae8e913_35fcc020","updated":"2021-11-08 06:51:13.000000000","message":"\u003e I\u0027ve only changed description of adapter speed that doesn\u0027t use JTAG word now.\n\nNo objections.","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"dd8849c1ecb529c8798a9b039f7439932ade35f4","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"a256b1df_f3c31409","updated":"2021-11-08 12:42:06.000000000","message":"Thanks for fast response","commit_id":"c6173cab44c093ed6bbf45585de21c88e98bceb1"}],"tcl/target/gd32e23x.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1d7afe2d10d27c64ebe5933e98dfbd53b161e8a3","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# script for gd32e23x family"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# gd32e23x devices support SWD transports only."}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"316e4371_761d7f0f","line":1,"range":{"start_line":1,"start_character":2,"end_line":1,"end_character":28},"updated":"2021-09-02 17:52:48.000000000","message":"Use SPDX indentifier. See https://review.openocd.org/c/openocd/+/5950/17/tcl/target/npcx.cfg\n\nInclude manufacturer name and used CPU","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# script for gd32e23x family"},{"line_number":2,"context_line":""},{"line_number":3,"context_line":"#"},{"line_number":4,"context_line":"# gd32e23x devices support SWD transports only."}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"53a78532_f92d66ef","line":1,"range":{"start_line":1,"start_character":2,"end_line":1,"end_character":28},"in_reply_to":"316e4371_761d7f0f","updated":"2021-09-06 17:59:00.000000000","message":"Done","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1d7afe2d10d27c64ebe5933e98dfbd53b161e8a3","unresolved":true,"context_lines":[{"line_number":9,"context_line":"if { [info exists CHIPNAME] } {"},{"line_number":10,"context_line":"   set _CHIPNAME $CHIPNAME"},{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32f1x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"03f25786_e7c5d380","line":12,"range":{"start_line":12,"start_character":17,"end_line":12,"end_character":25},"updated":"2021-09-02 17:52:48.000000000","message":"Why not gd32e23x?","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[{"line_number":9,"context_line":"if { [info exists CHIPNAME] } {"},{"line_number":10,"context_line":"   set _CHIPNAME $CHIPNAME"},{"line_number":11,"context_line":"} else {"},{"line_number":12,"context_line":"   set _CHIPNAME stm32f1x"},{"line_number":13,"context_line":"}"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"set _ENDIAN little"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"9878a7fe_39db1741","line":12,"range":{"start_line":12,"start_character":17,"end_line":12,"end_character":25},"in_reply_to":"03f25786_e7c5d380","updated":"2021-09-06 17:59:00.000000000","message":"Done","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1d7afe2d10d27c64ebe5933e98dfbd53b161e8a3","unresolved":true,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"159a65e4_fdb5ef7f","line":54,"range":{"start_line":53,"start_character":0,"end_line":54,"end_character":18},"updated":"2021-09-02 17:52:48.000000000","message":"This limit is not imposed by SWD\nConsider removing speed setting","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"217e8009_56dffcf2","line":54,"range":{"start_line":53,"start_character":0,"end_line":54,"end_character":18},"in_reply_to":"159a65e4_fdb5ef7f","updated":"2021-09-06 17:59:00.000000000","message":"Removing this paremeter causes error when running openocd. Changing speed parameter, clock on SWD interface also changes (checked using oscilloscope on stlink). I think 1000kHz should work fine even on long interface wires.","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7b0cf2c424eb71fce053d922d7ff130dee123f69","unresolved":true,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"e966ae31_cdd97d52","line":54,"range":{"start_line":53,"start_character":0,"end_line":54,"end_character":18},"in_reply_to":"217e8009_56dffcf2","updated":"2021-09-06 19:22:03.000000000","message":"There is 100 target cfg files with setting adapter speed and 173 without.\nWhy? If the clock frequency is a chip specific limit, then it goes to target config. Otherwise it should be in board config.\nAlso I\u0027m really tired reading \u0027JTAG speed should be \u003c\u003d F_CPU/6\u0027 again and again like a mantra. A modern SWD works happily at 10*F_CPU...\nSee https://openocd.org/doc/html/Config-File-Guidelines.html#JTAG-Clock-Rate","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":false,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ec00c749_0b820471","line":54,"range":{"start_line":53,"start_character":0,"end_line":54,"end_character":18},"in_reply_to":"68be1c4b_a18f65c3","updated":"2021-11-08 06:51:13.000000000","message":"Dunno why comments are discontinued, marking as resolved","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"400561e0bf132803c557ed2e52306ba25d4a99bd","unresolved":true,"context_lines":[{"line_number":50,"context_line":"set _FLASHNAME $_CHIPNAME.flash"},{"line_number":51,"context_line":"flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"68be1c4b_a18f65c3","line":54,"range":{"start_line":53,"start_character":0,"end_line":54,"end_character":18},"in_reply_to":"e966ae31_cdd97d52","updated":"2021-09-07 11:01:25.000000000","message":"I also counted it. There is 104 target config files with adapter speed, 103 without it and 69 config files that has internal other source included 😊\nNot everyone use board config file (professional projects are no based on devkits), so to simplify configuration this parameter should be initially set to optimal value to avoid error message. There is no problem to update this value to higher value at board config file if it is needed.\nLook at STM32F0x config file (its only SWD and has only JTAG word removed):\n# adapter speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz\nadapter speed 1000\nAlso this configuration has higher speed after configured PLL to faster flash programming.","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1d7afe2d10d27c64ebe5933e98dfbd53b161e8a3","unresolved":true,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"723f418c_8eeb6386","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"updated":"2021-09-02 17:52:48.000000000","message":"Is it really needed?","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"2e135feb52c9c5a3b853ed416f3f942feeb86924","unresolved":false,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"c1d7a012_5c7a0a0b","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"in_reply_to":"0d0bf7cc_d0268e49","updated":"2021-11-08 11:33:38.000000000","message":"Done","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":true,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0d0bf7cc_d0268e49","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"in_reply_to":"47219e77_3c8454e4","updated":"2021-11-08 06:51:13.000000000","message":"Please do","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"f114d317522898d68c2e4679c638a587b64b7216","unresolved":false,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"97ce9ff6_20ab406f","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"in_reply_to":"723f418c_8eeb6386","updated":"2021-09-06 17:59:00.000000000","message":"Sometimes I use RESET pin when microcontroller is in sleep mode (reset config srtst_only). Due to RC reset hardware circuit some delay after reset is required before connect.","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7b0cf2c424eb71fce053d922d7ff130dee123f69","unresolved":true,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"d09dd7a2_598ac539","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"in_reply_to":"97ce9ff6_20ab406f","updated":"2021-09-06 19:22:03.000000000","message":"Again, the delay is not required by the MCU itself, so it should be in board config, not here","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"400561e0bf132803c557ed2e52306ba25d4a99bd","unresolved":true,"context_lines":[{"line_number":53,"context_line":"# JTAG speed should be \u003c\u003d F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG \u003d 1MHz"},{"line_number":54,"context_line":"adapter speed 1000"},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"adapter srst delay 100"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"reset_config srst_nogate"},{"line_number":59,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"47219e77_3c8454e4","line":56,"range":{"start_line":56,"start_character":0,"end_line":56,"end_character":22},"in_reply_to":"d09dd7a2_598ac539","updated":"2021-09-07 11:01:25.000000000","message":"At this point you are right. This is needed only for special configuration (not default). STM32F0x also has this parameter. I can remove this.","commit_id":"c4d2779a4e4d4d8d13f3ef6dd8043f3ad6e53e59"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":true,"context_lines":[{"line_number":16,"context_line":"   set _CHIPNAME gd32e23x"},{"line_number":17,"context_line":"}"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"set _ENDIAN little"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"# Work-area is a space in RAM used for flash programming"},{"line_number":22,"context_line":"# By default use 4kB (as found on some GD32E230s)"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"a09bf5de_5146214e","line":19,"range":{"start_line":19,"start_character":0,"end_line":19,"end_character":18},"updated":"2021-11-08 06:51:13.000000000","message":"Please remove, Cortex-M has no configurable endianess. Sorry, I a bit noticed late, when I reviewed Michael\u0027s version.","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"2e135feb52c9c5a3b853ed416f3f942feeb86924","unresolved":false,"context_lines":[{"line_number":16,"context_line":"   set _CHIPNAME gd32e23x"},{"line_number":17,"context_line":"}"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"set _ENDIAN little"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"# Work-area is a space in RAM used for flash programming"},{"line_number":22,"context_line":"# By default use 4kB (as found on some GD32E230s)"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"406c2975_c5a4c258","line":19,"range":{"start_line":19,"start_character":0,"end_line":19,"end_character":18},"in_reply_to":"a09bf5de_5146214e","updated":"2021-11-08 11:33:38.000000000","message":"Done","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9e40cbb3228fbfe8cf40b11685e2ecdf5888a3c6","unresolved":true,"context_lines":[{"line_number":46,"context_line":"dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":49,"context_line":"target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":52,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"e0ca56e5_24406451","line":49,"range":{"start_line":49,"start_character":36,"end_line":49,"end_character":53},"updated":"2021-11-08 06:51:13.000000000","message":"Remove","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"2e135feb52c9c5a3b853ed416f3f942feeb86924","unresolved":false,"context_lines":[{"line_number":46,"context_line":"dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":49,"context_line":"target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":52,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"21bcc1b3_a61be0ff","line":49,"range":{"start_line":49,"start_character":36,"end_line":49,"end_character":53},"in_reply_to":"e0ca56e5_24406451","updated":"2021-11-08 11:33:38.000000000","message":"Done","commit_id":"261ae4519bf13876daf41263bec15cc79f77088b"}]}