)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"128a82e6d5e478c2079246f359a897acb045c537","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"069c59ad_1d97197d","updated":"2021-10-05 15:51:44.000000000","message":"Eh, no sorry, totally misread what the patch did, I\u0027ll restore your code snippet, although I\u0027m not particularly fond of very target specific quirks sprinkled around in otherwise generic code. This and the TI BE32 thing should need some refactoring.","commit_id":"ced1ec9214ddaa321578f135b5cfec6e39ea6937"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"f1769411acc9b4a60493cb2eaca806e3834fdfed","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"7605073b_b2782d1a","updated":"2021-10-05 15:48:21.000000000","message":"This should be equivalent, right? Please check.\n\nAlso, abandon all the other fixup commits and make sure to keep the Change-Id line from this commit in case you need to push any further version of this change. ","commit_id":"ced1ec9214ddaa321578f135b5cfec6e39ea6937"},{"author":{"_account_id":1001932,"name":"Ben Bender","email":"ben.bender@nuvoton.com","username":"benjbender"},"change_message_id":"181d3b0032dc5f2e0391887e0eb6c06feff19731","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"1ceb5837_25dec377","updated":"2022-03-30 15:16:37.000000000","message":"\u003e Patch Set 4:\n\u003e \n\u003e Hi,\n\u003e \n\u003e Are there any new developments re this issue?\n\u003e \n\u003e Ben Bender\n\nHi Antonio, Andreas and Wealian,\nAfter a lengthy verification in the NPCX design, we concluded that this bug is isolated to NPCX and probably also the NPCD (SIO) families. The issue was an incorrect bridge between the coresight and the AHB bus. The bug isn\u0027t present in our other M4 implementations. Therefore, I advise to go ahead with the patch as this will greatly benefit our costumers.\n\nThank you all.  ","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"d56bc20384feed3693d9be801539c8cf40f253ed","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"f9674373_0869bd6f","updated":"2021-10-17 09:42:57.000000000","message":"\u003e The fix is for all debuggers except jlink native. I was quite surprised when I discovered jlink duplicated all the lanes for bytes access. This seems to be different than the adi v5 spec.\n\nI suspect that jlink uses this method as a fix for one errata from ARM. Maybe this should be done in OpenOCD too, as default or after run-time detection.\nDo you have the possibility to talk with the SoC design team in Nuvoton? They \"must\" receive from ARM the list of errata that affect all the licensed IP blocks.\nThis could help us to better understand the limitation, what the do in OpenOCD, and even to correctly report the quirk as ARM error instead of blaming Nuvoton for it. The errata also reports the way to detect and how to workaround the issue.\nI have quickly searched in ARM errata, but didn\u0027t found anything really relevant. Only in \"CoreSight SoC-400 (TM100) Software Developer Errata Notice\" there are two issues on TAR HADDR[1:0] that could be interesting, but not sure are related with this.\nIf you get the full errata list from designers, you will probably not be allowed to report it here for confidentiality. It doesn\u0027t matter; if you can check them in ARM website and sort out the right one it would be enough.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1001932,"name":"Ben Bender","email":"ben.bender@nuvoton.com","username":"benjbender"},"change_message_id":"6fd7e5264094779f7970752a65eee0cbdd377f06","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"9a8ceeb7_251c3e2b","updated":"2022-04-06 14:39:34.000000000","message":"I wrote the added lines below. \nI\u0027m not sure it\u0027s being sent so I\u0027ll just go ahead and add them here as well.\n\n@deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}]\nSet/get quirks mode for Nuvoton NPCX/NPCD MCU families\nDisabled by default\n@end deffn\n\nRegards,\nBen","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3fb011e98285bf449645ce44b992b4f0e9922fa0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"947d3f1a_cdc0f033","updated":"2021-10-16 21:01:37.000000000","message":"Looks ok to me, even if it\u0027s an odd quirk.\nI\u0027m curious to know if this is a fix for OpenOCD only, or you had to set the same for other debuggers.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3aacab622e5635a55a8f6ee6126a3cb83c5e9b5f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"ca3e17a4_ac1eed8e","updated":"2022-03-31 07:21:19.000000000","message":"Ok, then. We can proceed with this fix.\nOnly remaining concern is that the new command \"nu_npcx_quirks\" is not documented. Can you add it?\nI have put a comment where it should go.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"85b414cf628ad24a1b5f1fc39b2e2da3f464bbc5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"f8d5754b_8a01bb83","updated":"2021-10-17 10:18:02.000000000","message":"The board npcx_evb embeds one jlink\nhttps://review.openocd.org/c/openocd/+/5950/17/tcl/board/npcx_evb.cfg\nIt\u0027s also possible that Nuvoton is using a special jlink FW to deal with the issue.\nIt could be interesting to check with a stand-alone off-the-shelf jlink adapter.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000005,"name":"Andreas Fritiofson","email":"andreas.fritiofson@gmail.com","username":"Nattgris"},"change_message_id":"aee383a64dd43d3f054282220e8168328dec0c43","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"750254d6_47611443","updated":"2021-10-05 16:12:35.000000000","message":"There. By the way, how does this work with packed transfers, where we don\u0027t control how the bytes are arranged?\n","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3aacab622e5635a55a8f6ee6126a3cb83c5e9b5f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"75aaa829_3c2cb373","in_reply_to":"17d24a20_47e9aa5b","updated":"2022-03-31 07:21:19.000000000","message":"\u003e So, it turns out, I am a Nuvoton engineer. (who would have thought)\nI know! Google has powers!","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c839588f6975151b50a68e59b0dc44755a52d51a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"ccd9c2ea_f097f310","in_reply_to":"9a8ceeb7_251c3e2b","updated":"2022-04-20 21:13:38.000000000","message":"Ben, the text you wrote looks ok, but I mean adding it inside the file doc/openocd.texi as part of the patch.\nEvery new command should be added with its documentation in openocd.texi.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1001932,"name":"Ben Bender","email":"ben.bender@nuvoton.com","username":"benjbender"},"change_message_id":"181d3b0032dc5f2e0391887e0eb6c06feff19731","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"17d24a20_47e9aa5b","in_reply_to":"ece20682_65ef846d","updated":"2022-03-30 15:16:37.000000000","message":"So, it turns out, I am a Nuvoton engineer. (who would have thought)\nI didn\u0027t logged in with my Nuvoton email b/c of oauth difficulty. I added it now.\n\nIn any case, as we discussed. this not a Cortex-M4 issue. Only an NPCX device issue. So therefore I recommend merging this patch. Wealian can back me up on this too.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1001833,"name":"Wealian Liao","email":"WHLIAO@nuvoton.com","username":"Wealian"},"change_message_id":"9b5021c63f1ebb346d694cb27411fcb85c25d4f1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"ece20682_65ef846d","in_reply_to":"f9674373_0869bd6f","updated":"2021-10-18 03:51:42.000000000","message":"It seems the symptom appears when writing data to 8-bits \u0026 16-bit registers which address without 4-byte aligned. I will check with our design team whether we have any errata related to this one.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"77d349109278097374bfe973ee806e8e9a67e40d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"89e5dc81_ecb1b39d","updated":"2022-07-05 14:48:46.000000000","message":"Thanks!","commit_id":"aee00791a480b1cf3deb81db18c9905fcc0851bb"}],"doc/openocd.texi":[{"author":{"_account_id":1001932,"name":"Ben Bender","email":"ben.bender@nuvoton.com","username":"benjbender"},"change_message_id":"6fd7e5264094779f7970752a65eee0cbdd377f06","unresolved":false,"context_lines":[{"line_number":4520,"context_line":"Set/get quirks mode for TI TMS450/TMS570 processors"},{"line_number":4521,"context_line":"Disabled by default"},{"line_number":4522,"context_line":"@end deffn"},{"line_number":4523,"context_line":""},{"line_number":4524,"context_line":""},{"line_number":4525,"context_line":"@node CPU Configuration"},{"line_number":4526,"context_line":"@chapter CPU Configuration"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"08eb6e9e_f703c0ad","line":4523,"updated":"2022-04-06 14:39:34.000000000","message":"@deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}]\nSet/get quirks mode for Nuvoton NPCX/NPCD MCU families\nDisabled by default\n@end deffn","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3aacab622e5635a55a8f6ee6126a3cb83c5e9b5f","unresolved":true,"context_lines":[{"line_number":4520,"context_line":"Set/get quirks mode for TI TMS450/TMS570 processors"},{"line_number":4521,"context_line":"Disabled by default"},{"line_number":4522,"context_line":"@end deffn"},{"line_number":4523,"context_line":""},{"line_number":4524,"context_line":""},{"line_number":4525,"context_line":"@node CPU Configuration"},{"line_number":4526,"context_line":"@chapter CPU Configuration"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"8838f765_b33d19cb","line":4523,"updated":"2022-03-31 07:21:19.000000000","message":"can you please add, here, a  short description of the new command?\nSomething similar to the format of the quirk command above.","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"},{"author":{"_account_id":1001932,"name":"Ben Bender","email":"ben.bender@nuvoton.com","username":"benjbender"},"change_message_id":"6fd7e5264094779f7970752a65eee0cbdd377f06","unresolved":false,"context_lines":[{"line_number":4520,"context_line":"Set/get quirks mode for TI TMS450/TMS570 processors"},{"line_number":4521,"context_line":"Disabled by default"},{"line_number":4522,"context_line":"@end deffn"},{"line_number":4523,"context_line":""},{"line_number":4524,"context_line":""},{"line_number":4525,"context_line":"@node CPU Configuration"},{"line_number":4526,"context_line":"@chapter CPU Configuration"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"560fd075_d836ccf9","line":4523,"in_reply_to":"8838f765_b33d19cb","updated":"2022-04-06 14:39:34.000000000","message":"@deffn {Config Command} {$dap_name nu_npcx_quirks} [@option{enable}]\nSet/get quirks mode for Nuvoton NPCX/NPCD MCU families\nDisabled by default\n@end deffn","commit_id":"e003fa4610d04f2d0f98017a5bfc2021bc00d0c0"}]}