)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"9c1ff2c8b715af8cf78df5d4d95379bcbcaecb3c","unresolved":true,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"d1749705_638dc191","line":16,"updated":"2021-12-06 19:05:36.000000000","message":"The RISC-V debug spec allows optional support for memory access when the target is running. Not all hardware implements this, and I was under the impression that OpenOCD doesn\u0027t support memory access while a target is running in any case.\n\nIt\u0027s certainly simpler not to rely on it, but this comment is incorrect.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"e1137b08de551d3b9a1e81faa4cba4ef2e30e915","unresolved":false,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"f1903197_ffdecaa3","line":16,"in_reply_to":"1bccdb00_b0ead491","updated":"2021-12-07 19:09:51.000000000","message":"I think it\u0027s generally not implemented on tiny single-core devices, and generally is on large multi-core devices. In between it depends. In the last couple of years it\u0027s been standard on all SiFive cores.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"9edf217fe0a5009864544a4e0f2bfce4dae527a2","unresolved":false,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"df3aced8_e8dc411a","line":16,"in_reply_to":"56de14d9_7a8f8d96","updated":"2021-12-07 00:17:56.000000000","message":"@Antonio, we can (and do) discover in examine() whether system bus access is supported.\n\nSystem bus access is the only option that has implementations which allows for accessing memory while running. There\u0027s another option in the spec named Quick Access, but I\u0027m not aware of any implementations, and OpenOCD doesn\u0027t support it. This explains why there is the seemingly duplicated information in `riscv info` output. Some day Quick Access support will be added, and this way today\u0027s software can simply check for target.memory.{read,write}_while_running{8,16,32,64,128} instead of needing to be updated when that happens.\n\nI think the current implementation is completely fine, but I did want to point out that some RISC-V targets do support memory access while running.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1f03c5eeaa1b695991a62dd264c45b05a0a1d8a6","unresolved":true,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"56de14d9_7a8f8d96","line":16,"in_reply_to":"d1749705_638dc191","updated":"2021-12-06 21:31:02.000000000","message":"@Tim\nIt\u0027s interesting information for me. I wrote it under the impression of original gd32vf103.c code where the stm32f1x async algo was rewritten to something like simulate-async-by-chunking and missing start_algorithm and wait_algorithm implementations in target/riscv/riscv.c\n\nYour message motivated me to finally read a part of \"RISC-V External Debug Support\nVersion 0.13.2\". So if I understand correctly, OpenOCD with running RISC-V target does not support progbuf memory access and supports sysbus and/or abstract if implemented on RISC-V hw. \n\nThe flash driver handles internal flash, so we get following riscv info on this device:\n\n hart.xlen              32\n hart.trigger_count      0\n target.memory.read_while_running8   0\n target.memory.write_while_running8   0\n target.memory.read_while_running16   0\n target.memory.write_while_running16   0\n target.memory.read_while_running32   0\n target.memory.write_while_running32   0\n target.memory.read_while_running64   0\n target.memory.write_while_running64   0\n target.memory.read_while_running128   0\n target.memory.write_while_running128   0\n dm.abits                7\n dm.progbufsize          2\n dm.sbversion            0\n dm.sbasize              0\n dm.sbaccess128          0\n dm.sbaccess64           0\n dm.sbaccess32           0\n dm.sbaccess16           0\n dm.sbaccess8            0\n dm.authenticated        1\n\nTBH I don\u0027t understand why all dm.sbaccessX and target.memory.read/write_while_runningX are printed, it is 3 times the exactly same bit.\nHmm, bad luck, the device has no sysbus access.\n\nAnd any read while running shows\n\n \u003e mdw 0x8000000\n Failed to read priv register.\n Target gd32v.cpu: Failed to read memory (addr\u003d0x8000000)\n  progbuf\u003dskipped (target not halted), sysbus\u003dskipped (unsupported size), abstract\u003dfailed\n\nSo if I haven\u0027t missed something, neither abstract access possible. No wonder on a cheap Chinese device.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"85d61a50f864a5ff022c2b9c7be637bd19b17a48","unresolved":true,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"6698c3d5_9632bcbf","line":16,"in_reply_to":"d1749705_638dc191","updated":"2021-12-06 20:51:51.000000000","message":"Is there any flag that can be checked at examine() to know if the specific implementation allows memory access at target running?\nThis could in turn be used to set a flag in struct target.\nFor other CPU this flag can be statically assigned, e.g. true for Cortex-M, false or Cortex-A","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"3a7b9f77eef13dd03a694dc792484f900ef65330","unresolved":false,"context_lines":[{"line_number":13,"context_line":"and the address has 32 bits."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"In case of RISC-V CPU use simple chunked write algo - async algo"},{"line_number":16,"context_line":"cannot be used as RISC-V doesn\u0027t allow memory access when target"},{"line_number":17,"context_line":"is running."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"1bccdb00_b0ead491","line":16,"in_reply_to":"df3aced8_e8dc411a","updated":"2021-12-07 05:26:56.000000000","message":"@Tim,\nthanks for clarification.\nBTW I checked HiFive1 rev B board and no sysbus access too. Is it typical that RV32 devices doesn\u0027t implement this option?","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5b3a2eb8afdc59e5d8be26f9af229adbf1cd300f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"7566adce_666eb44d","updated":"2021-11-17 17:32:13.000000000","message":"Tested with Sipeed Longan Nano and FT232H based JTAG adapter.\nflash write_image (without erase) makes 16.081 KiB/s @ adapter speed 1000, 29.818 KiB/s @ 12000\nSetting of sector write protection works.\nDidn\u0027t test chip locking (don\u0027t have spare board).\n\n","commit_id":"7c63312f9096e90d82b959bec649d4a2cd594c7d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"98a889953aef76c7ec2469ae29656e453881702e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"58859b1a_232affb8","updated":"2021-11-22 10:58:19.000000000","message":"Device identification fails on hla target","commit_id":"c6d56f48fdfae83e32efd7b15d91012bece3b557"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"7402c2218b2899f4db44c8fb21bf660e30af4e1e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"5f1ee596_975f3ab0","updated":"2021-11-25 20:02:50.000000000","message":"Tested on Sipeed Longan Nano with J-Link as debug probe. Flash probing, erasing and programming worked fine.","commit_id":"0b1df4e1245d40b95aaa29d4bf3b2a7ad808054b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0b953819d4d44530115bbdf218f06f90bf87c8fe","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"7913353e_7fc89a44","updated":"2021-12-03 07:55:30.000000000","message":"Tested again with Sipeed Longan Nano and FT232H based JTAG adapter, now including sector protection and option read/write. HWWDG option was set and watchdog resets observed. No problems found.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"9c1ff2c8b715af8cf78df5d4d95379bcbcaecb3c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"cf1e6ff8_095fe726","updated":"2021-12-06 19:05:36.000000000","message":"This looks OK to me, but I don\u0027t have access to hardware to test it.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"f3238d49f13e1badcae066ed019c7b6937818e99","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"986f816d_b7014863","updated":"2022-03-10 19:29:37.000000000","message":"Code still looks good.","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"f267d489072b9f8c8c3cceabd1caaacbd2df776e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"3a9528a0_3c26b039","updated":"2022-04-11 18:00:43.000000000","message":"I\u0027ve bought a Longan Nano board, and confirmed that this code works correctly with it.","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"664c7658f17f120d059e38e390132c97c5255155","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"e02f9947_008c791f","updated":"2022-03-09 19:17:17.000000000","message":"What is this change waiting for?","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"f3238d49f13e1badcae066ed019c7b6937818e99","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"2d6b6c61_ec6318de","in_reply_to":"1d483f47_41a43462","updated":"2022-03-10 19:29:37.000000000","message":"What changes does it depend on? The ones listed as \"Indirect ancestor\" in the top right here? Those both look trivial.","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7f8c36c168a9bf8a5bf81b95c3a5055a9b26be34","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"17833d41_1d452452","in_reply_to":"2d6b6c61_ec6318de","updated":"2022-03-10 20:29:38.000000000","message":"No. This one depends on changes shown under it in the relation chain:\nfrom 6753: Revert \"target: reset target examined flag if target::examine() fails\" | https://review.openocd.org/c/openocd/+/6753\nto 6710: flash/nor/stm32f1x: lock flash in case of error | https://review.openocd.org/c/openocd/+/6710\n5 of 6 changes are not reviewed.","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"fb151dd8d6601d4b43a68875db0ca403f0c166c3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"1d483f47_41a43462","in_reply_to":"e02f9947_008c791f","updated":"2022-03-09 20:36:34.000000000","message":"Mainly for merging the changes it depends on.\nBTW Refreshing of the positive review score is welcomed.","commit_id":"4602a6c9aadedf616e06f8a196a2056691f58d1c"}],"src/flash/nor/stm32f1x.c":[{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"9c1ff2c8b715af8cf78df5d4d95379bcbcaecb3c","unresolved":true,"context_lines":[{"line_number":768,"context_line":"\tcase CORTEX_M_PARTNO_INVALID:"},{"line_number":769,"context_line":"\t\t/* Check for GD32VF103 with RISC-V CPU */"},{"line_number":770,"context_line":"\t\tif (strcmp(target_type_name(target), \"riscv\") \u003d\u003d 0"},{"line_number":771,"context_line":"\t\t\t\t\u0026\u0026 target_address_bits(target) \u003d\u003d 32) {"},{"line_number":772,"context_line":"\t\t\t/* There is nothing like arm common_magic in riscv_info_t"},{"line_number":773,"context_line":"\t\t\t * check text name of target and if target is 32-bit"},{"line_number":774,"context_line":"\t\t\t */"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"b34f8115_fa419c9e","line":771,"updated":"2021-12-06 19:05:36.000000000","message":"Does this not work on 64-bit targets?","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1f03c5eeaa1b695991a62dd264c45b05a0a1d8a6","unresolved":false,"context_lines":[{"line_number":768,"context_line":"\tcase CORTEX_M_PARTNO_INVALID:"},{"line_number":769,"context_line":"\t\t/* Check for GD32VF103 with RISC-V CPU */"},{"line_number":770,"context_line":"\t\tif (strcmp(target_type_name(target), \"riscv\") \u003d\u003d 0"},{"line_number":771,"context_line":"\t\t\t\t\u0026\u0026 target_address_bits(target) \u003d\u003d 32) {"},{"line_number":772,"context_line":"\t\t\t/* There is nothing like arm common_magic in riscv_info_t"},{"line_number":773,"context_line":"\t\t\t * check text name of target and if target is 32-bit"},{"line_number":774,"context_line":"\t\t\t */"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"c9dd3632_876f7196","line":771,"in_reply_to":"b34f8115_fa419c9e","updated":"2021-12-06 21:31:02.000000000","message":"The loader code is compiled for RV32. Also there is no 64-bit device with this type of flash. Be aware that the flash is *internal*.","commit_id":"4013d190778bd56689d1d8d93f655f12462c1b53"}]}