)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"ac8f6902c567cf30416b4ee721742eac2d0f8f99","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2ad5eeb8_f6de89f8","updated":"2021-12-01 09:45:03.000000000","message":"I\u0027ve checked user manuals and I think that your change should work.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"bd4201c90cb7c88393925c53a828efbefeeeb1a6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"7622c487_935ca85b","in_reply_to":"04c4872d_61dd7ff6","updated":"2021-12-06 08:20:34.000000000","message":"I\u0027ve done tests using CMSIS-DAP interface. Now I can see:\nstm32f1x.cpu: external reset detected\nI\u0027ve done all tests and also double checked that hardware reset really works after setting it and do options_load.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"d27a56bc114836b62a3cd0c0be7e0f03e54b1c43","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"bceca057_d6624331","in_reply_to":"13379445_723c6f81","updated":"2021-12-03 14:15:12.000000000","message":"\u003e This is the same what I did. I have no device to test so I would appreciate if somebody test it on real hw.\n\u003e \n\u003e Working option load is nicely indicated by a msg \"external reset detected\".\n\u003e Of course testing with a real change in options (HWWDG seems easiest to track) is preferred.\n\n\nI tested this patch with GD32F130C8T6 and with GD32E230C8T6.\nWithout patch:\n\n\u003e stm32f1x options_load 0\n\u003e Command not applicable to stm32f1x devices - power cycle is required instead.\n\nWith patch:\n\u003e stm32f1x options_load 0\n\u003e stm32f1x options_read 0\n\u003e Target not halted\n\nThere was no message about external reset. Read options command showed that target is not halted, so reset occured.\nThen I changed option to HWWDG, did options_load and after init/reset halt did options_read to confirm that change was made. Everything was ok. I also checked change back option to default SWWDG and it also worked.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e2c4329a778c1bc2f4cbd2e786710ef17c8e4f1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"13379445_723c6f81","in_reply_to":"2ad5eeb8_f6de89f8","updated":"2021-12-03 08:53:41.000000000","message":"\u003e I\u0027ve checked user manuals...\n\nThis is the same what I did. I have no device to test so I would appreciate if somebody test it on real hw.\n\nWorking option load is nicely indicated by a msg \"external reset detected\".\nOf course testing with a real change in options (HWWDG seems easiest to track) is preferred.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c688d641488af40b081cefab1b1c9c0fbea82e00","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"4d5527b2_975667a7","in_reply_to":"7622c487_935ca85b","updated":"2021-12-06 08:27:27.000000000","message":"Thanks a lot, Andrzej!","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"8d13113d65087875c64ff0d6718ca715147d7784","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"04c4872d_61dd7ff6","in_reply_to":"98ef76b0_4911f938","updated":"2021-12-03 19:07:34.000000000","message":"openocd.exe -f interface/stlink.cfg -c \"transport select hla_swd\" -f target/stm32f1x.cfg\nI observed only telnet console..\nI can repeat tests again at work on Monday.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"238fdfaa8caf409c120e2b0cea70150cc4539e35","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"ce50394d_c449ba0d","in_reply_to":"bceca057_d6624331","updated":"2021-12-03 17:04:07.000000000","message":"Thanks for testing!\n\n\u003e There was no message about external reset. Read options command showed that target is not halted, so reset occured.\n\nThis is strange. Did you use ST/GD-Link in HLA mode? Can you retry with dapdirect-swd (use interface/stlink-dap.cfg - is GD-Link compatible with dapdirect?) or any no HLA adapter?\nOr did you change debug_level? Minimum for the info msg is 2, i.e. default level.\n\n\u003e Then I changed option to HWWDG, did options_load and after init/reset halt did options_read to confirm that change was made.\n\nHopefully it\u0027s ok. To be sure HWWDG is set I always run a target app which does not update WDG and observe if ext reset msg repeats. Will GD behave this way? It should  ... I\u0027d better check with STM32F03x and STM32F3x if there isn\u0027t a regression from\n6180: target/cortex_m: cumulate DHCSR sticky bits | https://review.openocd.org/c/openocd/+/6180","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"cf22edb283edd8dd3c6b65027ae448299782f07f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"98ef76b0_4911f938","in_reply_to":"ce50394d_c449ba0d","updated":"2021-12-03 18:06:17.000000000","message":"dapdirect:\n openocd -f interface/stlink-dap.cfg -f target/stm32f3x.cfg -c \u0027reset_config srst_only\u0027\n ...\n Info : auto-selecting first available session transport \"dapdirect_swd\"...\n ...\n Info : STLINK V2J29S0 (API v2) VID:PID 0483:3748\n ...\n \u003e reset init\n target halted due to debug-request, current mode: Thread\n xPSR: 0x01000000 pc: 0x080040b4 msp: 0x20000648\n \u003e stm32f3x options_load 0\n device id \u003d 0x10036422\n flash size \u003d 256kbytes\n stlink_dap_op_connect(reconnect)\n SWD DPIDR 0x2ba01477\n stm32f3x.cpu: external reset detected\n \u003e reset init\n ...\n \u003e stm32f1x options_write 0 HWWDG\n stm32x write options complete.\n INFO: \u0027stm32f1x options_load\u0027 command or power cycle is required for the new settings to take effect.\n \n \u003e stm32f3x options_load 0\n stlink_dap_op_connect(reconnect)\n SWD DPIDR 0x2ba01477\n stm32f3x.cpu: external reset detected\n stm32f3x.cpu: external reset detected\n stm32f3x.cpu: external reset detected\n ...\n\nHLA:\n openocd -f interface/stlink.cfg -f target/stm32f3x.cfg -c \u0027reset_config srst_only\u0027\n ...\n Info : auto-selecting first available session transport \"hla_swd\". To override use \u0027transport select \u003ctransport\u003e\u0027.\n Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD\n ...\n \u003e reset init\n target halted due to debug-request, current mode: Thread\n xPSR: 0x01000000 pc: 0x080040b4 msp: 0x20000648\n \u003e stm32f3x options_load 0\n device id \u003d 0x10036422\n flash size \u003d 256kbytes\n jtag status contains invalid mode value - communication failure\n Polling target stm32f3x.cpu failed, trying to reexamine\n Examination failed, GDB will be halted. Polling again in 100ms\n Previous state query failed, trying to reconnect\n Polling target stm32f3x.cpu failed, trying to reexamine\n stm32f3x.cpu: Cortex-M4 r0p1 processor detected\n stm32f3x.cpu: target has 6 breakpoints, 4 watchpoints\n \u003e reset init\n ...\n \u003e stm32f1x options_write 0 HWWDG\n stm32x write options complete.\n INFO: \u0027stm32f1x options_load\u0027 command or power cycle is required for the new settings to take effect.\n \n \u003e stm32f3x options_load 0\n jtag status contains invalid mode value - communication failure\n Polling target stm32f3x.cpu failed, trying to reexamine\n Examination failed, GDB will be halted. Polling again in 100ms\n Previous state query failed, trying to reconnect\n Polling target stm32f3x.cpu failed, trying to reexamine\n stm32f3x.cpu: Cortex-M4 r0p1 processor detected\n stm32f3x.cpu: target has 6 breakpoints, 4 watchpoints\n\nNo external resets detected.\nLooks ok on STM32F3.","commit_id":"4ae0fe90671ba3755c8e47b2c8cdda2a4dce1344"}]}