)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4b6ee6d36a06578c0f127dc9ee9c06038836d03d","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e"},{"line_number":5,"context_line":"CommitDate: 2021-12-26 13:27:45 +0100"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"Add GD32E50x Support"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"See user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference."},{"line_number":10,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"ff3daf47_663519c9","line":7,"updated":"2021-12-27 08:01:49.000000000","message":"Please specify touched driver \u0027flash/stm32f1x: Add GD...\u0027","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":4,"context_line":"Commit:     Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e"},{"line_number":5,"context_line":"CommitDate: 2021-12-26 13:27:45 +0100"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"Add GD32E50x Support"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"See user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference."},{"line_number":10,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"e127d107_b286deb5","line":7,"in_reply_to":"ff3daf47_663519c9","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4b6ee6d36a06578c0f127dc9ee9c06038836d03d","unresolved":true,"context_lines":[{"line_number":22,"context_line":"* \"flash info 0\" shows expected protected page layout"},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"Remaining bugs:"},{"line_number":25,"context_line":"* after core is halted (\"halt\" command), MCU seems to reset continously, but always after a different delay (between 5 seconds and 2 minutes). error messages: \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine, SWD DPIDR 0x0be12477, gd32e50x.cpu: Cortex-M33 r0p4 processor detected, gd32e50x.cpu: target has 8 breakpoints, 4 watchpoints\""},{"line_number":26,"context_line":"* looks like watchdog reset, but examination of DBG_CTL register via \"mrw 0xE0044004\" shows all relevant bits are on -- no idea what\u0027s happening here"},{"line_number":27,"context_line":"* tests done with Linux guest VM (VirtualBox) inside Windows host and USB forwarding, did not test on Windows host itslef"},{"line_number":28,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"57fa1a5f_ebbd8676","line":25,"range":{"start_line":25,"start_character":160,"end_line":25,"end_character":186},"updated":"2021-12-27 08:01:49.000000000","message":"This is a problem at USB communication level, not watchdog related. Try without virtualization first, if it doesn\u0027t help connect GD-Link to other USB port/other computer or even better use a different adapter.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":22,"context_line":"* \"flash info 0\" shows expected protected page layout"},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"Remaining bugs:"},{"line_number":25,"context_line":"* after core is halted (\"halt\" command), MCU seems to reset continously, but always after a different delay (between 5 seconds and 2 minutes). error messages: \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine, SWD DPIDR 0x0be12477, gd32e50x.cpu: Cortex-M33 r0p4 processor detected, gd32e50x.cpu: target has 8 breakpoints, 4 watchpoints\""},{"line_number":26,"context_line":"* looks like watchdog reset, but examination of DBG_CTL register via \"mrw 0xE0044004\" shows all relevant bits are on -- no idea what\u0027s happening here"},{"line_number":27,"context_line":"* tests done with Linux guest VM (VirtualBox) inside Windows host and USB forwarding, did not test on Windows host itslef"},{"line_number":28,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"52ddfabd_53f187a6","line":25,"range":{"start_line":25,"start_character":160,"end_line":25,"end_character":186},"in_reply_to":"57fa1a5f_ebbd8676","updated":"2021-12-27 22:10:00.000000000","message":"Ack","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"e6bc155e_483f6a08","updated":"2021-12-27 09:37:19.000000000","message":"I can see that you made the same mistakes as I did when starting my adventure with GigaDevice ;)\nUsing wrong option bits location in FMC_OBSTAT makes bits WDG_SW, nRST_STOP, nRST_STDBY set in not default values.. Your experiments with configurations for different GD32 devices probably set hardware watchdog in your testing microcontroller. Plaese use tools from GigaDevice (GD-Link Programmer) to connect to this microcontroller, read all configuration bits, check them and update with default factory values. Then continue your work on patch.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4b6ee6d36a06578c0f127dc9ee9c06038836d03d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"508c0c3e_71cd62ea","updated":"2021-12-27 08:01:49.000000000","message":"Max, thanks for contribution!\nThe change looks good.\nUnfortunately there are pending changes of stm32f1x driver, e.g.\n6704: flash/stm32f1x: add support for RISC-V GigaDevice GD32VF103 | https://review.openocd.org/c/openocd/+/6704\nso this one should wait for merging them.\n\nAlso feel free to join the discussion at\n6543: add GigaDevice GD32Exxx flash driver | https://review.openocd.org/c/openocd/+/6543","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"04cd1a32_f3d728b4","in_reply_to":"e6bc155e_483f6a08","updated":"2021-12-27 22:10:00.000000000","message":"Ack","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"021733734095b5776bb7f9271742e4f97a420d7d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"eacac953_cfa118c2","updated":"2021-12-28 07:17:46.000000000","message":"Max,\nyou submitted patchset 3 with commit message changes but stm32f1x.c and gd32e50x.cfg files are unchanged. Make sure to issue \u0027git add .\u0027 or \u0027git add -p\u0027 before \u0027git commit --amend\u0027","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"dde965ff_4a071bb1","updated":"2021-12-27 22:10:00.000000000","message":"Thanks for both of your reviews, I addressed them in the new code, config file and commit message changes. \n\nI can still flash binaries and debug fine with it, just have to test OpenOCD with my native Windows machine and another USB cable (mine seems to have a loose connection) to make sure these \"error writing (null)\" errors don\u0027t come from the changed code.","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"2c64ec38a429cbfeff44076335eee0859a18f42a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"78568bbb_ffc81c2f","in_reply_to":"788ef3ab_ad02151c","updated":"2021-12-28 16:16:46.000000000","message":"Thanks, I think now this commit is on track again.","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"57fb65a087926830562a6c19f40ad400ed2b11d7","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"ef35d6fa_b685de9c","in_reply_to":"eacac953_cfa118c2","updated":"2021-12-28 11:41:44.000000000","message":"Well I did first do an amment and then a git commit -s -a which has entirely messed up the git flow and a git push review now created a new patch request https://review.openocd.org/c/openocd/+/6795 \n\nCan I still rescue this ticket or is it done for?","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"bb7f784f1616d1a7d9f822472e287c4920d96de5","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"788ef3ab_ad02151c","in_reply_to":"ef35d6fa_b685de9c","updated":"2021-12-28 13:15:57.000000000","message":"You restored 6795. But we want to move changes from 6795 to the new patchset of 6794.\nOpen 6795 in gerrit, use DOWNLOAD button and select checkout. Paste the command and run it in your local OpenOCD copy. Check \u0027git log\u0027, the first two commits should be 6af9f57d2608a69dc2f358653d8b39d59df7b998 and ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348\nNow issue \u0027git reset --soft ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348\u0027\nYou may do other changes and \u0027git add -p\u0027 them.\nThen \u0027git commit --amend\u0027 and \u0027git push review\u0027","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1002374,"name":"ALTracer","username":"ALTracer"},"change_message_id":"3e9f84ec4573784818d9e61896563d69834c9c74","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"3a3e10e1_b8dfb6f4","updated":"2025-02-08 08:01:54.000000000","message":"This PR worked in 2023 for GD32E508 when I\u0027ve tested it, I believe. If stm32f1x flash driver haven\u0027t diverged since then, please fix TAP ident for JTAG. Or I can pick it up myself.","commit_id":"14a5539a620c29499d020f3269f5d46d0713d80b"}],"src/flash/nor/stm32f1x.c":[{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[{"line_number":743,"context_line":"\t\t\tpage_size \u003d 8192; /* flash page size is 8Kbyte */"},{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"af5bc0d5_ae6cb57c","line":746,"range":{"start_line":746,"start_character":35,"end_line":746,"end_character":36},"updated":"2021-12-27 09:37:19.000000000","message":"it should be 10 (GigaDevice uses own terminology..)","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":743,"context_line":"\t\t\tpage_size \u003d 8192; /* flash page size is 8Kbyte */"},{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"c5569d8c_5887dc7d","line":746,"range":{"start_line":746,"start_character":35,"end_line":746,"end_character":36},"in_reply_to":"af5bc0d5_ae6cb57c","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"},{"line_number":750,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"5350bdf6_bea764af","line":747,"range":{"start_line":747,"start_character":32,"end_line":747,"end_character":34},"updated":"2021-12-27 09:37:19.000000000","message":"It should be 0 (not 2 because spc and obr are included historically). Compare to manual for GD32F103 that has identical bits location.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"},{"line_number":750,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"024d4dd1_66294a92","line":747,"range":{"start_line":747,"start_character":32,"end_line":747,"end_character":34},"in_reply_to":"5350bdf6_bea764af","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"},{"line_number":750,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"},{"line_number":751,"context_line":"\t\t\tpage_size \u003d 1024;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8b25d82d_8121d924","line":748,"range":{"start_line":748,"start_character":3,"end_line":748,"end_character":9},"updated":"2021-12-27 09:37:19.000000000","message":"not needed here","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 2; /* to the right of user_data there are only 2 bits (SPC, OBERR) */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 10; /* to the right of DATA, the are 10 bits */"},{"line_number":748,"context_line":"\t\t\tbreak;"},{"line_number":749,"context_line":"\t\t} else {"},{"line_number":750,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"},{"line_number":751,"context_line":"\t\t\tpage_size \u003d 1024;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"a1569cf6_35e4b5a3","line":748,"range":{"start_line":748,"start_character":3,"end_line":748,"end_character":9},"in_reply_to":"8b25d82d_8121d924","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"81af43a1c37456093a6b4e0c37adbd32555dee54","unresolved":true,"context_lines":[{"line_number":742,"context_line":"\t\tif (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003) {"},{"line_number":743,"context_line":"\t\t\tpage_size \u003d 8192; /* flash page size is 8Kbyte */"},{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 10; /* same as in GD32F103 */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 0;"},{"line_number":748,"context_line":"\t\t} else {"},{"line_number":749,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"},{"line_number":750,"context_line":"\t\t\tpage_size \u003d 1024;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"2808748c_febb0953","line":747,"range":{"start_line":745,"start_character":30,"end_line":747,"end_character":34},"updated":"2021-12-29 09:54:23.000000000","message":"This can be omitted since it is identical to the default values.","commit_id":"7d928552ed3b07972146ab2e43a5e3ba47ecafda"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"9aa48febca17f3021c122b3cf1c7c5ab2179af63","unresolved":false,"context_lines":[{"line_number":742,"context_line":"\t\tif (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003) {"},{"line_number":743,"context_line":"\t\t\tpage_size \u003d 8192; /* flash page size is 8Kbyte */"},{"line_number":744,"context_line":"\t\t\tstm32x_info-\u003eppage_size \u003d 1; /* 1 page per protection block, except for pages 31-63 */"},{"line_number":745,"context_line":"\t\t\tmax_flash_size_in_kb \u003d 512;"},{"line_number":746,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 10; /* same as in GD32F103 */"},{"line_number":747,"context_line":"\t\t\tstm32x_info-\u003eoption_offset \u003d 0;"},{"line_number":748,"context_line":"\t\t} else {"},{"line_number":749,"context_line":"\t\t\t/* stm32f03x, stm32f04x */"},{"line_number":750,"context_line":"\t\t\tpage_size \u003d 1024;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"158c7243_26b49d65","line":747,"range":{"start_line":745,"start_character":30,"end_line":747,"end_character":34},"in_reply_to":"2808748c_febb0953","updated":"2021-12-29 10:49:02.000000000","message":"Done","commit_id":"7d928552ed3b07972146ab2e43a5e3ba47ecafda"}],"tcl/target/gd32e50x.cfg":[{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[{"line_number":6,"context_line":"# https://www.gigadevice.com/microcontroller/gd32e503cet6/"},{"line_number":7,"context_line":""},{"line_number":8,"context_line":"#"},{"line_number":9,"context_line":"# gd32e50x devices support SWD transports only."},{"line_number":10,"context_line":"#"},{"line_number":11,"context_line":"source [find target/swj-dp.tcl]"},{"line_number":12,"context_line":"source [find mem_helper.tcl]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"6c4b236e_054b66f5","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":47},"updated":"2021-12-27 09:37:19.000000000","message":"As I\u0027ve seen on manual this microcontroller has also JTAG.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":6,"context_line":"# https://www.gigadevice.com/microcontroller/gd32e503cet6/"},{"line_number":7,"context_line":""},{"line_number":8,"context_line":"#"},{"line_number":9,"context_line":"# gd32e50x devices support SWD transports only."},{"line_number":10,"context_line":"#"},{"line_number":11,"context_line":"source [find target/swj-dp.tcl]"},{"line_number":12,"context_line":"source [find mem_helper.tcl]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"154c36aa_f7a6c00c","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":47},"in_reply_to":"6c4b236e_054b66f5","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c9b511be61b7967799d7d3d48d7e7c4969a74e79","unresolved":true,"context_lines":[{"line_number":64,"context_line":"    cortex_m reset_config sysresetreq"},{"line_number":65,"context_line":"}"},{"line_number":66,"context_line":""},{"line_number":67,"context_line":"$_TARGETNAME configure -event examine-end {"},{"line_number":68,"context_line":"\t# Debug clock enable"},{"line_number":69,"context_line":"\t# RCU_APB2EN |\u003d DBGMCUEN"},{"line_number":70,"context_line":"\tmmw 0x40021018 0x00400000 0"},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":73,"context_line":"\t# DBG_CTL |\u003d WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"aa529e5b_7dc0105b","line":70,"range":{"start_line":67,"start_character":43,"end_line":70,"end_character":28},"updated":"2021-12-27 09:37:19.000000000","message":"Remove this. Enabling debug clock is specific only for gd32e230. Here it is reserved bit.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"c8ed8728d97ad78d8f2f2ec796d1c73a5fd081f1","unresolved":false,"context_lines":[{"line_number":64,"context_line":"    cortex_m reset_config sysresetreq"},{"line_number":65,"context_line":"}"},{"line_number":66,"context_line":""},{"line_number":67,"context_line":"$_TARGETNAME configure -event examine-end {"},{"line_number":68,"context_line":"\t# Debug clock enable"},{"line_number":69,"context_line":"\t# RCU_APB2EN |\u003d DBGMCUEN"},{"line_number":70,"context_line":"\tmmw 0x40021018 0x00400000 0"},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":73,"context_line":"\t# DBG_CTL |\u003d WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"aab2db3a_a999f782","line":70,"range":{"start_line":67,"start_character":43,"end_line":70,"end_character":28},"in_reply_to":"aa529e5b_7dc0105b","updated":"2021-12-27 22:10:00.000000000","message":"Done","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4b6ee6d36a06578c0f127dc9ee9c06038836d03d","unresolved":false,"context_lines":[{"line_number":71,"context_line":""},{"line_number":72,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":73,"context_line":"\t# DBG_CTL |\u003d WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD"},{"line_number":74,"context_line":"\tmmw 0xE0044004 0x00000307 0"},{"line_number":75,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"01c2573b_631c9ff6","line":74,"range":{"start_line":74,"start_character":1,"end_line":74,"end_character":28},"updated":"2021-12-27 08:01:49.000000000","message":"I checked with the manual and can confirm it\u0027s correct.","commit_id":"4217c6a072334d7004709a3e4d66e431f0bd8f69"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"bb7f784f1616d1a7d9f822472e287c4920d96de5","unresolved":true,"context_lines":[{"line_number":72,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":73,"context_line":"\t# DBG_CTL |\u003d WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD"},{"line_number":74,"context_line":"\tmmw 0xE0044004 0x00000307 0"},{"line_number":75,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"49211d32_938d2dde","line":75,"updated":"2021-12-28 13:15:57.000000000","message":"Add newline at the end of file","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"change_message_id":"2c64ec38a429cbfeff44076335eee0859a18f42a","unresolved":false,"context_lines":[{"line_number":72,"context_line":"\t# Stop watchdog counters during halt"},{"line_number":73,"context_line":"\t# DBG_CTL |\u003d WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD"},{"line_number":74,"context_line":"\tmmw 0xE0044004 0x00000307 0"},{"line_number":75,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"f51a0542_7c7af54c","line":75,"in_reply_to":"49211d32_938d2dde","updated":"2021-12-28 16:16:46.000000000","message":"Done","commit_id":"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348"},{"author":{"_account_id":1002374,"name":"ALTracer","username":"ALTracer"},"change_message_id":"3e9f84ec4573784818d9e61896563d69834c9c74","unresolved":true,"context_lines":[{"line_number":38,"context_line":"   set _CPUTAPID $CPUTAPID"},{"line_number":39,"context_line":"} else {"},{"line_number":40,"context_line":"   if { [using_jtag] } {"},{"line_number":41,"context_line":"      # See GD32E50x User Manual section 12.2.3"},{"line_number":42,"context_line":"      set _CPUTAPID 0x790007A3"},{"line_number":43,"context_line":"   } {"},{"line_number":44,"context_line":"      # this is the SW-DP tap id not the jtag tap id"},{"line_number":45,"context_line":"      set _CPUTAPID 0x0be12477"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"1f73f946_b42bfa30","line":42,"range":{"start_line":41,"start_character":6,"end_line":42,"end_character":30},"updated":"2025-02-08 08:01:54.000000000","message":"No, 0x790007A3 is the Boundary Scan TAP ID for GigaDevice vendor. Add a separate bscan tap for it in case someone needs XSVF playback.\nCPU TAP is 0x0ba04477, where 0xba04 signifies Cortex-M33 JTAG-DP DPv1 MINDP supporting ADIv5, with DPIDR of 0x0be11477.","commit_id":"14a5539a620c29499d020f3269f5d46d0713d80b"}]}