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Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* user_data_offset \u003d 2 (bits), option_offset \u003d 10 (bits) hopefully correct per page 63\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining bugs:\n* after core is halted (\"halt\" command), MCU seems to reset continously, but always after a different delay (between 5 seconds and 2 minutes). error messages: \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine, SWD DPIDR 0x0be12477, gd32e50x.cpu: Cortex-M33 r0p4 processor detected, gd32e50x.cpu: target has 8 breakpoints, 4 watchpoints\"\n* looks like watchdog reset, but examination of DBG_CTL register via \"mrw 0xE0044004\" shows all relevant bits are on -- no idea what\u0027s happening here\n* tests done with Linux guest VM (VirtualBox) inside Windows host and USB forwarding, did not test on Windows host itslef\n\nRelated ticket: https://sourceforge.net/p/openocd/tickets/328/\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}},"ff85e16c08a23a7fb64b6d4ff30fbe8aa816a348":{"kind":"NO_CODE_CHANGE","_number":3,"created":"2021-12-27 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FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d27d66bc1bdbef0cbfe43d88597576e173317c01","subject":"Document how vector registers are exposed to gdb."}],"author":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:03:22.000000000","tz":60},"committer":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-27 22:01:32.000000000","tz":60},"subject":"flash/stm32f1x: Add GD32E50x Support","message":"flash/stm32f1x: Add GD32E50x Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* for user_data_offset \u003d 10 (bits), option_offset \u003d 0 (bits), see page 63, same as for GD32F103\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining topics:\n* When testing in a VM, the error message \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine\" occured, testing outside a VM is an outstanding task..\n* the \"if (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003)\" check might not get all E50x devices, only tested for one particular GD32E503CE chip.\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}},"49f69a73734bff7cbe9fb889951c15ff5a413a7e":{"kind":"REWORK","_number":1,"created":"2021-12-26 12:23:49.000000000","uploader":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"ref":"refs/changes/94/6794/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/94/6794/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/1 \u0026\u0026 git checkout -b change-6794 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/94/6794/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d27d66bc1bdbef0cbfe43d88597576e173317c01","subject":"Document how vector registers are exposed to gdb."}],"author":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:03:22.000000000","tz":60},"committer":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:22:52.000000000","tz":60},"subject":"Add GD32E50x Support","message":"Add GD32E50x Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* user_data_offset \u003d 2 (bits), option_offset \u003d 10 (bits) hopefully correct per page 63\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining bugs:\n* after core is halted (\"halt\" command), MCU seems to reset continously, but always after a different delay (between 5 seconds and 2 minutes). error messages: \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine, SWD DPIDR 0x0be12477, gd32e50x.cpu: Cortex-M33 r0p4 processor detected, gd32e50x.cpu: target has 8 breakpoints, 4 watchpoints\"\n* looks like watchdog reset, but examination of DBG_CTL register via \"mrw 0xE0044004\" shows all relevant bits are on -- no idea what\u0027s happening here\n* tests done with Linux guest VM (VirtualBox) inside Windows host and USB forwarding, did not test on Windows host itslef\n\nRelated ticket: https://sourceforge.net/p/openocd/tickets/328/\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}},"14a5539a620c29499d020f3269f5d46d0713d80b":{"kind":"REWORK","_number":6,"created":"2021-12-29 10:47:40.000000000","uploader":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"ref":"refs/changes/94/6794/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/94/6794/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/6 \u0026\u0026 git checkout -b change-6794 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/94/6794/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d27d66bc1bdbef0cbfe43d88597576e173317c01","subject":"Document how vector registers are exposed to gdb."}],"author":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:03:22.000000000","tz":60},"committer":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-29 10:46:49.000000000","tz":60},"subject":"flash/stm32f1x: Add GD32E50x Support","message":"flash/stm32f1x: Add GD32E50x Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* the default user_data_offset \u003d 10 (bits), option_offset \u003d 0 (bits), see page 63, are already correct, same as for GD32F103\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining topics:\n* When testing in a VM, the error message \"error writing data: (null)\", this does not happen outside a VM in the Windows host.\n* the \"if (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003)\" check might not get all E50x devices, only tested for one particular GD32E503CE chip.\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}},"18c50286840a06f8d7d2bf5322970a9c8288e592":{"kind":"REWORK","_number":4,"created":"2021-12-28 16:14:56.000000000","uploader":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"ref":"refs/changes/94/6794/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/94/6794/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/4 \u0026\u0026 git checkout -b change-6794 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/94/6794/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d27d66bc1bdbef0cbfe43d88597576e173317c01","subject":"Document how vector registers are exposed to gdb."}],"author":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:03:22.000000000","tz":60},"committer":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-28 16:14:27.000000000","tz":60},"subject":"flash/stm32f1x: Add GD32E50x Support","message":"flash/stm32f1x: Add GD32E50x Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* for user_data_offset \u003d 10 (bits), option_offset \u003d 0 (bits), see page 63, same as for GD32F103\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining topics:\n* When testing in a VM, the error message \"error writing data: (null), Polling target gd32e50x.cpu failed, trying to reexamine\" occured, testing outside a VM is an outstanding task..\n* the \"if (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003)\" check might not get all E50x devices, only tested for one particular GD32E503CE chip.\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}},"7d928552ed3b07972146ab2e43a5e3ba47ecafda":{"kind":"NO_CODE_CHANGE","_number":5,"created":"2021-12-28 16:19:54.000000000","uploader":{"_account_id":1001949,"name":"Maximilian Gerhardt","email":"maximilian.gerhardt@rub.de","username":"maxgerhardt"},"ref":"refs/changes/94/6794/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/94/6794/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/5 \u0026\u0026 git checkout -b change-6794 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/94/6794/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/94/6794/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d27d66bc1bdbef0cbfe43d88597576e173317c01","subject":"Document how vector registers are exposed to gdb."}],"author":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-26 12:03:22.000000000","tz":60},"committer":{"name":"Max Gerhardt","email":"maximilian.gerhardt@rub.de","date":"2021-12-28 16:19:04.000000000","tz":60},"subject":"flash/stm32f1x: Add GD32E50x Support","message":"flash/stm32f1x: Add GD32E50x Support\n\nSee user manual at https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf for reference.\n\nNotes / change justication:\n* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board CMSIS-DAP (\"GD-Link\") probe\n* SWD DPIDR: 0x0be12477\n* DBGMCU ID code: 0x20030444\n* device id part 0x444 overlaps with existing stm32f03x, had to add check on revision ID of my particular chip (0x2003) to avoid confusion, not too nice\n* device_id_register \u003d 0xE0044000 is correct per page 270\n* flash_size_reg \u003d 0x1FFFF7E0 is correct per page 44\n* page_size \u003d 8192, ppage_size \u003d 1 correct per page 47 and 57\n* for user_data_offset \u003d 10 (bits), option_offset \u003d 0 (bits), see page 63, same as for GD32F103\n* gd32e50x.cfg\u0027s DBG_CTL address and content correct per page 270\n* flashing of binaries and opening of a GDB server works (blinky example tested)\n* \"flash info 0\" shows expected protected page layout\n\nRemaining topics:\n* When testing in a VM, the error message \"error writing data: (null)\", this does not happen outside a VM in the Windows host.\n* the \"if (device_id \u003d\u003d 0x444 \u0026\u0026 rev_id \u003d\u003d 0x2003)\" check might not get all E50x devices, only tested for one particular GD32E503CE chip.\n\nSigned-off-by: Max Gerhardt \u003cmaximilian.gerhardt@rub.de\u003e\nChange-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"NOT_READY","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"NEED"}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"UNSATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"]}}]}