)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c1bfe4d08972fe7a6478717f728f677d5fe0e125","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"eabe25a3_e5a3557e","updated":"2022-04-16 22:01:02.000000000","message":"I will return on this review asap","commit_id":"76c540f1e58b95fec727144154d34ac965fd34b2"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"22b3f2a9f1228a2cef25e46e0091a5690ea6c740","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"63e94fc6_cbd4922b","updated":"2022-04-18 19:51:27.000000000","message":"I have completely forgot my old patch https://review.openocd.org/6681/\nAnyway, this is way better than mine. I will merge this, then rebase mine.","commit_id":"7dc69974cab2b0fe8e8ff2ca2238b552ecdcbc90"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"84e3fcf632f92157910333e881b6bf866d64d1b5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"2dfdf627_736cf06d","updated":"2022-04-18 19:49:09.000000000","message":"Ok, it should work, even if I cannot test it.\nThe only issue was the base address of GPIOE.\nI have checked the alternate function and it\u0027s the same as STM32F4.\nThanks!","commit_id":"7dc69974cab2b0fe8e8ff2ca2238b552ecdcbc90"}],"tcl/target/stm32l4x.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c1bfe4d08972fe7a6478717f728f677d5fe0e125","unresolved":true,"context_lines":[{"line_number":108,"context_line":"\t\tswitch [$_chipname.tpiu cget -port-width] {"},{"line_number":109,"context_line":"\t\t\t1 {"},{"line_number":110,"context_line":"\t\t\t\tmmw 0xE0042004 0x00000060 0x000000c0"},{"line_number":111,"context_line":"\t\t\t\tmmw 0x40021020 0x00000000 0x0000ff00"},{"line_number":112,"context_line":"\t\t\t\tmmw 0x40021000 0x000000a0 0x000000f0"},{"line_number":113,"context_line":"\t\t\t\tmmw 0x40021008 0x000000f0 0x00000000"},{"line_number":114,"context_line":"\t\t\t  }"},{"line_number":115,"context_line":"\t\t\t2 {"},{"line_number":116,"context_line":"\t\t\t\tmmw 0xE0042004 0x000000a0 0x000000c0"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0b8e1a20_743b7d73","line":113,"range":{"start_line":111,"start_character":1,"end_line":113,"end_character":40},"updated":"2022-04-16 22:01:02.000000000","message":"These three lines are taken from my code in tcl/target/stm32f4x.cfg and are to enable trace mode on GPIO PE[2:6].\nAlso on L4 the same GPIO PE[2:6] are for trace, but the base address for GPIOE controller is not anymore 0x40021000, but 0x48001000!\nIt should be enough changing the base address, but I want to take some more time checking this setup.","commit_id":"76c540f1e58b95fec727144154d34ac965fd34b2"},{"author":{"_account_id":1001977,"name":"Markus Reiter","email":"me@reitermark.us","username":"reitermarkus"},"change_message_id":"0628a51325ad06263c264481ae5d1100c969c28f","unresolved":true,"context_lines":[{"line_number":108,"context_line":"\t\tswitch [$_chipname.tpiu cget -port-width] {"},{"line_number":109,"context_line":"\t\t\t1 {"},{"line_number":110,"context_line":"\t\t\t\tmmw 0xE0042004 0x00000060 0x000000c0"},{"line_number":111,"context_line":"\t\t\t\tmmw 0x40021020 0x00000000 0x0000ff00"},{"line_number":112,"context_line":"\t\t\t\tmmw 0x40021000 0x000000a0 0x000000f0"},{"line_number":113,"context_line":"\t\t\t\tmmw 0x40021008 0x000000f0 0x00000000"},{"line_number":114,"context_line":"\t\t\t  }"},{"line_number":115,"context_line":"\t\t\t2 {"},{"line_number":116,"context_line":"\t\t\t\tmmw 0xE0042004 0x000000a0 0x000000c0"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"3ae54af5_853656aa","line":113,"range":{"start_line":111,"start_character":1,"end_line":113,"end_character":40},"in_reply_to":"0b8e1a20_743b7d73","updated":"2022-04-17 14:14:13.000000000","message":"I updated the GPIOE base address to 0x48001000.","commit_id":"76c540f1e58b95fec727144154d34ac965fd34b2"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c1bfe4d08972fe7a6478717f728f677d5fe0e125","unresolved":true,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"$_CHIPNAME.tpiu configure -event post-enable \"proc_post_enable $_CHIPNAME\""},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"$_TARGETNAME configure -event reset-init {"},{"line_number":136,"context_line":"\t# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz)."},{"line_number":137,"context_line":"\t# Use MSI 24 MHz clock, compliant even with VOS \u003d\u003d 2."},{"line_number":138,"context_line":"\t# 3 WS compliant with VOS \u003d\u003d 2 and 24 MHz."},{"line_number":139,"context_line":"\tmww 0x40022000 0x00000103   ;# FLASH_ACR \u003d PRFTBE | 3(Latency)"},{"line_number":140,"context_line":"\tmww 0x40021000 0x00000099   ;# RCC_CR \u003d MSI_ON | MSIRGSEL | MSI Range 9"},{"line_number":141,"context_line":""},{"line_number":142,"context_line":""},{"line_number":143,"context_line":""},{"line_number":144,"context_line":"\t# Boost JTAG frequency"},{"line_number":145,"context_line":"\tadapter speed 4000"},{"line_number":146,"context_line":"}"},{"line_number":147,"context_line":""},{"line_number":148,"context_line":"$_TARGETNAME configure -event reset-start {"},{"line_number":149,"context_line":"\t# Reset clock is MSI (4 MHz)"},{"line_number":150,"context_line":"\tadapter speed 500"},{"line_number":151,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"e2b29ffa_d06cde3d","line":151,"range":{"start_line":135,"start_character":0,"end_line":151,"end_character":1},"updated":"2022-04-16 22:01:02.000000000","message":"Please don\u0027t reorder the code, if there is no real reason for doing it.\nIt makes more time consuming reviewing the patch.","commit_id":"76c540f1e58b95fec727144154d34ac965fd34b2"},{"author":{"_account_id":1001977,"name":"Markus Reiter","email":"me@reitermark.us","username":"reitermarkus"},"change_message_id":"0628a51325ad06263c264481ae5d1100c969c28f","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"$_CHIPNAME.tpiu configure -event post-enable \"proc_post_enable $_CHIPNAME\""},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"$_TARGETNAME configure -event reset-init {"},{"line_number":136,"context_line":"\t# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz)."},{"line_number":137,"context_line":"\t# Use MSI 24 MHz clock, compliant even with VOS \u003d\u003d 2."},{"line_number":138,"context_line":"\t# 3 WS compliant with VOS \u003d\u003d 2 and 24 MHz."},{"line_number":139,"context_line":"\tmww 0x40022000 0x00000103   ;# FLASH_ACR \u003d PRFTBE | 3(Latency)"},{"line_number":140,"context_line":"\tmww 0x40021000 0x00000099   ;# RCC_CR \u003d MSI_ON | MSIRGSEL | MSI Range 9"},{"line_number":141,"context_line":""},{"line_number":142,"context_line":""},{"line_number":143,"context_line":""},{"line_number":144,"context_line":"\t# Boost JTAG frequency"},{"line_number":145,"context_line":"\tadapter speed 4000"},{"line_number":146,"context_line":"}"},{"line_number":147,"context_line":""},{"line_number":148,"context_line":"$_TARGETNAME configure -event reset-start {"},{"line_number":149,"context_line":"\t# Reset clock is MSI (4 MHz)"},{"line_number":150,"context_line":"\tadapter speed 500"},{"line_number":151,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"48227b0e_c89e6ffe","line":151,"range":{"start_line":135,"start_character":0,"end_line":151,"end_character":1},"in_reply_to":"e2b29ffa_d06cde3d","updated":"2022-04-17 14:14:13.000000000","message":"I reordered it to have the same order as `tcl/target/stm32f4x.cfg`. I moved the reordering to a separate commit.","commit_id":"76c540f1e58b95fec727144154d34ac965fd34b2"}]}