)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"114314530f376ec19173205dac5a8c4b232a3166","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1beeaad3_e51ed53d","updated":"2022-04-30 06:53:21.000000000","message":"Adding relevant reviewers","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"change_message_id":"316fa244b7159107f459d400b87630f5cc33ac2a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"b78e595b_ac5b012c","updated":"2022-05-12 17:35:01.000000000","message":"I\u0027ve no objections to this patch, but also don\u0027t really know enough to properly review it.","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d2f03617f88b92f99540741a4ee2f10b793972fb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"0b8bec5d_7c1fe4b2","updated":"2022-05-01 14:31:56.000000000","message":"Tom, thanks for the patch!","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b1a597803a7cfd5cb93e3387269686f49342a4ca","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"0a089d88_0019d554","updated":"2023-11-17 06:22:38.000000000","message":"I missed the last update from Marc. Let\u0027s merge...","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f900d519c0ea37693048d04cfdad38595a68ac82","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"2df5fa66_c06e7c50","updated":"2023-03-31 06:14:24.000000000","message":"Looks like Tom stopped communicating with us.\n\nMarc, do you have any comments?","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"70fcfcabbddb5e8ee0122f77da6d10793f45e8ca","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"544830e0_0928e679","updated":"2023-04-08 20:15:03.000000000","message":"No regression found.","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0e3f852909695e166e71f8fd2963cec06ff1276a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"e716fb8d_1cbbe60a","updated":"2022-09-16 13:12:42.000000000","message":"Removed $_TARGETNAME prefixes from commands in reset-assert event.\nDuring event handler OpenOCD sets the current target to the target which emitted the event. If more than one target are linked in JTAG chain and more target configs sourced,\n$_TARGETNAME points to the last one - not what what we want in the event handler.\n\nAdded write to DM_DMCONTROL_ACKHAVERESET before \u0027halt\u0027 cmd to suppress message\n Hart 0 unexpectedly reset!\n\nTested on Sipeed Longan Nano with GD32VF103CBT6","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5c20829b25299b47f26c36493c4ff4dd7913693e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"d1bf4e0e_e49ae10b","updated":"2023-02-04 07:51:03.000000000","message":"Tom, could you review/test the updated version and give some score? Thanks","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"0791302412948da471e81ca9db2ee127668edf19","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"cc1809fe_f5f974fa","in_reply_to":"2df5fa66_c06e7c50","updated":"2023-04-02 08:39:58.000000000","message":"I would like to make a regression test with the Longan Nano.","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f3ac9c3c84affed1ceb58af81f6b34fb9007bfc2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"6a16f19e_d99c460f","in_reply_to":"cc1809fe_f5f974fa","updated":"2023-04-02 09:26:44.000000000","message":"Please do, I\u0027ll wait.","commit_id":"9f0ff9c8f01ad086b1d9f1fd4fca09c016c409ba"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"5a33bfb8e51085f97539d3a24f3eec3cb82a9ac8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"6a3404ce_1765c587","updated":"2025-10-28 03:27:41.000000000","message":"Three years later and I think I finally understand the nuances of the SRST issue and the revisions you made, Tomas. The revisions were good and I\u0027m happy with the version that got merged. It works well on my Sipeed Longan Nano, both with and without SRST enabled.\n\nSorry I stopped responding: if I remember right, I bit off way more than I could chew by trying to fix the core reset code to avoid the double SRST assertion, and life got in the way soon after. By the time you revised the CL, I\u0027d forgotten the details and didn\u0027t have the time to remember them all. Thank you for seeing it through even though I didn\u0027t!","commit_id":"7ac389cf47463cc35667659804d939015a4815e5"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"48e91206e83f7f06eb57e03ab6d340e3ec2d3ad0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"5c01fa36_1ffbdbdb","in_reply_to":"6a3404ce_1765c587","updated":"2025-10-29 14:38:55.000000000","message":"You\u0027re welcome!\n\nBTW once upon a time I tried to make the OpenOCD reset infrastructure better (and avoid the double SRST assertion amongst other things). I failed too.\nSee https://review.openocd.org/q/topic:reset\n(It hanged as a draft couple of days)","commit_id":"7ac389cf47463cc35667659804d939015a4815e5"}],"tcl/target/gd32vf103.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d2f03617f88b92f99540741a4ee2f10b793972fb","unresolved":true,"context_lines":[{"line_number":27,"context_line":"target create $_TARGETNAME riscv -chain-position $_TARGETNAME"},{"line_number":28,"context_line":""},{"line_number":29,"context_line":"proc default_mem_access {} {"},{"line_number":30,"context_line":"\triscv set_mem_access progbuf"},{"line_number":31,"context_line":"}"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"default_mem_access"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"a2e99a4c_7c44d0a3","line":30,"range":{"start_line":30,"start_character":22,"end_line":30,"end_character":29},"updated":"2022-05-01 14:31:56.000000000","message":"riscv target has all 3 access types enabled by default. Looking at \u0027riscv info\u0027 sysbus access doesn\u0027t seem to be implemented on this device. I don\u0027t know riscv in detail so I\u0027m unsure if blocked abstract access cannot break anything.","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d2f03617f88b92f99540741a4ee2f10b793972fb","unresolved":true,"context_lines":[{"line_number":52,"context_line":"#"},{"line_number":53,"context_line":"#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2"},{"line_number":54,"context_line":"#"},{"line_number":55,"context_line":"$_TARGETNAME configure -event reset-assert {"},{"line_number":56,"context_line":"\tset dmcontrol \t\t0x10"},{"line_number":57,"context_line":"\tset dmcontrol_dmactive\t[expr {1 \u003c\u003c 0}]"},{"line_number":58,"context_line":"\tset dmcontrol_haltreq\t[expr {1 \u003c\u003c 31}]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"44757ac6_c9903168","line":55,"range":{"start_line":55,"start_character":30,"end_line":55,"end_character":42},"updated":"2022-05-01 14:31:56.000000000","message":"The overridden reset control works as expected with \u0027reset_config none\u0027\nUnfortunately there is some interference in mode \u0027reset_config srst_only\u0027.\nA message\n  Hart 0 unexpectedly reset!\n\nappears in the log just after JTAG rescan. \u0027halt\u0027 command @ line 65 explicitly polls the target state and reports SRST triggered reset as unexpected. After that the target is reset for the second time.\n\nWouldn\u0027t be better to hook reset-assert-post instead and trigger the reset by undocumented DBGMCU register only if reset_config is none?\nUsing reset-assert-post keeps the riscv target assert_reset code working so no unexpected reset is reported.\nOn the other hand, \u0027reset halt\u0027 with \u0027reset_config srst_only\u0027 executes some code before execution is halted so the second reset could gain a benefit.","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"fb4626ad2ca6df55831a38509671c383aac362d5","unresolved":true,"context_lines":[{"line_number":52,"context_line":"#"},{"line_number":53,"context_line":"#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2"},{"line_number":54,"context_line":"#"},{"line_number":55,"context_line":"$_TARGETNAME configure -event reset-assert {"},{"line_number":56,"context_line":"\tset dmcontrol \t\t0x10"},{"line_number":57,"context_line":"\tset dmcontrol_dmactive\t[expr {1 \u003c\u003c 0}]"},{"line_number":58,"context_line":"\tset dmcontrol_haltreq\t[expr {1 \u003c\u003c 31}]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"d4b54e93_db709fb5","line":55,"range":{"start_line":55,"start_character":30,"end_line":55,"end_character":42},"in_reply_to":"0e35e7a9_522c86b2","updated":"2022-05-03 08:51:45.000000000","message":"\u003e My reading of the code for various architectures gave me the impression that it was up to the arch-specific `assert_reset()` hook to call `adapter_assert_reset()` if it wanted to use SRST as a reset mechanism...\n\nI admit the OpenOCD reset-related code is one big mess.\nSRST is pulsed during JTAG initialization.\nI marked some important point FYI:\n\nhttps://review.openocd.org/c/openocd/+/6957/1/src/target/startup.tcl#61\n\nJTAG specific interface initialization starts here:\n\nhttps://review.openocd.org/c/openocd/+/6957/1/src/jtag/startup.tcl#25\n\nand continues\n\nhttps://review.openocd.org/c/openocd/+/6957/1/src/jtag/tcl.c#714\n\nfinally both TRST and SRST is asserted here as required by JTAG specification\n\nhttps://review.openocd.org/c/openocd/+/6957/1/src/jtag/core.c#1627\n\nTRST is deasserted and JTAG chain is scanned.\nSRST is kept asserted only is srst_connect_assert is configured, what is IMO wrong as SRST is in target specific assert_reset() pulsed again and some devices don\u0027t like it.\nriscv target does not handle assert_reset() at all probably because the current reset framework in not suitable for multicore targets.\n\nSo I refreshed the drawback of with current reset framework I\u0027ve forgotten: the double reset is inevitable on JTAG with configured SRST\n\nThe more correct solution would pulse SRST if configured and use the undocumented DBGMCU registers only if SRST is not available. Considering SRST is not handled by riscv target, your patch looks like a good compromise.\n\nWe just need to write DM_DMCONTROL_ACKHAVERESET before \u0027halt\u0027 cmd starts polling\nto avoid bogus\n Hart 0 unexpectedly reset!","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"a157278f25e45bdedb9eb03a2b87a4bd0353366d","unresolved":true,"context_lines":[{"line_number":52,"context_line":"#"},{"line_number":53,"context_line":"#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2"},{"line_number":54,"context_line":"#"},{"line_number":55,"context_line":"$_TARGETNAME configure -event reset-assert {"},{"line_number":56,"context_line":"\tset dmcontrol \t\t0x10"},{"line_number":57,"context_line":"\tset dmcontrol_dmactive\t[expr {1 \u003c\u003c 0}]"},{"line_number":58,"context_line":"\tset dmcontrol_haltreq\t[expr {1 \u003c\u003c 31}]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"0e35e7a9_522c86b2","line":55,"range":{"start_line":55,"start_character":30,"end_line":55,"end_character":42},"in_reply_to":"44757ac6_c9903168","updated":"2022-05-03 02:03:49.000000000","message":"Thanks for catching this! I admit that I never tried this patch with SRST hooked up. That was because I didn\u0027t think SRST ever actually got asserted on RISC-V targets.\n\nMy reading of the code for various architectures gave me the impression that it was up to the arch-specific `assert_reset()` hook to call `adapter_assert_reset()` if it wanted to use SRST as a reset mechanism. I couldn\u0027t (and still can\u0027t) find such a call in `riscv-013.c`, so I assumed that we trusted in ndmreset enough fir RISC-V to not even support an external SRST line.\n\nI just tried hooking up SRST though, and sure enough it gets toggled when I have an appropriate reset config. I\u0027m still trying to trace out the code where that happens (since, as you point out, there also seems to be a sequencing issue where haltreq isn\u0027t set early enough, causing some instructions to run before the core halts). If you know exactly where it gets toggled, I\u0027d appreciate a pointer.\n\nLet me spend some time trying to make this work as a `reset-assert-post` handler. I recall that there were significant enough obstacles to that to make me introduce support for `reset-assert` in `RISC-V` just to avoid it, but unfortunately I don\u0027t remember the specifics of what they were. (I wrote this config file a while ago.) Will follow up once I\u0027ve experimented a bit.","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b1a597803a7cfd5cb93e3387269686f49342a4ca","unresolved":false,"context_lines":[{"line_number":52,"context_line":"#"},{"line_number":53,"context_line":"#   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2"},{"line_number":54,"context_line":"#"},{"line_number":55,"context_line":"$_TARGETNAME configure -event reset-assert {"},{"line_number":56,"context_line":"\tset dmcontrol \t\t0x10"},{"line_number":57,"context_line":"\tset dmcontrol_dmactive\t[expr {1 \u003c\u003c 0}]"},{"line_number":58,"context_line":"\tset dmcontrol_haltreq\t[expr {1 \u003c\u003c 31}]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"a165d60f_466817a6","line":55,"range":{"start_line":55,"start_character":30,"end_line":55,"end_character":42},"in_reply_to":"d4b54e93_db709fb5","updated":"2023-11-17 06:22:38.000000000","message":"Done","commit_id":"89eb05a0807be92b78b573356b50051cbcd5ae2d"}]}