)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"cab9bfd9f2a517541778b968b2e5181cff47d1f2","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"f4944c58_7f6ce641","updated":"2025-12-11 16:36:23.000000000","message":"Tested on actual hardware, found no regression.","commit_id":"0eb0e7e463da62687fee621fef6b785e549fde63"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0706f46d2a9b07b569de7c92d4053eb33171bd73","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"6372d015_9dbee7be","in_reply_to":"f4944c58_7f6ce641","updated":"2025-12-12 17:42:17.000000000","message":"Ack","commit_id":"0eb0e7e463da62687fee621fef6b785e549fde63"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6d85944c72024f9874a310c5a541aab20400834f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"0008a7db_d87dbfc2","updated":"2025-12-11 20:48:33.000000000","message":"Thanks!","commit_id":"eed1f454e230e3ca954136ce0a8599d5ee316d7c"}],"tcl/target/gd32vf103.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7883c5376cd6ce4c01bf6156aeb27faf330f2528","unresolved":true,"context_lines":[{"line_number":21,"context_line":"   set _WORKAREASIZE 0x1800"},{"line_number":22,"context_line":"}"},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"reset_config srst_nogate"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"165f16eb_b2d91383","line":24,"range":{"start_line":24,"start_character":0,"end_line":24,"end_character":24},"updated":"2022-05-01 14:48:41.000000000","message":"Not sure about nogate.\nIf you keep reset button pressed and start OpenOCD, the cpu tap looks working\nbut bs tap does not. srst_gates_jtag seems me the safer side then.","commit_id":"78d6f0e323cbcac7eb98e76ca27d1a4b39fab48f"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"dbf449197f2aca172a648a8d426457e345180c6f","unresolved":false,"context_lines":[{"line_number":21,"context_line":"   set _WORKAREASIZE 0x1800"},{"line_number":22,"context_line":"}"},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"reset_config srst_nogate"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"cf7e072c_c9bd128a","line":24,"range":{"start_line":24,"start_character":0,"end_line":24,"end_character":24},"in_reply_to":"165f16eb_b2d91383","updated":"2025-10-28 10:49:24.000000000","message":"Done","commit_id":"78d6f0e323cbcac7eb98e76ca27d1a4b39fab48f"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"3efc87e3a681c87be99806cd176e6ca3d2b748cf","unresolved":false,"context_lines":[{"line_number":21,"context_line":"   set _WORKAREASIZE 0x1800"},{"line_number":22,"context_line":"}"},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"reset_config srst_nogate"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"36ac5861_2d6abe09","line":24,"range":{"start_line":24,"start_character":0,"end_line":24,"end_character":24},"in_reply_to":"165f16eb_b2d91383","updated":"2025-10-28 14:24:02.000000000","message":"You\u0027re right. I didn\u0027t think to check bs, since I don\u0027t really know how to use it with OpenOCD. I will remove this line.","commit_id":"78d6f0e323cbcac7eb98e76ca27d1a4b39fab48f"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"dbf449197f2aca172a648a8d426457e345180c6f","unresolved":true,"context_lines":[{"line_number":23,"context_line":"   set _WORKAREASIZE 0x1800"},{"line_number":24,"context_line":"}"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."},{"line_number":28,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d"},{"line_number":29,"context_line":"jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3"},{"line_number":30,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ba1c219d_5ee51760","line":27,"range":{"start_line":26,"start_character":58,"end_line":27,"end_character":56},"updated":"2025-10-28 10:49:24.000000000","message":"Please don\u0027t describe as it were based on testing of one device.\nBetter suggest that an old GD32VF103 revision could use the other id and ask\nuser to report if he encounters the case. Or ask the vendor for a clarification.\n\nBTW I also googled `riscv.cpu tap/device found: 0x1e200a6d` and there is only few hits of found, in the majority of pages the id is only expected. It looks that vast majority of GD32VF103 has 0x1000563d, so I wouldn\u0027t recommend adding 0x1e200a6d as the second id until someone reports.","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"3efc87e3a681c87be99806cd176e6ca3d2b748cf","unresolved":false,"context_lines":[{"line_number":23,"context_line":"   set _WORKAREASIZE 0x1800"},{"line_number":24,"context_line":"}"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."},{"line_number":28,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d"},{"line_number":29,"context_line":"jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3"},{"line_number":30,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"ed404435_ae6a6a37","line":27,"range":{"start_line":26,"start_character":58,"end_line":27,"end_character":56},"in_reply_to":"ba1c219d_5ee51760","updated":"2025-10-28 14:24:02.000000000","message":"Done","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"dbf449197f2aca172a648a8d426457e345180c6f","unresolved":false,"context_lines":[{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."},{"line_number":28,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d"},{"line_number":29,"context_line":"jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":32,"context_line":"target create $_TARGETNAME riscv -chain-position $_TARGETNAME"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"1dd20b26_5d2cbea3","line":29,"updated":"2025-10-28 10:49:24.000000000","message":"Although bs tap is not functional under reset the explicit definition of bs tap helps to correctly communicate with cpu tap under reset. Unfortunately riscv target code cannot cope correctly with unavailable hart during the examination.\nProbably not worth to waste more time on it but looks like we are not far away from working start under reset. Note it was tested with some patches of riscv code for rp2350 support, mainly https://github.com/tom-van/openocd-rp2350-riscv/commit/833de9ec5f1d7f2d346f23a127e6530a22460b1b\n```\nopenocd -f your_adapter -f target/gd32vf103.cfg -c \"reset_config srst_only srst_nogate connect_assert_srst\"\n...\nInfo : JTAG tap: gd32vf103.cpu tap/device found: 0x1000563d (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)\nInfo : JTAG tap: gd32vf103.bs tap/device found: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nWarn : JTAG tap: gd32vf103.bs       UNEXPECTED: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nError: JTAG tap: gd32vf103.bs  expected 1 of 1: 0x790007a3 (mfg: 0x3d1 (GigaDevice Semiconductor (Beijing)), part: 0x9000, ver: 0x7)\nError: Trying to use configured scan chain anyway...\nWarn : Bypassing JTAG setup events due to errors\nInfo : [gd32vf103.cpu] datacount\u003d4 progbufsize\u003d2\nInfo : [gd32vf103.cpu] Hart unexpectedly reset!\nInfo : [gd32vf103.cpu] unavailable.\nError: [gd32vf103.cpu] Examination failed\nWarn : target gd32vf103.cpu examination failed\n...\n```\nSo far looks good - but issuing `reset halt` does not release SRST and fails to examine:\n```\nInfo : JTAG tap: gd32vf103.cpu tap/device found: 0x1000563d (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)\nInfo : JTAG tap: gd32vf103.bs tap/device found: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nWarn : JTAG tap: gd32vf103.bs       UNEXPECTED: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nError: JTAG tap: gd32vf103.bs  expected 1 of 1: 0x790007a3 (mfg: 0x3d1 (GigaDevice Semiconductor (Beijing)), part: 0x9000, ver: 0x7)\nError: Trying to use configured scan chain anyway...\nWarn : Bypassing JTAG setup events due to errors\nInfo : [gd32vf103.cpu] datacount\u003d4 progbufsize\u003d2\nInfo : [gd32vf103.cpu] Hart unexpectedly reset!\nInfo : [gd32vf103.cpu] unavailable.\nError: Target not examined yet\nError: [gd32vf103.cpu] Execution of event reset-assert failed:\n/home/vanekt/o/tcl/target/gd32vf103.cfg:77: Error:\nTraceback (most recent call last):\n  File \"embedded:startup.tcl\", line 1454, in ocd_process_reset\n    ocd_process_reset_inner halt\n  File \"/home/vanekt/o/tcl/target/gd32vf103.cfg\", line 77, in ocd_process_reset_inner\n    halt\nInfo : [gd32vf103.cpu] datacount\u003d4 progbufsize\u003d2\nInfo : [gd32vf103.cpu] Hart unexpectedly reset!\nInfo : [gd32vf103.cpu] unavailable.\nTARGET: gd32vf103.cpu - Not examined\n```\nand neither works with the native riscv reset `gd32vf103.cpu configure -event reset-assert \"\"`\n\n```\nInfo : JTAG tap: gd32vf103.cpu tap/device found: 0x1000563d (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)\nInfo : JTAG tap: gd32vf103.bs tap/device found: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nWarn : JTAG tap: gd32vf103.bs       UNEXPECTED: 0xffffffff (mfg: 0x7ff (\u003cinvalid\u003e), part: 0xffff, ver: 0xf)\nError: JTAG tap: gd32vf103.bs  expected 1 of 1: 0x790007a3 (mfg: 0x3d1 (GigaDevice Semiconductor (Beijing)), part: 0x9000, ver: 0x7)\nError: Trying to use configured scan chain anyway...\nWarn : Bypassing JTAG setup events due to errors\nInfo : [gd32vf103.cpu] datacount\u003d4 progbufsize\u003d2\nInfo : [gd32vf103.cpu] Hart unexpectedly reset!\nInfo : [gd32vf103.cpu] unavailable.\nInfo : [gd32vf103.cpu] datacount\u003d4 progbufsize\u003d2\nInfo : [gd32vf103.cpu] Hart unexpectedly reset!\nInfo : [gd32vf103.cpu] unavailable.\nTARGET: gd32vf103.cpu - Not examined\n```","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"3efc87e3a681c87be99806cd176e6ca3d2b748cf","unresolved":false,"context_lines":[{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."},{"line_number":28,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d"},{"line_number":29,"context_line":"jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":32,"context_line":"target create $_TARGETNAME riscv -chain-position $_TARGETNAME"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"aa657be6_99cd236c","line":29,"in_reply_to":"1dd20b26_5d2cbea3","updated":"2025-10-28 14:24:02.000000000","message":"Should I leave out the bs tap, then, or is this an issue regardless? I don\u0027t particularly need it if it causes issues.","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"055701fc3f3c3848134e1973f3d109641643fe50","unresolved":false,"context_lines":[{"line_number":26,"context_line":"# The vendor\u0027s configuration expects an ID of 0x1e200a6d, but this one is what"},{"line_number":27,"context_line":"# I have on my board (Sipeed Longan Nano, GD32VF103CBT6)."},{"line_number":28,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d"},{"line_number":29,"context_line":"jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":32,"context_line":"target create $_TARGETNAME riscv -chain-position $_TARGETNAME"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"09b76fc4_5e9fc339","line":29,"in_reply_to":"aa657be6_99cd236c","updated":"2025-10-29 14:40:29.000000000","message":"No, keep it. Surprisingly it works better under reset.","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"dbf449197f2aca172a648a8d426457e345180c6f","unresolved":true,"context_lines":[{"line_number":34,"context_line":"# Disable virtual address translation since we don\u0027t have an MMU. Nothing will"},{"line_number":35,"context_line":"# break without this line, but OpenOCD will do a few unnecessary register reads"},{"line_number":36,"context_line":"# to figure it out on its own."},{"line_number":37,"context_line":"$_TARGETNAME riscv set_enable_virt2phys off"},{"line_number":38,"context_line":""},{"line_number":39,"context_line":"proc default_mem_access {} {"},{"line_number":40,"context_line":"\triscv set_mem_access progbuf"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"5b24c52f_7909bfcd","line":37,"range":{"start_line":37,"start_character":19,"end_line":37,"end_character":39},"updated":"2025-10-28 10:49:24.000000000","message":"Let\u0027s delay the patch after merging the riscv-sync series and use the new wording of the command `riscv virt2phys_mode`","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"3efc87e3a681c87be99806cd176e6ca3d2b748cf","unresolved":false,"context_lines":[{"line_number":34,"context_line":"# Disable virtual address translation since we don\u0027t have an MMU. Nothing will"},{"line_number":35,"context_line":"# break without this line, but OpenOCD will do a few unnecessary register reads"},{"line_number":36,"context_line":"# to figure it out on its own."},{"line_number":37,"context_line":"$_TARGETNAME riscv set_enable_virt2phys off"},{"line_number":38,"context_line":""},{"line_number":39,"context_line":"proc default_mem_access {} {"},{"line_number":40,"context_line":"\triscv set_mem_access progbuf"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"df75096b_b00b6f44","line":37,"range":{"start_line":37,"start_character":19,"end_line":37,"end_character":39},"in_reply_to":"5b24c52f_7909bfcd","updated":"2025-10-28 14:24:02.000000000","message":"Ack","commit_id":"48b609ec7e040b27715b1f8c9427c52063cc6f0e"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"135da06a927251cd5db7c1dc4221d514b7723811","unresolved":true,"context_lines":[{"line_number":35,"context_line":"# Disable virtual address translation since we don\u0027t have an MMU. Nothing will"},{"line_number":36,"context_line":"# break without this line, but OpenOCD will do a few unnecessary register reads"},{"line_number":37,"context_line":"# to figure it out on its own."},{"line_number":38,"context_line":"$_TARGETNAME riscv set_enable_virt2phys off"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"proc default_mem_access {} {"},{"line_number":41,"context_line":"\triscv set_mem_access progbuf"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"dcfd8476_df709d70","line":38,"range":{"start_line":38,"start_character":19,"end_line":38,"end_character":39},"updated":"2025-12-05 20:50:17.000000000","message":"Please adjust to `virt2phys_mode` for updated RISC-V target","commit_id":"0eb0e7e463da62687fee621fef6b785e549fde63"},{"author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"change_message_id":"62965800810feac4f064eeb956411f8b2195c919","unresolved":false,"context_lines":[{"line_number":35,"context_line":"# Disable virtual address translation since we don\u0027t have an MMU. Nothing will"},{"line_number":36,"context_line":"# break without this line, but OpenOCD will do a few unnecessary register reads"},{"line_number":37,"context_line":"# to figure it out on its own."},{"line_number":38,"context_line":"$_TARGETNAME riscv set_enable_virt2phys off"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"proc default_mem_access {} {"},{"line_number":41,"context_line":"\triscv set_mem_access progbuf"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"9fd9e8eb_7f9c17f8","line":38,"range":{"start_line":38,"start_character":19,"end_line":38,"end_character":39},"in_reply_to":"dcfd8476_df709d70","updated":"2025-12-11 17:04:15.000000000","message":"Done","commit_id":"0eb0e7e463da62687fee621fef6b785e549fde63"}]}