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It\u0027s\ntranslating IR/DR and JTAG traversal commands to the two-wire clocking\nand signaling.\n\nSee:\n- https://github.com/riscv-collab/riscv-openocd/pull/320\n- https://github.com/riscv-collab/riscv-openocd/pull/736\n\nSigned-off-by: Greg Savin \u003cgreg.savin@sifive.com\u003e\nSigned-off-by: mrv96 \u003cmrv96@users.noreply.github.com\u003e\nSigned-off-by: Tim Newsome \u003ctim@sifive.com\u003e\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nChange-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874\nReviewed-on: https://review.openocd.org/c/openocd/+/6981\nTested-by: jenkins\n"}},"115d076b81f81e7a7f5c6d59e8e2f63e2f9634ab":{"kind":"TRIVIAL_REBASE","_number":4,"created":"2025-10-21 19:29:38.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/81/6981/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/81/6981/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/4 \u0026\u0026 git checkout -b change-6981 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/81/6981/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"f98eeeedbb9fd62d292266203024c7acad16ce99","subject":"target/riscv: fix get mode filed for vsatp and hgatp"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-07-26 10:17:46.000000000","tz":120},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2025-10-21 19:27:35.000000000","tz":120},"subject":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters","message":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters\n\ncJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration\noption for some SiFive hardware. An FTDI-based adapter that can be\nconfigured to drive the bidirectional pin TMSC is assumed for this\ntopology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD\nadapter, connected to a SiFive cJTAG-enabled target board is the only\nknown concrete topology, currently. But in theory, other FTDI based\ndevices that can drive a two-wire bidirectional signaling pattern could\nbe made to work in this scheme in the future.\n\nThese code changes are offered as a way to drive that topology. It\u0027s\ntranslating IR/DR and JTAG traversal commands to the two-wire clocking\nand signaling.\n\nSee:\n- https://github.com/riscv-collab/riscv-openocd/pull/320\n- https://github.com/riscv-collab/riscv-openocd/pull/736\n\nSigned-off-by: Greg Savin \u003cgreg.savin@sifive.com\u003e\nSigned-off-by: mrv96 \u003cmrv96@users.noreply.github.com\u003e\nSigned-off-by: Tim Newsome \u003ctim@sifive.com\u003e\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nChange-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874\n"}},"51213ad19c0601b899d42d3e384e40c9ecab9426":{"kind":"TRIVIAL_REBASE","_number":5,"created":"2025-10-21 19:41:27.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/81/6981/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/81/6981/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/5 \u0026\u0026 git checkout -b change-6981 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/81/6981/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"f598e184ab6ac047abec5991add42a7267ca614d","subject":"target/riscv: fix get mode filed for vsatp and hgatp"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-07-26 10:17:46.000000000","tz":120},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2025-10-21 19:40:52.000000000","tz":120},"subject":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters","message":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters\n\ncJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration\noption for some SiFive hardware. An FTDI-based adapter that can be\nconfigured to drive the bidirectional pin TMSC is assumed for this\ntopology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD\nadapter, connected to a SiFive cJTAG-enabled target board is the only\nknown concrete topology, currently. But in theory, other FTDI based\ndevices that can drive a two-wire bidirectional signaling pattern could\nbe made to work in this scheme in the future.\n\nThese code changes are offered as a way to drive that topology. It\u0027s\ntranslating IR/DR and JTAG traversal commands to the two-wire clocking\nand signaling.\n\nSee:\n- https://github.com/riscv-collab/riscv-openocd/pull/320\n- https://github.com/riscv-collab/riscv-openocd/pull/736\n\nSigned-off-by: Greg Savin \u003cgreg.savin@sifive.com\u003e\nSigned-off-by: mrv96 \u003cmrv96@users.noreply.github.com\u003e\nSigned-off-by: Tim Newsome \u003ctim@sifive.com\u003e\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nChange-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874\n"}},"ad3087c30ce06324c1900a3e53233a05db526f2f":{"kind":"REWORK","_number":2,"created":"2025-07-26 10:56:06.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/81/6981/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/81/6981/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/2 \u0026\u0026 git checkout -b change-6981 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/81/6981/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6872f7e406ad74f366f55947d23becd5a5faca15","subject":"adapter/xds110: Hide \u0027(dis)connected\u0027 message"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-07-26 10:17:46.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-07-26 10:54:51.000000000","tz":120},"subject":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters","message":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters\n\ncJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration\noption for some SiFive hardware. An FTDI-based adapter that can be\nconfigured to drive the bidirectional pin TMSC is assumed for this\ntopology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD\nadapter, connected to a SiFive cJTAG-enabled target board is the only\nknown concrete topology, currently. But in theory, other FTDI based\ndevices that can drive a two-wire bidirectional signaling pattern could\nbe made to work in this scheme in the future.\n\nThese code changes are offered as a way to drive that topology. It\u0027s\ntranslating IR/DR and JTAG traversal commands to the two-wire clocking\nand signaling.\n\nSee:\n- https://github.com/riscv-collab/riscv-openocd/pull/320\n- https://github.com/riscv-collab/riscv-openocd/pull/736\n\nSigned-off-by: Greg Savin \u003cgreg.savin@sifive.com\u003e\nSigned-off-by: mrv96 \u003cmrv96@users.noreply.github.com\u003e\nSigned-off-by: Tim Newsome \u003ctim@sifive.com\u003e\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nChange-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874\n"}},"d6c8ef0a27c25f41dfa199e8ec9ad589e3e77ac8":{"kind":"REWORK","_number":3,"created":"2025-10-11 16:47:57.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/81/6981/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/81/6981/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/3 \u0026\u0026 git checkout -b change-6981 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/81/6981/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4882e7b91c5ed47ef57aace76c5bf1f9db9da392","subject":"target/riscv: fix get mode filed for vsatp and hgatp"}],"author":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-07-26 10:17:46.000000000","tz":120},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2025-10-11 16:45:04.000000000","tz":120},"subject":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters","message":"Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters\n\ncJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration\noption for some SiFive hardware. An FTDI-based adapter that can be\nconfigured to drive the bidirectional pin TMSC is assumed for this\ntopology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD\nadapter, connected to a SiFive cJTAG-enabled target board is the only\nknown concrete topology, currently. But in theory, other FTDI based\ndevices that can drive a two-wire bidirectional signaling pattern could\nbe made to work in this scheme in the future.\n\nThese code changes are offered as a way to drive that topology. It\u0027s\ntranslating IR/DR and JTAG traversal commands to the two-wire clocking\nand signaling.\n\nSee:\n- https://github.com/riscv-collab/riscv-openocd/pull/320\n- https://github.com/riscv-collab/riscv-openocd/pull/736\n\nSigned-off-by: Greg Savin \u003cgreg.savin@sifive.com\u003e\nSigned-off-by: mrv96 \u003cmrv96@users.noreply.github.com\u003e\nSigned-off-by: Tim Newsome \u003ctim@sifive.com\u003e\nSigned-off-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nChange-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874\n"}},"808d8d56139e343537d64771c1d7fe175018420f":{"kind":"REWORK","_number":1,"created":"2022-05-17 21:10:47.000000000","uploader":{"_account_id":1001242,"name":"Tim Newsome","email":"tim@sifive.com","username":"timsifive"},"ref":"refs/changes/81/6981/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/81/6981/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/1 \u0026\u0026 git checkout -b change-6981 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/81/6981/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/81/6981/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"830d70bfc66ada2a68c73283b9e4fa4770d408ee","subject":"tcl/interface/ftdi: Add config for Tigard board"}],"author":{"name":"Tim Newsome","email":"tim@sifive.com","date":"2022-05-16 21:02:30.000000000","tz":-420},"committer":{"name":"Tim Newsome","email":"tim@sifive.com","date":"2022-05-17 20:41:31.000000000","tz":-420},"subject":"Support two-wire cJTAG OSCAN1 using FTDI adapters","message":"Support two-wire cJTAG OSCAN1 using FTDI adapters\n\ncJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration\noption for some SiFive hardware. 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