)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"be5acb2b02a3b1f4a3efff4d5275ce159081943a","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2022-09-29 13:04:17 -0600"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/adiv5: add MEM-AP mdd and mwd support"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Change-Id: Icb61639711d55b5642f20e2ef14e39e6a9c98937"},{"line_number":10,"context_line":"Signed-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":4,"id":"fc4df6b1_9beea0e0","line":7,"range":{"start_line":7,"start_character":25,"end_line":7,"end_character":36},"updated":"2022-09-30 10:04:27.000000000","message":"64-bit read/write ?","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"4554658fa2b3559b24258747cd1f885c61182832","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2022-09-29 13:04:17 -0600"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/adiv5: add MEM-AP mdd and mwd support"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Change-Id: Icb61639711d55b5642f20e2ef14e39e6a9c98937"},{"line_number":10,"context_line":"Signed-off-by: Daniel Goehring \u003cdgoehrin@os.amperecomputing.com\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":4,"id":"092ceb08_28742373","line":7,"range":{"start_line":7,"start_character":25,"end_line":7,"end_character":36},"in_reply_to":"fc4df6b1_9beea0e0","updated":"2022-09-30 22:24:09.000000000","message":"Done","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"16e855e9_448d517d","updated":"2022-09-29 18:49:56.000000000","message":"See updated patch-set. If I missed something or if you see any issues with the update, let me know.","commit_id":"3b9954e99832b2ba786d306f8a658d48301ebceb"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a62bc284f07945e715394de769d64b8a2b4f8e1a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"8b60f5ef_c6a59e7e","updated":"2023-04-03 07:01:26.000000000","message":"Daniel,\nI like the verification of CSW.Size before memory access in your patch set 5.\nUnfortunately missing test for packing support breaks Cortex-M0 and M0+ operation\ncontrary to ADI spec.\n\nPeter,\nthe simplification of byte lane conversion you proposed seems me worth to implement.\n\nDaniel, Peter,\nI tried to go a step further and integrated the size and packing tests to CSW setting,\nso the only CSW read-back takes place to verify a transfer mode.\nCould you please test\n7576: target/adiv5: probe MEM-AP supported transfer sizes including large data | https://review.openocd.org/c/openocd/+/7576\n(and eventually the others in the dependency chain) and give me some feedback?\n\n","commit_id":"d18b30d2eb0726837f266dce6bc1ca368053da83"}],"src/target/arm_adi_v5.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"29d3fbec3036e12867c6124908cfed0c56589eee","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"af989c8e_2cacfd0c","line":167,"updated":"2022-09-15 06:41:43.000000000","message":"64 is not handled?","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9aa25e706533824cfede2ad167ce078730d80715","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"a9b04ede_15e64ca4","line":167,"in_reply_to":"1beba0d7_bb9f4adf","updated":"2022-09-22 08:55:51.000000000","message":"Daniel,\nwe should be careful because some parts of ADI spec are not implemented correctly or suffers from silicon errata. I tested STM32H7A3 (32-bit Cortex M, DPv2, Large Data Ext not supported). CSW.Size write 3 -\u003e reads 3. write 4 -\u003e reads 0. Just two low bits are R/W, bit 2 is clearly RAZ/WI. And no indication that size 3 is unsupported. Actually 64-bit read apparently works (internally uses two 32-bit consecutive reads, it can be observed from TAR changes), write doesn\u0027t work, writes just zeroes.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"c5c5fa40_85f2fee6","line":167,"in_reply_to":"73bacd4b_1838c19d","updated":"2022-09-29 18:49:56.000000000","message":"Requested updates made and tested on an Ampere Altra Max and AmpereOne server systems. Let me know if you see any issues.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"250df680c9eac316a7dc9479c1f4ea61c88d41ce","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"73bacd4b_1838c19d","line":167,"in_reply_to":"76f9f3f0_720a0bc0","updated":"2022-09-28 19:26:53.000000000","message":"Tomas and Antonio, thanks for the feedback. What you mentioned makes sense and I\u0027ll make the suggested updates. While the documentation is confusing, my interpretation is that if LDE is not supported, after the CSW.Size write occurs, reading the field returns the value corresponding to a supported size. Since Byte/Halfword accesses are documented as implementation defined, without the CSW.Size write/read mechanism I\u0027m not sure how else the supported 8- and 16-bit data types would be probed.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f22041944c6d1ab2a32e5e12a8d48ddfc228b41a","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"1beba0d7_bb9f4adf","line":167,"in_reply_to":"82c73fcf_bf55d57d","updated":"2022-09-22 06:25:45.000000000","message":"Yes, this should be tested. BTW even the support of 8-bit and 16-bit transfers is implementation defined although I\u0027m not aware of any device without it.\nmem_ap_init() similarly tests if packed transfers are supported.\nThe CSW readback shouldn\u0027t take place on every mem_ap_setup_transfer() to avoid impact to r/w performance. We should also avoid testing 64-bit support at init time until we want to use it. So test the CSW on the first use of 64-bit access?","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1d09c21b36e5c5cbca8262e5d27f6a2db7121dd9","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ccac463b_f6813cb7","line":167,"in_reply_to":"a9b04ede_15e64ca4","updated":"2022-09-22 16:51:42.000000000","message":"The spec IHI0031C, the first that introduces DPv2 and Large Data Ext, say:\n\n\u003e Size, bits[2:0] Size of access. This field indicates the size of access to\n\u003e perform. It is IMPLEMENTATION DEFINED whether a MEM-AP supports access sizes\n\u003e other than 32-bits:\n\u003e * If it does then the Size field is RW, and the field indicates the size of\n\u003e   the access to perform.\n\nNote, it say nothing of what you read back, only say it is RW!\nContinuing ...\n\n\u003e ...\n\u003e * If it does not then this field is RO and it reads as 0b010 to indicate\n\u003e   that only 32-bit accesses are supported.\n\u003e If a MEM-AP implementation includes the Large Data Extension then:\n\u003e * This field must be implemented as RW.\n\u003e * If a reserved value, or a value corresponding to an unsupported access size,\n\u003e   is written to this field, then:\n\u003e   - A read of the field returns the value corresponding to a supported size.\n\u003e   - MEM-AP behavior corresponds to the value returned by a read of this field.\n\nSo only if Large Data Ext is supported we can write 3 (64 bit) or more and read back if the mode is supported.\nWithout Large Data Ext we can only write 0, 1 or 2, and in case only 2 is supported then the field is RO and we always read 2; we are not supposed to write 3.\n\nThis check should be moved in mem_ap_init(), as Tomas suggests, and save somewhere the result.\n\n uint32_t csw[8];\n max_mode \u003d (ap-\u003ecfg_reg \u0026 MEM_AP_REG_CFG_LD) ? 7 : 3;\n for (i \u003d 0; i \u003c\u003d max_mode; i++) {\n   retval \u003d dap_queue_ap_write(ap, MEM_AP_REG_CSW(dap), i);\n   if (retval) ...\n   retval \u003d dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), \u0026csw[i]);\n   if (retval) ...\n }\n dap_run(dap);\n ap-\u003esupported_size \u003d 0;\n for (i \u003d 0; i \u003c\u003d max_mode; i++)\n   if ((csw[i] \u0026 CSW_SIZE_MASK) \u003d\u003d i)\n     ap-\u003esupported_size |\u003d BIT(i);","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"275831d1baa98e860cb1adb463b52ec2880bf566","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"baa06905_4937b663","line":167,"in_reply_to":"af989c8e_2cacfd0c","updated":"2022-09-22 00:33:44.000000000","message":"Fixed. Although there is a problem I want to bring up with proposed solution.\n\nThe Arm Debug Interface Architecture Specification ADIv6.0 (IHI0074D), table C2-10 \"Size field values\", mentions the following for the CSW size field...\n\n\"If a reserved value, or a value corresponding to an unsupported access size, is written to this field, reading the field returns the value corresponding to a supported size, and the MEM-AP behaves according to the return value.\"\n\nMy concern is that if a user executes a mdd/mwd command that generates a 64-bit data request, but the Access Port doesn\u0027t support the doubleword (64-bit) option since it\u0027s implementation defined, the AP could default to using a word (32-bit) setting instead. If this happens, the cached \"ap-\u003ecsw_value\" would be out-of-sync with the AP\u0027s hardware CSW size.\n\nIf you think this is a valid concern, the proposed fix would be to modify \"mem_ap_setup_csw()\" to read the CSW value back after it is written to the hardware to verify the CSW setting. If you think that is worth doing let me know and I\u0027ll add the check.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a9b251797fddebafbb46026d8b737cc52c96dc41","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"82c73fcf_bf55d57d","line":167,"in_reply_to":"baa06905_4937b663","updated":"2022-09-22 00:42:51.000000000","message":"Somehow my comment didn\u0027t save correctly... I also mentioned that while it would be a good idea to read the CSW setting back from the hardware, there may be higher level caller functions that could fail if the CSW data size changed from 64- to 32-bit. I need to review this more.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"09ebcc57e964d37425836b3e67be186a062b2e39","unresolved":true,"context_lines":[{"line_number":164,"context_line":"\t\t\treturn 2;"},{"line_number":165,"context_line":"\t\tcase CSW_32BIT:"},{"line_number":166,"context_line":"\t\t\treturn 4;"},{"line_number":167,"context_line":"\t\tdefault:"},{"line_number":168,"context_line":"\t\t\treturn 0;"},{"line_number":169,"context_line":"\t\t}"},{"line_number":170,"context_line":"\tcase CSW_ADDRINC_PACKED:"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"76f9f3f0_720a0bc0","line":167,"in_reply_to":"ccac463b_f6813cb7","updated":"2022-09-22 20:21:07.000000000","message":"\u003e The spec IHI0031C...\n\n\u003e \u003e If a MEM-AP implementation includes the Large Data Extension then:\n\u003e \u003e * This field must be implemented as RW.\n\u003e \u003e * If a reserved value, or a value corresponding to an unsupported access size,\n\u003e \u003e   is written to this field, then:\n\u003e \u003e   - A read of the field returns the value corresponding to a supported size.\n\u003e \u003e   - MEM-AP behavior corresponds to the value returned by a read of this field.\n\nThis corresponds to what I observed on Cortex-M7.\n\nBut IHI0031F reads\n\n\u003e b. Supported by the MEM-AP Large Data Extension, see MEM-AP Large Data\n\u003e Extension on page C2-165. The following usage constraints apply:\n\u003e If the extension is not implemented, this value is reserved.\n\u003e If a reserved value, or a value corresponding to an unsupported access size, is written\n\u003e to this field, reading the field returns the value corresponding to a supported size, and\n\u003e the MEM-AP behaves according to the return value.\n\nI understood that CSW.Size \u003d 3 is reserved because LD is not implemented,\nand the part \"If a reserved value...\" would apply. Hmmm, great doc...\n\n\u003e This check should be moved in mem_ap_init(),\n\nOr just read CFG.LD in mem_ap_init() and if LD is enabled most probably 64-bit access is supported. It would be enough until 128-bit access is implemented.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"29d3fbec3036e12867c6124908cfed0c56589eee","unresolved":true,"context_lines":[{"line_number":357,"context_line":"\tif (size \u003d\u003d 8) {"},{"line_number":358,"context_line":"\t\tcsw_size \u003d CSW_64BIT;"},{"line_number":359,"context_line":"\t\taddr_xor \u003d 0;"},{"line_number":360,"context_line":"\t\tcsw_addrincr \u003d CSW_ADDRINC_OFF;"},{"line_number":361,"context_line":"\t} else if (size \u003d\u003d 4) {"},{"line_number":362,"context_line":"\t\tcsw_size \u003d CSW_32BIT;"},{"line_number":363,"context_line":"\t\taddr_xor \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"5a97caa7_efb2b7cd","line":360,"range":{"start_line":360,"start_character":2,"end_line":360,"end_character":33},"updated":"2022-09-15 06:41:43.000000000","message":"Could you explain why address increment is not supported?","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"275831d1baa98e860cb1adb463b52ec2880bf566","unresolved":false,"context_lines":[{"line_number":357,"context_line":"\tif (size \u003d\u003d 8) {"},{"line_number":358,"context_line":"\t\tcsw_size \u003d CSW_64BIT;"},{"line_number":359,"context_line":"\t\taddr_xor \u003d 0;"},{"line_number":360,"context_line":"\t\tcsw_addrincr \u003d CSW_ADDRINC_OFF;"},{"line_number":361,"context_line":"\t} else if (size \u003d\u003d 4) {"},{"line_number":362,"context_line":"\t\tcsw_size \u003d CSW_32BIT;"},{"line_number":363,"context_line":"\t\taddr_xor \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"0ae4c469_ca968cf2","line":360,"range":{"start_line":360,"start_character":2,"end_line":360,"end_character":33},"in_reply_to":"5a97caa7_efb2b7cd","updated":"2022-09-22 00:33:44.000000000","message":"Fixed.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9f1f78a99c491717e34a669308bf0659df766585","unresolved":true,"context_lines":[{"line_number":378,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":379,"context_line":""},{"line_number":380,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":381,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":382,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":383,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":384,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"356a17c5_fe7db4ac","line":381,"updated":"2022-09-15 08:07:19.000000000","message":"this forces non-packet for all 64 bit accesses.\nIs it here because there a bug in the detection of ap-\u003epacked_transfers ?\nOr because your implementation does not support addrinc?","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"275831d1baa98e860cb1adb463b52ec2880bf566","unresolved":true,"context_lines":[{"line_number":378,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":379,"context_line":""},{"line_number":380,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":381,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":382,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":383,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":384,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"6eb05d1e_96bebfa9","line":381,"in_reply_to":"356a17c5_fe7db4ac","updated":"2022-09-22 00:33:44.000000000","message":"I don\u0027t think packed transfers is supported by the ARM architecture for 64-bit accesses, but I could be misinterpreting the specification.\n\nThe Arm Debug Interface Architecture Specification ADIv6.0 (IHI0074D), section C2.2.8 Packed transfers, mentions the following...\n\n\"Use of packed transfers with CSW.Size set to a transfer size larger than word is UNPREDICTABLE.\"\n\nBecause of this, I added the \"size \u003c\u003d 4\" constraint to avoid enabling packed-transfer support for access sizes larger than a word (32 bits).","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f22041944c6d1ab2a32e5e12a8d48ddfc228b41a","unresolved":true,"context_lines":[{"line_number":378,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":379,"context_line":""},{"line_number":380,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":381,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":382,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":383,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":384,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"cd24d9c4_7fb2bae3","line":381,"in_reply_to":"6eb05d1e_96bebfa9","updated":"2022-09-22 06:25:45.000000000","message":"Please don\u0027t overuse parentheses.\n\nI have (slightly off-topic) concern why we use packed transfers for size 4, when AFAIK no packing takes place and CSW_ADDRINC_PACKED is just an alias of CSW_ADDRINC_SINGLE? We might try\n size \u003c 4\n\nin a separate patch to save some CSW handling at the end of TAR block.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"250df680c9eac316a7dc9479c1f4ea61c88d41ce","unresolved":true,"context_lines":[{"line_number":378,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":379,"context_line":""},{"line_number":380,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":381,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":382,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":383,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":384,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"d6c92b3e_4ffdbdb6","line":381,"in_reply_to":"cd24d9c4_7fb2bae3","updated":"2022-09-28 19:26:53.000000000","message":"I also wondered about packed transfers with a size of 4. Like you mention, CSW_ADDRINC_PACKED should have the same result as CSW_ADDRINC_SINGLE. I reviewed section C2.2.8 \"Packed transfers\" in the IHI0074D and don\u0027t see any advantage of using PACKED over SINGLE for single word (32-bit) data transfers.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":true,"context_lines":[{"line_number":378,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":379,"context_line":""},{"line_number":380,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":381,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":382,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":383,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":384,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"7225ca69_c79eff0d","line":381,"in_reply_to":"d6c92b3e_4ffdbdb6","updated":"2022-09-29 18:49:56.000000000","message":"Fixed parentheses issue. I\u0027ll submit a request to ARM support and inquire about PACKED vs SINGLE for word (32-bit) data type access.","commit_id":"d8de3ae0a830e88e22adae8adacd59f068d42f6b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1d09c21b36e5c5cbca8262e5d27f6a2db7121dd9","unresolved":true,"context_lines":[{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\tif (size \u003d\u003d 8) {"},{"line_number":360,"context_line":"\t\tcsw_size \u003d CSW_64BIT;"},{"line_number":361,"context_line":"\t\taddr_xor \u003d 0;"},{"line_number":362,"context_line":"\t} else if (size \u003d\u003d 4) {"},{"line_number":363,"context_line":"\t\tcsw_size \u003d CSW_32BIT;"},{"line_number":364,"context_line":"\t\taddr_xor \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"b55cade4_bdc65550","line":361,"updated":"2022-09-22 16:51:42.000000000","message":"We have no idea about the behavior of the devices that requires ti_be_32_quirks on R/W other than 4, 2, 1. Please add here (and in write below):\n if (dap-\u003eti_be_32_quirks) {\n   LOG_ERROR(\"Read 64 bits not supported with ti_be_32_quirks\");\n   return ERROR_TARGET_INVALID;\n }","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":true,"context_lines":[{"line_number":358,"context_line":""},{"line_number":359,"context_line":"\tif (size \u003d\u003d 8) {"},{"line_number":360,"context_line":"\t\tcsw_size \u003d CSW_64BIT;"},{"line_number":361,"context_line":"\t\taddr_xor \u003d 0;"},{"line_number":362,"context_line":"\t} else if (size \u003d\u003d 4) {"},{"line_number":363,"context_line":"\t\tcsw_size \u003d CSW_32BIT;"},{"line_number":364,"context_line":"\t\taddr_xor \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"58b1553a_68679f44","line":361,"in_reply_to":"b55cade4_bdc65550","updated":"2022-09-29 18:49:56.000000000","message":"Done","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f22041944c6d1ab2a32e5e12a8d48ddfc228b41a","unresolved":true,"context_lines":[{"line_number":531,"context_line":"\t/* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant"},{"line_number":532,"context_line":"\t * over-allocation if packed transfers are going to be used, but determining the real need at"},{"line_number":533,"context_line":"\t * this point would be messy. */"},{"line_number":534,"context_line":"\tuint32_t *read_buf;"},{"line_number":535,"context_line":"\tif (size \u003e 4)"},{"line_number":536,"context_line":"\t\tread_buf \u003d (uint32_t *)calloc(count, sizeof(uint64_t));"},{"line_number":537,"context_line":"\telse"},{"line_number":538,"context_line":"\t\tread_buf \u003d (uint32_t *)calloc(count, sizeof(uint32_t));"},{"line_number":539,"context_line":""},{"line_number":540,"context_line":"\t/* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */"},{"line_number":541,"context_line":"\tuint32_t *read_ptr \u003d read_buf;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"be0b582d_f26c2426","line":538,"range":{"start_line":534,"start_character":1,"end_line":538,"end_character":57},"updated":"2022-09-22 06:25:45.000000000","message":"Shorter and ready for sizes \u003e 8:\n\n uint32_t *read_buf \u003d calloc(count, MAX(sizeof(uint32_t), size));","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":true,"context_lines":[{"line_number":531,"context_line":"\t/* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant"},{"line_number":532,"context_line":"\t * over-allocation if packed transfers are going to be used, but determining the real need at"},{"line_number":533,"context_line":"\t * this point would be messy. */"},{"line_number":534,"context_line":"\tuint32_t *read_buf;"},{"line_number":535,"context_line":"\tif (size \u003e 4)"},{"line_number":536,"context_line":"\t\tread_buf \u003d (uint32_t *)calloc(count, sizeof(uint64_t));"},{"line_number":537,"context_line":"\telse"},{"line_number":538,"context_line":"\t\tread_buf \u003d (uint32_t *)calloc(count, sizeof(uint32_t));"},{"line_number":539,"context_line":""},{"line_number":540,"context_line":"\t/* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */"},{"line_number":541,"context_line":"\tuint32_t *read_ptr \u003d read_buf;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"1e288366_102d24c2","line":538,"range":{"start_line":534,"start_character":1,"end_line":538,"end_character":57},"in_reply_to":"be0b582d_f26c2426","updated":"2022-09-29 18:49:56.000000000","message":"Done","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f22041944c6d1ab2a32e5e12a8d48ddfc228b41a","unresolved":true,"context_lines":[{"line_number":551,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":552,"context_line":""},{"line_number":553,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":554,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":555,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":556,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":557,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"4cf1f130_062a882b","line":554,"range":{"start_line":554,"start_character":6,"end_line":554,"end_character":52},"updated":"2022-09-22 06:25:45.000000000","message":"Please don\u0027t overuse parentheses.\nWe might pre-evaluate the const part of the term to a bool variable and use it here and bellow on line 611","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"a8f075716e7f3ac22cfeedb2128fcf92d6808c58","unresolved":true,"context_lines":[{"line_number":551,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":552,"context_line":""},{"line_number":553,"context_line":"\t\t/* Select packed transfer if possible */"},{"line_number":554,"context_line":"\t\tif ((size \u003c\u003d 4) \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":555,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":556,"context_line":"\t\t\tthis_size \u003d 4;"},{"line_number":557,"context_line":"\t\t\tretval \u003d mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"0a68a746_5527d738","line":554,"range":{"start_line":554,"start_character":6,"end_line":554,"end_character":52},"in_reply_to":"4cf1f130_062a882b","updated":"2022-09-29 18:49:56.000000000","message":"Done","commit_id":"41baa48cc331dca69a2adf044c03e685dbea5489"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"be5acb2b02a3b1f4a3efff4d5275ce159081943a","unresolved":true,"context_lines":[{"line_number":891,"context_line":"\tuint32_t csw_list[8];"},{"line_number":892,"context_line":"\tint max_mode \u003d (ap-\u003ecfg_reg \u0026 MEM_AP_REG_CFG_LD) ? 7 : 3;"},{"line_number":893,"context_line":"\tfor (int i \u003d 0; i \u003c\u003d max_mode; i++) {"},{"line_number":894,"context_line":"\t\tretval \u003d dap_queue_ap_write(ap, MEM_AP_REG_CSW(dap), i);"},{"line_number":895,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":896,"context_line":"\t\t\treturn retval;"},{"line_number":897,"context_line":"\t\tretval \u003d dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), \u0026csw_list[i]);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"276406c2_20d8c020","line":894,"range":{"start_line":894,"start_character":11,"end_line":894,"end_character":29},"updated":"2022-09-30 10:04:27.000000000","message":"mem_ap_setup_csw() should be used instead.\nap_write does not update ap-\u003ecsw_value cache.\nAlso ap-\u003ecsw_default is omitted.","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"4554658fa2b3559b24258747cd1f885c61182832","unresolved":true,"context_lines":[{"line_number":891,"context_line":"\tuint32_t csw_list[8];"},{"line_number":892,"context_line":"\tint max_mode \u003d (ap-\u003ecfg_reg \u0026 MEM_AP_REG_CFG_LD) ? 7 : 3;"},{"line_number":893,"context_line":"\tfor (int i \u003d 0; i \u003c\u003d max_mode; i++) {"},{"line_number":894,"context_line":"\t\tretval \u003d dap_queue_ap_write(ap, MEM_AP_REG_CSW(dap), i);"},{"line_number":895,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":896,"context_line":"\t\t\treturn retval;"},{"line_number":897,"context_line":"\t\tretval \u003d dap_queue_ap_read(ap, MEM_AP_REG_CSW(dap), \u0026csw_list[i]);"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"1b547d41_80878aa4","line":894,"range":{"start_line":894,"start_character":11,"end_line":894,"end_character":29},"in_reply_to":"276406c2_20d8c020","updated":"2022-09-30 22:24:09.000000000","message":"Done","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"be5acb2b02a3b1f4a3efff4d5275ce159081943a","unresolved":true,"context_lines":[{"line_number":898,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":899,"context_line":"\t\t\treturn retval;"},{"line_number":900,"context_line":"\t}"},{"line_number":901,"context_line":"\tdap_run(dap);"},{"line_number":902,"context_line":"\tap-\u003esupported_size \u003d 0;"},{"line_number":903,"context_line":"\tfor (int i \u003d 0; i \u003c\u003d max_mode; i++)"},{"line_number":904,"context_line":"\t\tif ((csw_list[i] \u0026 CSW_SIZE_MASK) \u003d\u003d (uint32_t)i)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"c3ac306c_395279de","line":901,"range":{"start_line":901,"start_character":1,"end_line":901,"end_character":14},"updated":"2022-09-30 10:04:27.000000000","message":"Check the returned value for error.\n\nBe aware that ap_init could be time critical for some Cortex-M devices with internal flash and poor design (reset clears debug circuitry). That\u0027s why I\u0027m not happy it\u0027s getting longer and longer (ADIv6 added one read).\n\nThis test could be integrated with testing of packing availability to save one dap_run.\nAlso testing of compulsory CSW.Size \u003d\u003d 2 is IMO waste of time.\n\nI did NOT proposed to put this stuff to ap_init as Antonio thought, I just wrote that packing is tested here. IMO the best solution would be to run the test for both packing and size just in time, before the first mem r/w with size different from 32-bit. It would enable to control the core without the delay (as long as 32-bit access is used)","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"},{"author":{"_account_id":1001661,"name":"Daniel Goehring","email":"dgoehrin@os.amperecomputing.com","username":"dgoehrin"},"change_message_id":"4554658fa2b3559b24258747cd1f885c61182832","unresolved":true,"context_lines":[{"line_number":898,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":899,"context_line":"\t\t\treturn retval;"},{"line_number":900,"context_line":"\t}"},{"line_number":901,"context_line":"\tdap_run(dap);"},{"line_number":902,"context_line":"\tap-\u003esupported_size \u003d 0;"},{"line_number":903,"context_line":"\tfor (int i \u003d 0; i \u003c\u003d max_mode; i++)"},{"line_number":904,"context_line":"\t\tif ((csw_list[i] \u0026 CSW_SIZE_MASK) \u003d\u003d (uint32_t)i)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"1d142845_58ac910d","line":901,"range":{"start_line":901,"start_character":1,"end_line":901,"end_character":14},"in_reply_to":"c3ac306c_395279de","updated":"2022-09-30 22:24:09.000000000","message":"I made the following changes to reduce mem_ap_init() time.\n\n1. Made the CSW Size checking just-in-time by moving the support to the mem_ap_read() and mem_ap_write() routines. Those routines call function csw_size_verify() to perform the CSW data type size check.\n\n2. Simplified checking for packed transfer data support. From IHI0074D, C2.2.2 \"Auto-incrementing the Transfer Address Register (TAR)\"\n\n\"An implementation that supports transfers smaller than a word must support packed transfers.\"\n\nIn conclusion, if 8- and 16-bit transfers are supported, they must support packed transfers. Thus, no need to check for it which removes a dap_run() call.\n\nThe document does state the following...\n\"Packed transfers cannot be supported on a MEM-AP that only supports word transfers.\"\n\nTo simplify the determination on whether packed vs non-packed for 32-bit data transfers is supported for a particular MEM-AP, this use case is avoided by removing 32-bit data packed support which we had previously considered doing.\n\nI verified the updates on an Ampere Altra Max and AmpereOne server system.","commit_id":"08757d39fb8f626d06173ccc6986c2d1e6ce1909"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"2bdf40eef31c8913b2bae7c739d7ef2d2a3a438f","unresolved":true,"context_lines":[{"line_number":424,"context_line":"\twhile (nbytes \u003e 0) {"},{"line_number":425,"context_line":"\t\tuint32_t this_size \u003d size;"},{"line_number":426,"context_line":""},{"line_number":427,"context_line":"\t\t/* Select packed transfer if possible and size \u003c 4 */"},{"line_number":428,"context_line":"\t\tif (size \u003c 4 \u0026\u0026 addrinc \u0026\u0026 ap-\u003epacked_transfers \u0026\u0026 nbytes \u003e\u003d 4"},{"line_number":429,"context_line":"\t\t\t\t\u0026\u0026 max_tar_block_size(ap-\u003etar_autoincr_block, address) \u003e\u003d 4) {"},{"line_number":430,"context_line":"\t\t\tthis_size \u003d 4;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"704274aa_dddbe56d","line":427,"updated":"2023-01-12 21:57:13.000000000","message":"Isn\u0027t \"size \u003c 4\" implied by \"possible\"? (Same below.)","commit_id":"d18b30d2eb0726837f266dce6bc1ca368053da83"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"2bdf40eef31c8913b2bae7c739d7ef2d2a3a438f","unresolved":true,"context_lines":[{"line_number":482,"context_line":"\t\t\t}"},{"line_number":483,"context_line":"\t\t} else {"},{"line_number":484,"context_line":"\t\t\tswitch (this_size) {"},{"line_number":485,"context_line":"\t\t\tcase 8:"},{"line_number":486,"context_line":"\t\t\t\toutlow |\u003d (uint32_t)*buffer++ \u003c\u003c 8 * (drw_byte_idx++ \u0026 3);"},{"line_number":487,"context_line":"\t\t\t\toutlow |\u003d (uint32_t)*buffer++ \u003c\u003c 8 * (drw_byte_idx++ \u0026 3);"},{"line_number":488,"context_line":"\t\t\t\toutlow |\u003d (uint32_t)*buffer++ \u003c\u003c 8 * (drw_byte_idx++ \u0026 3);"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"c35f3bc9_694ceb78","line":485,"updated":"2023-01-12 21:57:13.000000000","message":"Likewise, maybe this can be removed by transforming into a loop that does the necessary number of DRW writes?","commit_id":"d18b30d2eb0726837f266dce6bc1ca368053da83"},{"author":{"_account_id":1001992,"name":"Peter Collingbourne","email":"pcc@google.com","username":"pcc"},"change_message_id":"2bdf40eef31c8913b2bae7c739d7ef2d2a3a438f","unresolved":true,"context_lines":[{"line_number":682,"context_line":"\t\t\t}"},{"line_number":683,"context_line":"\t\t} else {"},{"line_number":684,"context_line":"\t\t\tswitch (this_size) {"},{"line_number":685,"context_line":"\t\t\tcase 8:"},{"line_number":686,"context_line":"\t\t\t\t*buffer++ \u003d *read_ptr \u003e\u003e 8 * (address++ \u0026 3);"},{"line_number":687,"context_line":"\t\t\t\t*buffer++ \u003d *read_ptr \u003e\u003e 8 * (address++ \u0026 3);"},{"line_number":688,"context_line":"\t\t\t\t*buffer++ \u003d *read_ptr \u003e\u003e 8 * (address++ \u0026 3);"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"6bb52205_f9e24011","line":685,"updated":"2023-01-12 21:57:13.000000000","message":"I think this code can be removed if you clamp this_size to 4, as I did in my CL: https://review.openocd.org/c/openocd/+/7436\n\nIt should also make it easier to expand to larger bitwidths.","commit_id":"d18b30d2eb0726837f266dce6bc1ca368053da83"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a62bc284f07945e715394de769d64b8a2b4f8e1a","unresolved":true,"context_lines":[{"line_number":895,"context_line":"\tap-\u003ecsw_size_supported \u003d BIT(CSW_32BIT);"},{"line_number":896,"context_line":"\tap-\u003ecsw_size_probed \u003d BIT(CSW_32BIT);"},{"line_number":897,"context_line":""},{"line_number":898,"context_line":"\t/* Implementations that support transfers smaller than a word must"},{"line_number":899,"context_line":"\t * support packed transfers (IHI0074D)."},{"line_number":900,"context_line":"\t * Packed transfers on TI BE-32 processors do not work correctly in"},{"line_number":901,"context_line":"\t * many cases. */"},{"line_number":902,"context_line":"\tap-\u003epacked_transfers \u003d dap-\u003eti_be_32_quirks ? false : true;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"6ffb77ab_a2523e54","line":899,"range":{"start_line":898,"start_character":4,"end_line":899,"end_character":40},"updated":"2023-04-03 07:01:26.000000000","message":"Also IHI0031F states the same. Unfortunately it is NOT true at least for Cortex-M0 and M0+ as they support byte and halfword transfers but do not support packing.","commit_id":"d18b30d2eb0726837f266dce6bc1ca368053da83"}]}