)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"381b9dde11c686d50d52688252f74ce4be21fb27","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"I also added other models, the datasheets can be found at:"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":" - https://datasheet.lcsc.com/lcsc/2203210916_Zbit-Semi-ZB25VQ16ASIG_C2982491.pdf"},{"line_number":15,"context_line":" - https://datasheet.lcsc.com/lcsc/2003141132_Zbit-Semi-ZB25VQ32BSIG_C495744.pdf"},{"line_number":16,"context_line":" - https://datasheet.lcsc.com/lcsc/2003141132_Zbit-Semi-ZB25VQ64ASIG_C495745.pdf"},{"line_number":17,"context_line":" - https://datasheet.lcsc.com/lcsc/2006151421_Zbit-Semi-ZB25VQ128ASIG_C609616.pdf"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"cfe3dc01_5fb21fbe","line":14,"updated":"2023-01-26 22:29:22.000000000","message":"checkpatch complains because this line and next 3 are too long\nRewrite them as:\nLink: https://datasheet.lcsc.com/lcsc/2203210916_Zbit-Semi-ZB25VQ16ASIG_C2982491.pdf","commit_id":"d17f89f9cf7fe36b88756a0142d335b13a9a6f10"},{"author":{"_account_id":1002113,"name":"Daniel Serpell","display_name":"dmsc","email":"daniel.serpell@gmail.com","username":"dmsc"},"change_message_id":"73c9ba2adaa2878c2377aa52c0e9734505cf7c35","unresolved":false,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"I also added other models, the datasheets can be found at:"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":" - https://datasheet.lcsc.com/lcsc/2203210916_Zbit-Semi-ZB25VQ16ASIG_C2982491.pdf"},{"line_number":15,"context_line":" - https://datasheet.lcsc.com/lcsc/2003141132_Zbit-Semi-ZB25VQ32BSIG_C495744.pdf"},{"line_number":16,"context_line":" - https://datasheet.lcsc.com/lcsc/2003141132_Zbit-Semi-ZB25VQ64ASIG_C495745.pdf"},{"line_number":17,"context_line":" - https://datasheet.lcsc.com/lcsc/2006151421_Zbit-Semi-ZB25VQ128ASIG_C609616.pdf"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"a4d76ec0_31bfd286","line":14,"in_reply_to":"cfe3dc01_5fb21fbe","updated":"2023-01-27 03:07:38.000000000","message":"Thank you, did not know how to fix the checkpath output.","commit_id":"d17f89f9cf7fe36b88756a0142d335b13a9a6f10"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"4ea1ce8b8d130edf37a5402fd1e48ece07e82dde","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"458e21d9_a159bdcd","updated":"2023-01-25 08:58:34.000000000","message":"Thanks for pointing out these devices, I hadn\u0027t come across this manufacturer ...\n\nBut: VQ16 has memory type 0x60, not 0x40, in its ID. And it does not support QPI mode with qread 0xEB (it does have 0xEB read, but that\u0027s a mixed mode, instruction via 1 line, and only adress/data via 4 lines, whereas the other three allow intruction via 4 lines, too).\n\nFurthermore, VQ32, VQ64 and VQ128 share a rather nasty property with some winbond devices, i.e. they CHANGE their ID upon entering QPI mode. So there must be two entries, one with memory type 0x40 and one with 0x60 (note that for VQ16 the meaning of memory type is exactly the other way round), cf. W25Q16 ... W25Q256.\n\nFor qread 0xEB is ok except that there is an additional parameter byte MF7-0 which could cause trouble (similar to other devices where I never encountered problems with that) but 0x0B might be safer choice.","commit_id":"f862b469b2df0d0478bd7d9a7213e0bc445ca5d0"},{"author":{"_account_id":1002113,"name":"Daniel Serpell","display_name":"dmsc","email":"daniel.serpell@gmail.com","username":"dmsc"},"change_message_id":"73c9ba2adaa2878c2377aa52c0e9734505cf7c35","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"972f3b73_6482d21c","in_reply_to":"458e21d9_a159bdcd","updated":"2023-01-27 03:07:38.000000000","message":"Thank you for the review, I pushed a new version with the changes suggested.\n\nI also saw that almost all the other chips use the 0xEB command for qread. I could make a program in my rp2040 to try reading the flash using both commands to see if they are the same (this program should be in RAM).","commit_id":"f862b469b2df0d0478bd7d9a7213e0bc445ca5d0"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"d5ab434d81c7103917a16c54eff166a386ba4e5b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"4900434d_2584f1af","updated":"2023-01-28 14:52:42.000000000","message":"Hm, I don\u0027t see any changes except for the commit message???\n\nAs I said 0xEB should be okay, too, but 0x0B is slightly safer. As long as all four data lines are sensed as 0 or all as 1 during first dummy byte, there is no risk of accidentally entering \"continuous read\" aka XIP mode. Most older devices do not support this mode anyway, hence have no mode byte after 0xEB.\nApparently the ZBIT devices do have much in common with Winbond ones. What a coincidence ;-)","commit_id":"d3cec68894bee788b74e68c4cc96b32bdf80bc4e"},{"author":{"_account_id":1002113,"name":"Daniel Serpell","display_name":"dmsc","email":"daniel.serpell@gmail.com","username":"dmsc"},"change_message_id":"08ed63072f18ae4c40b35d49420c0bd93fc02ffc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7e85e7dd_3c3d2467","in_reply_to":"4900434d_2584f1af","updated":"2023-01-28 15:05:40.000000000","message":"Hi!\n\nThis is probably me struggling with the gerrit interface 😞\n\nI pushed again the full changes.\n\nThank you!","commit_id":"d3cec68894bee788b74e68c4cc96b32bdf80bc4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"161a43bb73bde165c246f4898e8e8bb4ce7b7733","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"077e88ba_99f0000b","updated":"2023-01-28 21:14:30.000000000","message":"Thanks for the patch, Daniel.\nAnd also thanks to Andreas for the review!\nI will merge it in one week, unless someone disagrees.","commit_id":"4a7f29101ef1528289e866e05431329efbe7aefe"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"9f948415758aa1477d602b21888bf13b60041dbf","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"2cb7b58f_43ac61a4","updated":"2023-01-28 16:24:14.000000000","message":"Thanks, seems perfect.","commit_id":"4a7f29101ef1528289e866e05431329efbe7aefe"},{"author":{"_account_id":1001036,"name":"Andreas Bolsch","email":"hyphen0break@gmail.com","username":"abmero"},"change_message_id":"cfc51b37a202638136784783ede0a354353502c2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"b72ac32c_6a63bb23","updated":"2023-01-28 16:24:16.000000000","message":"Thanks, seems perfect.","commit_id":"4a7f29101ef1528289e866e05431329efbe7aefe"}]}