)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"161082f0eca2fdabe7aaf1b72dd96e18fe416d10","unresolved":true,"context_lines":[{"line_number":9,"context_line":"fix the execution of soft reset fails with time out error"},{"line_number":10,"context_line":"(after 100 ms: S_HALT not raised \u003d\u003e Target not halted"},{"line_number":11,"context_line":" \u003d\u003e reset not performed)."},{"line_number":12,"context_line":"Accordingly to ARM DDI0403E.B, chapter"},{"line_number":13,"context_line":" “B3.2.6 Application Interrupt and Reset Control Register,"},{"line_number":14,"context_line":"AIRCR before setting DEMCR.VC_CORERESET to perform local system reset,"},{"line_number":15,"context_line":"we must halt the core otherwisethe behavior is unpredictable."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"a56a411c_3bdc8e06","line":12,"updated":"2023-03-03 22:51:14.000000000","message":"The commit message is not really clear. I see the note in the mentioned chapter. Would you mind rephrasing the commit message as, e.g.:\n\nAccordingly to ARM DDI0403E.B, chapter B3.2.6 \"Application\nInterrupt and Reset Control Register, AIRCR\":\n\"The effect of writing a 1 to this bit (VECTRESET) if the processor\nis not halted in Debug state is UNPREDICTABLE\".\n\nHalt the core, before setting AIRCR_VECTRESET.","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1002119,"name":"Fedi Bouzazi","email":"fedi.bouzazi@st.com","username":"FBOSTM"},"change_message_id":"76daa939a80d31d62367702a0b2435f9d87281f7","unresolved":false,"context_lines":[{"line_number":9,"context_line":"fix the execution of soft reset fails with time out error"},{"line_number":10,"context_line":"(after 100 ms: S_HALT not raised \u003d\u003e Target not halted"},{"line_number":11,"context_line":" \u003d\u003e reset not performed)."},{"line_number":12,"context_line":"Accordingly to ARM DDI0403E.B, chapter"},{"line_number":13,"context_line":" “B3.2.6 Application Interrupt and Reset Control Register,"},{"line_number":14,"context_line":"AIRCR before setting DEMCR.VC_CORERESET to perform local system reset,"},{"line_number":15,"context_line":"we must halt the core otherwisethe behavior is unpredictable."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"000ec848_b59d2272","line":12,"in_reply_to":"a56a411c_3bdc8e06","updated":"2023-03-29 09:07:57.000000000","message":"Done","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"060e6a89cb37bda616f5a7da3097ba82c5295d97","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"15a9de04_6ab9d839","updated":"2023-03-03 14:02:56.000000000","message":"LGTM","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a00d89cae0f4812dc7ac5d801cb3aeb370c42c7b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8468af53_449e4bbe","updated":"2023-03-04 16:01:03.000000000","message":"Let me elaborate a little bit more.\n\nThe purpose of the reset is to change the CPU from any state (including fails and undefined behaviour) to a well defined state. IMO imposing any prerequisites (like both ARM DDI0403C and DDI0403E.B, chapter B3.2.6 do) is a substantial design flaw, even if the reset source is limited to a debugger only. What happens if the CPU is waiting for a stalled bus? It probably cannot be gracefully halted (at least immediately), but reset should work anyway as the CPU doesn\u0027t need to finish the instruction...\n\nI wondered why the old code worked for years and nobody complained.\nI tested Cortex-M3 (STM32F103) and a few M4 (SAMG55, SAMD50, Kinetis K22, STM32F413)\nand they all respond correctly to soft_reset_halt regardless they are running or halted.\nThe only Cortex-M which refuses to respond to VECTRESET bit when running, seems to be M7\n(I tested STM32F723, H745 and SAME70, neither respond to soft_reset_halt when running)\nARMv6M M0, M0+ and ARMv8 based CPUs do not implement VECTRESET at all.\n\nWouldn\u0027t be better to implement halting CPU as Cortex-M7 only related quirk instead of blindly following the disputable part of DDI0403 spec? Or just state in OpenOCD manual that some target needs to be halted before issuing soft_reset_halt?\n\nAnother aspect:\nThe soft_reset_halt code mostly has not been maintained for long time, because as the debug message suggests\n \"soft_reset_halt is discouraged, please use \u0027reset halt\u0027 instead.\"\n\n\u0027reset\u0027 command with configurable callbacks is preferred. Unfortunately \u0027reset\u0027 command has\nno option to reset just one core of a multicore SoC. That\u0027s why soft_reset_halt has not been dropped.\n\ncortex_m_assert_reset() called from \u0027reset\u0027 command can depending on \u0027reset_config\u0027 and \u0027cortex_m reset_config\u0027 settings use VECTRESET as well and similarly does not ensure the target is halted before.\n","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"161082f0eca2fdabe7aaf1b72dd96e18fe416d10","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5ef02b05_36d2547b","updated":"2023-03-03 22:51:14.000000000","message":"Thanks for the patch. The code and the fix looks correct.\nCan you please add the reference in the comment to make everyone remembering why we have to do that?","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1002119,"name":"Fedi Bouzazi","email":"fedi.bouzazi@st.com","username":"FBOSTM"},"change_message_id":"76daa939a80d31d62367702a0b2435f9d87281f7","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"de88f914_42d3695d","in_reply_to":"8468af53_449e4bbe","updated":"2023-03-29 09:07:57.000000000","message":"Thanks Tomas for your feedback, in our case, GDB event \"gdb-flash-erase-start\", a soft reset dont perform correctly target need to halt. the problem occurs while executing a \"soft_reset_halt\" for dual core targets (M7, M4). This patch solves the issue. I don\u0027t have an idea about the old single core target (STM32F723, H745 and SAME70).","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"621b609cbc6dde7e9693305ea38ee2acc25080f7","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"9dd131c0_c6a0dfcb","updated":"2025-03-18 12:16:17.000000000","message":"@Antonio could you please let us know if there is more fixes needed ?","commit_id":"e9265b30b74ba665f965bf0ccf756401be21bc8b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"48300555507b10be973fbe51e73a7d48ac1e505a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"f68a81d9_2c2434c7","in_reply_to":"9dd131c0_c6a0dfcb","updated":"2025-03-18 14:16:28.000000000","message":"Tarek, I wrote a detailed reasoning why I prefer to implement the halt code for Cortex-M7 only. Either persuade me that I\u0027m wrong or accept my proposal (it\u0027s one additional condition only).","commit_id":"e9265b30b74ba665f965bf0ccf756401be21bc8b"}],"src/target/cortex_m.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"161082f0eca2fdabe7aaf1b72dd96e18fe416d10","unresolved":true,"context_lines":[{"line_number":1152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1153,"context_line":"\t\treturn retval;"},{"line_number":1154,"context_line":""},{"line_number":1155,"context_line":"\t/* Enter Debug state before setting 1 to AIRCR_VECTRESET */"},{"line_number":1156,"context_line":"\tretval \u003d cortex_m_write_debug_halt_mask(target, C_HALT, 0);"},{"line_number":1157,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1158,"context_line":"\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"a11f570e_a10e6e08","line":1155,"updated":"2023-03-03 22:51:14.000000000","message":"Add in the comment:\nRequired by ARM DDI0403E.B, chapter B3.2.6 \"Application Interrupt and Reset Control Register, AIRCR\"","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1002119,"name":"Fedi Bouzazi","email":"fedi.bouzazi@st.com","username":"FBOSTM"},"change_message_id":"76daa939a80d31d62367702a0b2435f9d87281f7","unresolved":false,"context_lines":[{"line_number":1152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1153,"context_line":"\t\treturn retval;"},{"line_number":1154,"context_line":""},{"line_number":1155,"context_line":"\t/* Enter Debug state before setting 1 to AIRCR_VECTRESET */"},{"line_number":1156,"context_line":"\tretval \u003d cortex_m_write_debug_halt_mask(target, C_HALT, 0);"},{"line_number":1157,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1158,"context_line":"\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"329989bf_1cefcd73","line":1155,"in_reply_to":"a11f570e_a10e6e08","updated":"2023-03-29 09:07:57.000000000","message":"Done","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a00d89cae0f4812dc7ac5d801cb3aeb370c42c7b","unresolved":true,"context_lines":[{"line_number":1166,"context_line":"\t\t\t\tcortex_m_poll(target);"},{"line_number":1167,"context_line":"\t\t\t\treturn ERROR_OK;"},{"line_number":1168,"context_line":"\t\t\t}"},{"line_number":1169,"context_line":"\t\t\tLOG_TARGET_DEBUG(target, \"waiting for system reset-halt, \""},{"line_number":1170,"context_line":"\t\t\t\t\"DHCSR 0x%08\" PRIx32 \", %d ms\","},{"line_number":1171,"context_line":"\t\t\t\tcortex_m-\u003edcb_dhcsr, timeout);"},{"line_number":1172,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"58623e22_dcd0aefb","line":1169,"updated":"2023-03-04 16:01:03.000000000","message":"One message per each millisecond of waiting may flood the log.\nSame in the original code below.","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1002119,"name":"Fedi Bouzazi","email":"fedi.bouzazi@st.com","username":"FBOSTM"},"change_message_id":"76daa939a80d31d62367702a0b2435f9d87281f7","unresolved":false,"context_lines":[{"line_number":1166,"context_line":"\t\t\t\tcortex_m_poll(target);"},{"line_number":1167,"context_line":"\t\t\t\treturn ERROR_OK;"},{"line_number":1168,"context_line":"\t\t\t}"},{"line_number":1169,"context_line":"\t\t\tLOG_TARGET_DEBUG(target, \"waiting for system reset-halt, \""},{"line_number":1170,"context_line":"\t\t\t\t\"DHCSR 0x%08\" PRIx32 \", %d ms\","},{"line_number":1171,"context_line":"\t\t\t\tcortex_m-\u003edcb_dhcsr, timeout);"},{"line_number":1172,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"da86afc2_d59ed2b7","line":1169,"in_reply_to":"58623e22_dcd0aefb","updated":"2023-03-29 09:07:57.000000000","message":"No need to add message every millisecond. log message deleted.","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a00d89cae0f4812dc7ac5d801cb3aeb370c42c7b","unresolved":true,"context_lines":[{"line_number":1208,"context_line":"\t\t\t\t/* FIXME restore user\u0027s vector catch config */"},{"line_number":1209,"context_line":"\t\t\t\treturn ERROR_OK;"},{"line_number":1210,"context_line":"\t\t\t} else {"},{"line_number":1211,"context_line":"\t\t\t\tLOG_TARGET_DEBUG(target, \"waiting for system reset-halt, \""},{"line_number":1212,"context_line":"\t\t\t\t\t\"DHCSR 0x%08\" PRIx32 \", %d ms\","},{"line_number":1213,"context_line":"\t\t\t\t\tcortex_m-\u003edcb_dhcsr, timeout);"},{"line_number":1214,"context_line":"\t\t\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"cd0bc480_59f9f2ad","line":1211,"updated":"2023-03-04 16:01:03.000000000","message":"Same as above","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"},{"author":{"_account_id":1002119,"name":"Fedi Bouzazi","email":"fedi.bouzazi@st.com","username":"FBOSTM"},"change_message_id":"76daa939a80d31d62367702a0b2435f9d87281f7","unresolved":false,"context_lines":[{"line_number":1208,"context_line":"\t\t\t\t/* FIXME restore user\u0027s vector catch config */"},{"line_number":1209,"context_line":"\t\t\t\treturn ERROR_OK;"},{"line_number":1210,"context_line":"\t\t\t} else {"},{"line_number":1211,"context_line":"\t\t\t\tLOG_TARGET_DEBUG(target, \"waiting for system reset-halt, \""},{"line_number":1212,"context_line":"\t\t\t\t\t\"DHCSR 0x%08\" PRIx32 \", %d ms\","},{"line_number":1213,"context_line":"\t\t\t\t\tcortex_m-\u003edcb_dhcsr, timeout);"},{"line_number":1214,"context_line":"\t\t\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"4e3f8e91_8fa5222b","line":1211,"in_reply_to":"cd0bc480_59f9f2ad","updated":"2023-03-29 09:07:57.000000000","message":"No need to add message every millisecond. log message deleted","commit_id":"2319d2e329dc2e007d8a3e3f0c686dc980feebb9"}]}