)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a9819ac2675ce5fd9c80ff1a2d7257fa82b08daf","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1b6d6302_ed37c20d","updated":"2023-03-10 12:07:24.000000000","message":"Kai,\nI don\u0027t have a FPGA environment to test completely these additional 3 patches.\nWould you mind reviewing and testing them?\nThanks","commit_id":"75a9dec49e11191c77efeadaa054e1b989567025"}]}