)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"56c50ae838f7756a1d1d7e26a430cb4ddc546673","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"2995c228_8fddfcdb","updated":"2023-05-10 16:46:10.000000000","message":"Thanks for the patch","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5fb6f122680daa69455cb0d8ef335147ce3bbf22","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"b89d4df3_31815cf6","updated":"2023-05-12 14:40:50.000000000","message":"Antonio wrote:\n\n\u003e Tomas, do you have any hint or any way to test with some old chip?\n\nSorry, I don\u0027t have any, neither I remember anybody who does...","commit_id":"f01161d697667d45d1bcae047dcbe2c4b199fb39"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"25fb11a9f61d028cf58ca6a7dfac17383957e81b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"25552fbe_bb24ccaa","updated":"2023-05-12 13:32:41.000000000","message":"thanks","commit_id":"f01161d697667d45d1bcae047dcbe2c4b199fb39"}],"tcl/target/ti_tms570.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"56c50ae838f7756a1d1d7e26a430cb4ddc546673","unresolved":true,"context_lines":[{"line_number":22,"context_line":"if { [info exists DAP_TAPID] } {"},{"line_number":23,"context_line":"\tset _DAP_TAPID $DAP_TAPID"},{"line_number":24,"context_line":"}"},{"line_number":25,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable"},{"line_number":26,"context_line":"jtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\""},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"# ICEpick-C (JTAG route controller)"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"01689e61_15928e0b","line":25,"updated":"2023-05-10 16:46:10.000000000","message":"Adding here and at next comment the flag \"-ignore-version\", then the 4 MSB bits of the TAP id are ignored (masked with 0x0fffffff).\nWith both lines modified, you can use a single file\ntcl/target/ti_tms570lc43xxx.cfg\nfor both version A and B of the chip","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"cce9214197775953e5f63253aec094d5b8d3be2a","unresolved":true,"context_lines":[{"line_number":22,"context_line":"if { [info exists DAP_TAPID] } {"},{"line_number":23,"context_line":"\tset _DAP_TAPID $DAP_TAPID"},{"line_number":24,"context_line":"}"},{"line_number":25,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable"},{"line_number":26,"context_line":"jtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\""},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"# ICEpick-C (JTAG route controller)"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"f8e3cddc_7efe35f9","line":25,"in_reply_to":"01689e61_15928e0b","updated":"2023-05-11 07:44:57.000000000","message":"For this and the next comment, I\u0027ll test later today and get back to you.","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"e47d11b802f9364d5f88ae57e271cad5034929fe","unresolved":false,"context_lines":[{"line_number":22,"context_line":"if { [info exists DAP_TAPID] } {"},{"line_number":23,"context_line":"\tset _DAP_TAPID $DAP_TAPID"},{"line_number":24,"context_line":"}"},{"line_number":25,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable"},{"line_number":26,"context_line":"jtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\""},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"# ICEpick-C (JTAG route controller)"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"6d390b76_22a2d0ce","line":25,"in_reply_to":"f8e3cddc_7efe35f9","updated":"2023-05-12 13:15:31.000000000","message":"Applied the ignore version, condensed to a single target, and tested.  Works great!","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"56c50ae838f7756a1d1d7e26a430cb4ddc546673","unresolved":true,"context_lines":[{"line_number":41,"context_line":"set _JRC_TAPID9 0x3D8A002F"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\"},{"line_number":45,"context_line":"\t-expected-id $_JRC_TAPID \\"},{"line_number":46,"context_line":"\t-expected-id $_JRC_TAPID2 \\"},{"line_number":47,"context_line":"\t-expected-id $_JRC_TAPID3 \\"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"9af3d4fb_16056a77","line":44,"updated":"2023-05-10 16:46:10.000000000","message":"This is the other place where to add the flag \"-ignore-version\".\nWith the flag, you can then reduce the list above, as:\n- _JRC_TAPID7 and _JRC_TAPID9 can be dropped as already covered by _JRC_TAPID5;\n- _JRC_TAPID6 and _JRC_TAPID8 can be replaced by a single 0x0B8A002F","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"e47d11b802f9364d5f88ae57e271cad5034929fe","unresolved":false,"context_lines":[{"line_number":41,"context_line":"set _JRC_TAPID9 0x3D8A002F"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\"},{"line_number":45,"context_line":"\t-expected-id $_JRC_TAPID \\"},{"line_number":46,"context_line":"\t-expected-id $_JRC_TAPID2 \\"},{"line_number":47,"context_line":"\t-expected-id $_JRC_TAPID3 \\"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"1081ffed_0f3c8f8e","line":44,"in_reply_to":"9af3d4fb_16056a77","updated":"2023-05-12 13:15:31.000000000","message":"Turns out there was already an ignore-version flag.  I simplified the TAP list, modifying 6 and removing 7, 8, and 9, and tested it and it appears to function the same as before.","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"56c50ae838f7756a1d1d7e26a430cb4ddc546673","unresolved":true,"context_lines":[{"line_number":60,"context_line":"# Cortex-R4 target"},{"line_number":61,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":62,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":63,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":66,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"b3959abf_d7427920","line":63,"updated":"2023-05-10 16:46:10.000000000","message":"Humm, the value 0x00001003 looks incorrect, but it\u0027s strange nobody challenged it before\nDo you have some of the old TMS570, already supported by OpenOCD, to check?","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"60fc9acc9416f2f6f7cf541de295644bb6337388","unresolved":true,"context_lines":[{"line_number":60,"context_line":"# Cortex-R4 target"},{"line_number":61,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":62,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":63,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":66,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"8c02638c_662dbf1a","line":63,"in_reply_to":"5f56a452_51e2c39a","updated":"2023-05-11 16:47:37.000000000","message":"Sorry I wasn\u0027t clear on the notes.  For this to work with the TMS570LC43xx the change to both the LSBs and MSB are required.  In the commit message, Note 1 is regarding the MSB change, while Note 2 is regarding the LSB.\n\nWhen I was bringing this up, my first attempt was to use the original value of 0x00001003.  This doesn\u0027t work at all.  I then found the E2E post I linked in the commit message and tried a value of 0x80001003.  This worked except for the memory_fast calls.  Digging into that then lead to the stuff in Note 2 and the debugbase of 0x80001000.","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f7a6970004921cfc17250d84acd57a4591c4830b","unresolved":false,"context_lines":[{"line_number":60,"context_line":"# Cortex-R4 target"},{"line_number":61,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":62,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":63,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":66,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"bf6ebd3a_ad863442","line":63,"in_reply_to":"8c02638c_662dbf1a","updated":"2023-05-12 07:28:33.000000000","message":"Thanks for the explanation, I probably read too fast the commit msg.\nOpenOCD can also autodetect the dbgbase when it is not specified, but the autodetection can be too slow when several cores are to be detected (not in this case) so I prefer specifying dbgbase in the script.\nI think we can keep this new value, here.","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"ee894d5744e67f3a81fabd0abd976b8c4a78196f","unresolved":true,"context_lines":[{"line_number":60,"context_line":"# Cortex-R4 target"},{"line_number":61,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":62,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":63,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":66,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"5f56a452_51e2c39a","line":63,"in_reply_to":"9ea35da0_d1a99d57","updated":"2023-05-11 16:12:16.000000000","message":"The last time we have received a \"real\" patch for any TMS570 config scripts was in 2014.\nI don\u0027t know if this means:\n- everything works fine, no need to change anything, or\n- nobody uses these chips anymore with OpenOCD!\n\nIn the commit message you report you are making this change for the two low bits, but you are actually also changing the MSB.\nDoes it means the script works with either -dbgbase 0x1000 and 0x80001000 ?\nWe had this patch for alerting on this case\nhttps://review.openocd.org/5105/\nMaybe 0x80001000 is the right value to use.\n\nTomas, do you have any hint or any way to test with some old chip?","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"cce9214197775953e5f63253aec094d5b8d3be2a","unresolved":true,"context_lines":[{"line_number":60,"context_line":"# Cortex-R4 target"},{"line_number":61,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":62,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":63,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":66,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"9ea35da0_d1a99d57","line":63,"in_reply_to":"b3959abf_d7427920","updated":"2023-05-11 07:44:57.000000000","message":"Unfortunately I don\u0027t.  I only have a TMS570LC4357.  Let me know how you would like to proceed with this.","commit_id":"d03cb02c9585eb28a60080d1248011ca9c48e479"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5fb6f122680daa69455cb0d8ef335147ce3bbf22","unresolved":true,"context_lines":[{"line_number":56,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":57,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":58,"context_line":""},{"line_number":59,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":60,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"},{"line_number":61,"context_line":""},{"line_number":62,"context_line":"$_TARGETNAME configure -event \"reset-assert\" {"},{"line_number":63,"context_line":"\tglobal _CHIPNAME"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"7ea81f61_18019f4f","line":60,"range":{"start_line":59,"start_character":0,"end_line":60,"end_character":32},"updated":"2023-05-12 14:40:50.000000000","message":"Philip,\ncould you please verify if TI big endian quirk workaround is still required for your TMS570LC43xx device? Probably yes as the common config enables it and you reported the device is working. I would appreciate if you can test memory access with ti_be_32_quirks 0: all reads are expected to be byte swapped - so probably the CPU examination will fail.\nThanks!","commit_id":"f01161d697667d45d1bcae047dcbe2c4b199fb39"},{"author":{"_account_id":1002140,"name":"Philip Kirkpatrick","display_name":"Philip Kirkpatrick","email":"p.kirkpatrick@reflexaerospace.com","username":"RA-Phil-K","status":"Reflex Aerospace"},"change_message_id":"8b9c7b196ab95ef1584f8d93fb800656354b166f","unresolved":false,"context_lines":[{"line_number":56,"context_line":"target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\"},{"line_number":57,"context_line":"\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000"},{"line_number":58,"context_line":""},{"line_number":59,"context_line":"# TMS570 uses quirky BE-32 mode"},{"line_number":60,"context_line":"$_CHIPNAME.dap ti_be_32_quirks 1"},{"line_number":61,"context_line":""},{"line_number":62,"context_line":"$_TARGETNAME configure -event \"reset-assert\" {"},{"line_number":63,"context_line":"\tglobal _CHIPNAME"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"a4d190a6_0d6b8075","line":60,"range":{"start_line":59,"start_character":0,"end_line":60,"end_character":32},"in_reply_to":"7ea81f61_18019f4f","updated":"2023-05-12 16:10:55.000000000","message":"Yep, definitely fails with quirks \u003d 0.","commit_id":"f01161d697667d45d1bcae047dcbe2c4b199fb39"}]}