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{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"232ca100e735033f9e53fb1897eee7c49115d6e9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"edfe25a6_f0292683","updated":"2023-05-18 13:14:08.000000000","message":"We have already 211 patches merged since v0.12.0 and others are in queue or under review.\nLet\u0027s start sharing this file to check it for errors and/or omissions.","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"2278171d4b32364feaddc26ae9dba8a70c49a7a9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"5a1d6d87_079dcee4","updated":"2023-07-08 18:44:51.000000000","message":"Daniel, is it ok now concerning the new Xilinx devices?","commit_id":"757820646a77bc355dfe9902f99fc59ab28e992c"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"3a3cfc02fbe7df1cebf30e822557c99be1c01c79","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"5b997377_acd19f30","updated":"2023-12-06 10:01:20.000000000","message":"I think we got it now! thanks.\n\nOne last thing, if the patches 7978 to 7980 can also make it into the next release I would be super happy. It\u0027s a massive (30x) speed improvement for ipdbg.","commit_id":"757820646a77bc355dfe9902f99fc59ab28e992c"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"710817039e981bcaad905d5cbd0ef445c48b880d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"a3a8f060_3cb6cf2b","in_reply_to":"5a1d6d87_079dcee4","updated":"2023-07-10 20:30:05.000000000","message":"Antonio, yes sure!\nI\u0027d like to have 7715 and 7716 (ultrascale and devices with longer ir) in it too, but it\u0027s ok like this.\nThanks.","commit_id":"757820646a77bc355dfe9902f99fc59ab28e992c"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"616d410c8d6e847d6beb683dba676f68ac14a987","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"c9b33ec1_6db757f1","in_reply_to":"a3a8f060_3cb6cf2b","updated":"2023-07-24 00:15:35.000000000","message":"Hi Antonio\n\nPlease review/merge 7821 before a new release. Without 7821 most xilinx tcl scripts will fail:\n\"Error: The \u0027virtex2 set_user_codes\u0027 command must be used after \u0027init\u0027.\"\nMy apologies - I don\u0027t know why I couldn\u0027t catch it earlier.","commit_id":"757820646a77bc355dfe9902f99fc59ab28e992c"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"7a76aee20d8b701e6202b8480e5643dd078d75d2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7510b0fd_fb97b1df","updated":"2024-06-15 15:26:37.000000000","message":"It\u0027s time for a new release!","commit_id":"ca4333281c45c520f43a3cd7455433b63dfce3f9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"22f57d5527480dad0c222f8ad53b4fc1f3fc43e1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"71aa0c3a_89dc4917","updated":"2024-12-22 10:09:20.000000000","message":"We failed to tag OpenOCD v0.13.0 in 2024. Never mind!\nLet\u0027s target directly for OpenOCD v1.0.0 in 2025.\nMy proposal is to drop rc1 before summer, having enough time to finalize the release before the end of the year.","commit_id":"97bcd4ae2926a984ea9dea5d42119d74598f005d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b32a9d432864bcdcef11f7acc2087136d85000d1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":9,"id":"8e7d1a96_0359d414","updated":"2025-09-11 07:55:44.000000000","message":"Some linux distributions already released a version witch uses libgpiod v2\n(e.g. Debian Trixie). I do not understand why the patch series on top of\n8202: jtag: linuxgpiod: wrap gpiod_request_config from libgpiod v2 | https://review.openocd.org/c/openocd/+/8202\nis still marked as WIP and nobody responds to comments here.\nI think we should finish libgpiod v2 support and include it to the upcoming release.\nAntonio, could you take a look?","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c63f6c96dfca777f162d7efddc5571e61823650b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"de3108cb_c0526c54","in_reply_to":"2cd9bc3e_5501ff67","updated":"2025-12-14 21:33:25.000000000","message":"Done","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"dad3420d579e5581bc27e6cde5968e47caf1c457","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":9,"id":"2cd9bc3e_5501ff67","in_reply_to":"8e7d1a96_0359d414","updated":"2025-09-11 08:03:16.000000000","message":"I consider only two last points to be relevant before v1.0.0: libgpio v2 and passing the risc-v tests proposed by Evgeniy on August 13 in https://review.openocd.org/c/openocd/+/8893\nNot much time available on my side for, at least, the next two weeks.","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7559f0d4098f3431d4674fb0f1aa58e641b12c","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":9,"id":"dbce7230_cb7c1428","in_reply_to":"ae9093e3_f9031dcc","updated":"2026-05-01 20:29:15.000000000","message":"Thanks Tomas.\nI would like to merge before rc1 also the two series below\nhttps://review.openocd.org/c/openocd/+/9585\nhttps://review.openocd.org/c/openocd/+/9507\nsince they change some Tcl command, so as soon as they are merged, the earlier we can drop the deprecated procs.\nAnd if someone can run a review, also the long\nhttps://review.openocd.org/c/openocd/+/9551\nbefore it hits a merge conflict","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"426de5cbc237013627ffd598474f71ab7d824af9","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":9,"id":"ea290295_6c0d77d7","in_reply_to":"de3108cb_c0526c54","updated":"2026-01-06 07:38:23.000000000","message":"Antonio, to actually finish riscv sync we should decide about\n6964: target: base poll frequency on wall time | https://review.openocd.org/c/openocd/+/6964\n\nTo avoid FIXME comments in this patch I created\n9180: target: introduce active_polled flag in struct target | https://review.openocd.org/c/openocd/+/9180\nwhich IMO should be merged regardless of 6964, but it\u0027s not reviewed\n\nThere are also 3 pending riscv fixes around\n9276: target/riscv: do not set DTM_DTMCS_VERSION_UNKNOWN on examine fail | https://review.openocd.org/c/openocd/+/9276\nwhich I\u0027d like to merge before tagging rc","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"572ead0f18d2df5d3b1a2eb1c2179525ccf4f8cf","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":9,"id":"ae9093e3_f9031dcc","in_reply_to":"ea290295_6c0d77d7","updated":"2026-04-29 10:59:18.000000000","message":"Antonio, I self-approved and merged couple of patches nobody cares about.\n\n6964: target: base poll frequency on wall time | https://review.openocd.org/c/openocd/+/6964\nhas currently score +1 and could be merged soon.\nI think we can finally tag rc1 after merging 6964","commit_id":"1b4e35e4c30cfda181f7a4719bdd8958ff7bf862"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"38fcbedd4b81c477ae29a8ea419fbadaa2744fff","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"ddd9886f_768fcd5d","updated":"2026-05-18 18:21:58.000000000","message":"Antonio, unfortunately I believe I have found a blocker. See [1].\n1: https://review.openocd.org/c/openocd/+/8404/comments/95b76a8b_367ac9af","commit_id":"e7e62d107cadcb2d0d369e33812dd0aec9354dbd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"24eff1b3e82aed1b1cf14aa4c4a5587aafd5ceb4","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"91c20271_4b4d512a","updated":"2026-06-04 11:55:53.000000000","message":"If at all possible I\u0027d like to include 9729 -- It\u0027s a simple fix to some memory management issues in `target smp`","commit_id":"e7e62d107cadcb2d0d369e33812dd0aec9354dbd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"78a6b131125f2e1df196f0ede84ccbfabdeb3c96","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":13,"id":"09ae80de_7c3c370f","in_reply_to":"ddd9886f_768fcd5d","updated":"2026-05-18 18:24:51.000000000","message":"Sorry, forgot to mark as unresolved.","commit_id":"e7e62d107cadcb2d0d369e33812dd0aec9354dbd"}],"NEWS":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"ffbb8c0466710ac73eecf28b51174aa89c2816a1","unresolved":true,"context_lines":[{"line_number":3,"context_line":""},{"line_number":4,"context_line":"JTAG Layer:"},{"line_number":5,"context_line":"\t* Andes AICE adapter dropped"},{"line_number":6,"context_line":"\t* JLink support for SWD multidrop"},{"line_number":7,"context_line":""},{"line_number":8,"context_line":"Boundary Scan:"},{"line_number":9,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":1,"id":"753dc848_58180bf9","line":6,"updated":"2023-05-20 08:19:23.000000000","message":"J-Link","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"d11cc3591a55a0b8a370fb06923236e7fe02c4d6","unresolved":false,"context_lines":[{"line_number":3,"context_line":""},{"line_number":4,"context_line":"JTAG Layer:"},{"line_number":5,"context_line":"\t* Andes AICE adapter dropped"},{"line_number":6,"context_line":"\t* JLink support for SWD multidrop"},{"line_number":7,"context_line":""},{"line_number":8,"context_line":"Boundary Scan:"},{"line_number":9,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":1,"id":"1b838099_c94bc404","line":6,"in_reply_to":"753dc848_58180bf9","updated":"2023-05-22 21:29:12.000000000","message":"Thanks. Fixed locally, I will send a new version after some time!","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"45ca595eaf3c43d43d965c7761bf79af585fbf7d","unresolved":true,"context_lines":[{"line_number":32,"context_line":"\t* Efinix Trion and Titanium FPGA families config"},{"line_number":33,"context_line":"\t* Intel (former Altera) Arria II, Cyclone III, Cyclone IV, Cyclone V and Cyclone 10 FPGA families config"},{"line_number":34,"context_line":"\t* Lattice Certus, CertusPro, ECP2, ECP3 and ECP5 FPGA families config"},{"line_number":35,"context_line":"\t* Xilinx Virtex 6 FPGA families config"},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"PLD Layer:"},{"line_number":38,"context_line":"\t* Efinix Trion and Titanium FPGA families support"}],"source_content_type":"application/octet-stream","patch_set":1,"id":"18b0b467_fadbdfd5","line":35,"range":{"start_line":35,"start_character":2,"end_line":35,"end_character":39},"updated":"2023-05-18 19:29:48.000000000","message":"virtex 6 is not working yet:\n- not possible to load a bitstream (diffrent instructions for 10-bit irlength))\n- no Configuration Scripts available\n\nwhat should work:\n- read_status\n- ipdbg server (not tested)\n\nI have a set of patches to fix this issues.","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"2278171d4b32364feaddc26ae9dba8a70c49a7a9","unresolved":false,"context_lines":[{"line_number":32,"context_line":"\t* Efinix Trion and Titanium FPGA families config"},{"line_number":33,"context_line":"\t* Intel (former Altera) Arria II, Cyclone III, Cyclone IV, Cyclone V and Cyclone 10 FPGA families config"},{"line_number":34,"context_line":"\t* Lattice Certus, CertusPro, ECP2, ECP3 and ECP5 FPGA families config"},{"line_number":35,"context_line":"\t* Xilinx Virtex 6 FPGA families config"},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"PLD Layer:"},{"line_number":38,"context_line":"\t* Efinix Trion and Titanium FPGA families support"}],"source_content_type":"application/octet-stream","patch_set":1,"id":"a37a0a83_17ad8b9b","line":35,"range":{"start_line":35,"start_character":2,"end_line":35,"end_character":39},"in_reply_to":"023989ef_60218882","updated":"2023-07-08 18:44:51.000000000","message":"Ack","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"d11cc3591a55a0b8a370fb06923236e7fe02c4d6","unresolved":true,"context_lines":[{"line_number":32,"context_line":"\t* Efinix Trion and Titanium FPGA families config"},{"line_number":33,"context_line":"\t* Intel (former Altera) Arria II, Cyclone III, Cyclone IV, Cyclone V and Cyclone 10 FPGA families config"},{"line_number":34,"context_line":"\t* Lattice Certus, CertusPro, ECP2, ECP3 and ECP5 FPGA families config"},{"line_number":35,"context_line":"\t* Xilinx Virtex 6 FPGA families config"},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"PLD Layer:"},{"line_number":38,"context_line":"\t* Efinix Trion and Titanium FPGA families support"}],"source_content_type":"application/octet-stream","patch_set":1,"id":"023989ef_60218882","line":35,"range":{"start_line":35,"start_character":2,"end_line":35,"end_character":39},"in_reply_to":"18b0b467_fadbdfd5","updated":"2023-05-22 21:29:12.000000000","message":"You are right! I don\u0027t remember in which iteration of your code I added this.\nWhile waiting for merging your new patches, I will keep it but left this comment as not \u0027resolved\u0027.","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1001810,"name":"Daniel Anselmi","email":"danselmi@gmx.ch","username":"danselmi"},"change_message_id":"45ca595eaf3c43d43d965c7761bf79af585fbf7d","unresolved":true,"context_lines":[{"line_number":39,"context_line":"\t* Gowin FPGA families support"},{"line_number":40,"context_line":"\t* Intel (former Altera) Arria II, Cyclone III, Cyclone IV, Cyclone V and Cyclone 10 FPGA families support"},{"line_number":41,"context_line":"\t* Lattice Certus, CertusPro, ECP2, ECP3 and ECP5 FPGA families support"},{"line_number":42,"context_line":"\t* Xilinx Virtex 6 FPGA families support"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"Server Layer:"},{"line_number":45,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":1,"id":"df8ca7c0_b6d50e29","line":42,"range":{"start_line":42,"start_character":1,"end_line":42,"end_character":40},"updated":"2023-05-18 19:29:48.000000000","message":"dito","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"2278171d4b32364feaddc26ae9dba8a70c49a7a9","unresolved":false,"context_lines":[{"line_number":39,"context_line":"\t* Gowin FPGA families support"},{"line_number":40,"context_line":"\t* Intel (former Altera) Arria II, Cyclone III, Cyclone IV, Cyclone V and Cyclone 10 FPGA families support"},{"line_number":41,"context_line":"\t* Lattice Certus, CertusPro, ECP2, ECP3 and ECP5 FPGA families support"},{"line_number":42,"context_line":"\t* Xilinx Virtex 6 FPGA families support"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"Server Layer:"},{"line_number":45,"context_line":""}],"source_content_type":"application/octet-stream","patch_set":1,"id":"540be323_9bbd192f","line":42,"range":{"start_line":42,"start_character":1,"end_line":42,"end_character":40},"in_reply_to":"df8ca7c0_b6d50e29","updated":"2023-07-08 18:44:51.000000000","message":"Ack","commit_id":"2ee2c3d1a326f976f5125a55fb9dba8043bc0360"}]}