)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"728f0d3c2798b3f74ba12c3e5e26fdb99853d488","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"d2a9ff04_57546594","updated":"2023-08-22 15:23:12.000000000","message":"Thanks for the tests.\nThe performance impact doesn\u0027t look relevant, so I would consider as cleaner the move to GPIOs \u003e\u003d32 by default, thus dropping the old code and avoiding the #if.\n\nBut your test measures the total time for OpenOCD to start, test and shutdown.\n\nTCL offers the \"time\" command to measure the time duration of a command.\necho [time {sleep 100}]\nreturns\n102267 microseconds per iteration\n\nWould it be possible to re-run the tests using such more accurate measurement?","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"927ed017148198cb6076f608a2367d3fb8e7778b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"1f566711_ea541e08","updated":"2023-08-18 13:04:26.000000000","message":"What _is_ the performance impact?  If you have some measurements, it would help evaluate whether we really need to have this conditional path at all, or just use a single form.","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"9fce4d174fcacdeb62a743d333fd0374cec0af8b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"28b39d2a_a6cc70e1","in_reply_to":"04cc06e8_1fc75c6c","updated":"2023-08-22 14:09:57.000000000","message":"We found an stm32f4 dev board lying around and a spare RPi CM3 IO board. We\u0027re not seeing much degradation on SWDIO\n\n```\n### Number of stores reflects the compile uses bulk operations (and thus, not --enable-bcm2835_all_gpio)\nroot@rpi-8e5db4:~/openocd/tcl# aarch64-linux-gnu-objdump -d ~/openocd_low_pins | awk -v RS\u003d \u0027/^[[:xdigit:]]+ \u003cbcm2835gpio_write\u003e/\u0027 | grep str | wc -l\n2\n\n\n### Read block 0\nroot@rpi-8e5db4:~/openocd/tcl# time ~/openocd_low_pins -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0+dev-00247-gd68783be7 (2023-08-21-13:39)\nLicensed under GNU GPL v2\nFor bug reports, read\n    http://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\nInfo : Target not halted\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread\nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\nshutdown command invoked\n\nreal    0m29.044s\nuser    0m28.594s\nsys 0m0.033s\n\n\n### Erase and Program\nroot@rpi-8e5db4:~/openocd/tcl# time ~/openocd_low_pins -f ./stm32f4_rpi.cfg \nOpen On-Chip Debugger 0.12.0+dev-00247-gd68783be7 (2023-08-21-13:39)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\nInfo : Target not halted\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n** Verify Started **\n** Verified OK **\nshutdown command invoked\n\nreal\t0m10.062s\nuser\t0m4.431s\nsys\t0m0.069s\nroot@rpi-8e5db4:~/openocd/tcl#\n```\n\nVersus\n\n```\n### Number of stores reflects the compile uses split operations (and thus --enable-bcm2835_all_gpio)\nroot@rpi-8e5db4:~/openocd/tcl# aarch64-linux-gnu-objdump -d ../src/openocd | awk -v RS\u003d \u0027/^[[:xdigit:]]+ \u003cbcm2835gpio_write\u003e/\u0027 | grep str | wc -l\n6\n\n\n### Read block 0\nroot@rpi-8e5db4:~/openocd/tcl# time ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0+dev-00247-gd68783be7 (2023-08-21-14:20)\nLicensed under GNU GPL v2\nFor bug reports, read\n    http://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\nInfo : Target not halted\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread\nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\nshutdown command invoked\n\nreal    0m29.273s\nuser    0m28.818s\nsys 0m0.038s\nroot@rpi-8e5db4:~/openocd/tcl#\n\n\n### Erase and Program\nroot@rpi-8e5db4:~/openocd/tcl# time ../src/openocd -f ./stm32f4_rpi.cfg \nOpen On-Chip Debugger 0.12.0+dev-00247-gd68783be7 (2023-08-21-15:26)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\nInfo : Target not halted\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n** Verify Started **\n** Verified OK **\nshutdown command invoked\n\nreal\t0m10.325s\nuser\t0m4.561s\nsys\t0m0.083s\nroot@rpi-8e5db4:~/openocd/tcl# \n```\n\n### config file:\n```\n# OpenOCD configuration for raspberry pi\n\nadapter driver bcm2835gpio\n\nadapter gpio swclk 41\nadapter gpio swdio 38\n\n# Use for hardware reset\n#adapter gpio srst 18\n\nadapter srst delay 100\nadapter srst pulse_width 100\n# Use for hardware reset\n#reset_config srst_only srst_push_pull\n\n# Remove for hardware reset\nreset_config none separate\n\ntransport select swd\n\n# Device flash is 512KB\nset WORKAREASIZE 0x80000\n\nsource [find target/stm32f4x.cfg]\nadapter speed 100\n\ninit\ntargets\n\n# Use for hardware reset\n#reset halt\n\n# Remove for hardware reset\nsoft_reset_halt\n\nstm32f4x unlock 0\nstm32f4x mass_erase 0\nprogram /root/F411E-DISCO.hex verify\n#flash read_bank 0 STM32_BANK0.hex\n\nreset\nshutdown\n```","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"9c23e81a9828e031e2dd4b5c6ba40d0439ff3576","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"3ba33b2a_bb4f803b","in_reply_to":"1f566711_ea541e08","updated":"2023-08-18 14:22:57.000000000","message":"Is there a standard method to collect performance data? If so, I\u0027d like to provide that if possible, otherwise I can ask my team to collect some timings for programming images over JTAG: \n\n1. before changes (--enable-bcm2835gpio before patch is introduced)\n2. with the new macros (--enable-bcm2835gpio after patch is introduced)\n3. without the bulk operations (--enable-bcm2835gpio_all_gpio)","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"7449cd684c6f4a75d11dba5e4cb46349b7e7380d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"04cc06e8_1fc75c6c","in_reply_to":"394e4ff6_c565852b","updated":"2023-08-21 15:56:22.000000000","message":"Our deployment is a little \"unique\", so our test cases are a bit limited. Right now we have GPIO pins routed directly to an Altera Max10. Early performance tests show that JTAG programming @ 1MHz has a ~14% degradation with standard compile flags when doing SVF programming when not using the bulk operations, taking a 5 minute programming job to 5:40.\n\n\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"./max10fw.svf\"\n\n\nPre patch\n\nTime used: 5m0s225ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m0s328ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m0s365ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\n\n\nPost patch (lower pin support only)\n\nTime used: 5m0s158ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m0s372ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m0s291ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\n\nPost patch (full pin support)\n\nTime used: 5m42s64ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m41s882ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\nTime used: 5m41s923ms \nsvf file programmed successfully for 242257 commands with 0 errors\n\n\nI considered making the support dynamic vs being a compile-time flag... without profiling to know for a fact, I assume that the hotspot is bcm2835gpio_write with the now 6 stores vs 2 stores, but even if this was enabled dynamically, there will still be multiple paths to keep in sync, which seems discouraged.","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a7c5235e7c7a436515978672e92f41a5cf672536","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"394e4ff6_c565852b","in_reply_to":"3ba33b2a_bb4f803b","updated":"2023-08-18 20:23:01.000000000","message":"I have a strong allergy against #if/#endif. I would like to avoid it.\nIt requires recompile for user that want it, which is not always welcome.\nA code fix on one side of the condition will require testing and keeping aligned the other side.\nLet\u0027s see if can be dropped.\n\nFor a performance test, I would suggest a buffer read or write from target\u0027s RAM, or a buffer read from target flash.\nEither commands load_image (RAM write), and/or dump_image or verify_image (RAM or flash read)\nR/W a big amount of data, measure the time and compute the speed in byte/s.","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"051dffffb464f2ecafc35c9e02677b5ffc2c8417","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"992f047b_5e27ddb7","in_reply_to":"d2a9ff04_57546594","updated":"2023-08-22 16:24:08.000000000","message":"I\u0027ll work on getting the timings you requested.\n\nDoes it make sense to have an optimized code path if the pins _can_ be set in bulk? I\u0027m picturing something similar to what is being done with `bcm2835gpio_swd_write_fast`","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"c1ac44401a024547f401380b4bdd746334fd7adf","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"fe16eda4_aa69696e","updated":"2023-09-13 04:53:05.000000000","message":"Hm... do I see it correctly. This openocd driver depends on not mainlinable linux kernel driver?","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"4280a856ea7f159580b34a8c8d0271c8c6a51ed5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"dd922c5d_0033a098","updated":"2023-09-11 21:04:33.000000000","message":"I\u0027ve updated the implementation to not be based on a configure flag. Support is baked in for the full range of GPIO pins. Bulk updates are still used when possible, otherwise pins are toggled individually when bulk updates are not possible.\n\nPerformance degradation is largely minimal. ~-5% for split writes on JTAG, ~-\u003c0.1% for split writes on SWD.\n\n\nJTAG Timings\n----\n\nJTAG with current in-tree driver\n\n```\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    307014988 microseconds per iteration\nshutdown command invoked\n\nreal\t5m7.042s\nuser\t5m5.802s\nsys\t0m0.530s\n\n\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    306943687 microseconds per iteration\nshutdown command invoked\n\nreal\t5m6.972s\nuser\t5m5.730s\nsys\t0m0.558s\n\n```\n\nJTAG with bulk updates (pins share memory offset). Performance is largely inline with previous code\n\n```\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    306960159 microseconds per iteration\nshutdown command invoked\n\nreal\t5m6.988s\nuser\t5m5.643s\nsys\t0m0.668s\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    306982540 microseconds per iteration\nshutdown command invoked\n\nreal\t5m7.011s\nuser\t5m5.861s\nsys\t0m0.438s\n```\n\nJTAG with split writes (pins do not share an offset). New logic does 3 stores vs the previous 6. There\u0027s roughly a ~5% degradation with this change which is better than the previous ~14% degradation:\n\n```\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 1995 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    322234651 microseconds per iteration\nshutdown command invoked\n\nreal\t5m22.263s\nuser\t5m20.693s\nsys\t0m0.832s\nroot@rpi-8e5db4:~/openocd# time ./src/openocd -f ../max10.cfg\nOpen On-Chip Debugger 0.12.0-01018-g0b8496aec (2023-09-07-12:25)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 1995 kHz\nInfo : JTAG tap: 10M08SCU169I7G.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : gdb services need one or more targets defined\nsvf processing file: \"/root/max10fw.svf\"\n0%    adapter speed: 997 kHz\n\n95%    322259160 microseconds per iteration\nshutdown command invoked\n\nreal\t5m22.287s\nuser\t5m20.692s\nsys\t0m0.804s\n```\n\nSWD Timings\n----\n\nNot much of a degradation is seen between bulk vs split writes, probably because both pathways do two memory stores\n\nBulk operations:\n```\nOpen On-Chip Debugger 0.12.0-01019-g7f5822821 (2023-09-11-11:27)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n\nunlock...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n410846 microseconds per iteration\n\nmass_erase...\n8229927 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n1193710 microseconds per iteration\n\nverify...\n69868 microseconds per iteration\nshutdown command invoked\n```\n\n512KiB\nErased in 8.229 seconds\nProgrammed in 1.193 seconds\n\n\nSplit operations:\n```\nOpen On-Chip Debugger 0.12.0-01019-g7f5822821 (2023-09-11-11:27)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n\nunlock...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n413888 microseconds per iteration\n\nmass_erase...\n8236443 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n1197630 microseconds per iteration\n\nverify...\n69906 microseconds per iteration\nshutdown command invoked\n```\n\n512KiB\nErased in 8.236 seconds\nProgrammed in 1.197 seconds","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c3afe2d6b681273022ab793b4bc6cdd19b8baaaa","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"d720717e_b99a95fd","updated":"2023-09-17 17:15:13.000000000","message":"Thanks for removing the #if/#endif\nThe performance test on flash erase and flash write are not really useful because the flash driver synchronizes with the flash speed, way slower than the JTAG/SWD.\nPlease use only SRAM read/write or FLASH read for the tests.\nStill, please don\u0027t use time to get the whole start-exec-end time of OpenOCD, but use the TCL syntax\necho [time {command to test}]\nFor example, \"after\" you have programmed the flash with\nprogram /root/F411E-DISCO.hex\nrun\necho [time {flash verify_image /root/F411E-DISCO.hex}]","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"747a786471ab49ee8ab6a4d6ada455f31fdc415f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"6743433e_988b9120","in_reply_to":"5186c842_49b3bb65","updated":"2023-09-14 12:45:06.000000000","message":"The openocd driver does still support the /dev/mem interface as an option IIRC. It\u0027s just not the default. Most users should not be running a non RPi foundation kernel anyway on an RPi. Regardless, I think this is beyond the scope of this changeset and can be tackled in a different commit if it\u0027s considered problematic.","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"33d6eb5996b40f0bbeb64fd7fc513060b2a37507","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"fb77305e_1d96de69","in_reply_to":"6743433e_988b9120","updated":"2023-09-14 12:50:24.000000000","message":"Agreed, it is out of scope of this patch. I just noticed this issue.\n\"Most users should not be running a non RPi foundation kernel anyway on an RPi.\" - this is even worse statement. In this case, let\u0027s integrate all interfaces for all fancy downstream kernel what ever exist :)","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"d4d71791fb91bb6b6e90187ab8fd66079f9190fb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"5186c842_49b3bb65","in_reply_to":"8c315397_74a8a143","updated":"2023-09-14 12:35:19.000000000","message":"I mean, /dev/gpiomem is not support by mainline version of linux kernel v6.6-rc1. And I\u0027m pretty sure, it will not be supported by any other kernel version, except by accident.","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1fe7947b8448367b12ba9c2b70934019f7bf6439","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"fb0bf7b0_76fa9ff8","in_reply_to":"d720717e_b99a95fd","updated":"2023-09-17 17:58:23.000000000","message":"I posted JTAG timings for completeness to show that there is an impact, though negligible.\n\nThe SWD timings do not use Linux time and do use the TCL time command. I see I did not include timings for reading, but the flash erase, program and verify are included as I had done in the previous iteration of this patch.\n\nThe amount of testing I can do is limited to the hardware we have available. \n\nIf others are able to apply the patch and provide timings, that would be appreciated","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"d44f277e7aaac4b47c18ccdcde0fc70af27b6155","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"b74bc22d_ccdc9edb","in_reply_to":"fb0bf7b0_76fa9ff8","updated":"2023-09-19 17:53:41.000000000","message":"SWD Config\n```\nroot@rpi-be20e2:~/openocd/tcl# cat stm32f4_rpi.cfg\n# OpenOCD configuration for raspberry pi\n\nadapter driver bcm2835gpio\n\nadapter gpio swclk 41\nadapter gpio swdio 38\n\n# Use for hardware reset\n#adapter gpio srst 18\n\nadapter srst delay 100\nadapter srst pulse_width 100\n# Use for hardware reset\n#reset_config srst_only srst_push_pull\n\n# Remove for hardware reset\nreset_config none separate\n\ntransport select swd\n\n# Device flash is 512KB\nset WORKAREASIZE 0x80000\n\nsource [find target/stm32f4x.cfg]\nadapter speed 100\n\ninit\ntargets\n\n# Use for hardware reset\n#reset halt\n\n# Remove for hardware reset\nsoft_reset_halt\n\necho \"\\nread_bank 0...\"\necho [time {flash read_bank 0 /root/stm32_bank0.bin}]\n\necho \"\\nunlock...\"\necho [time {stm32f4x unlock 0}]\n\necho \"\\nmass_erase...\"\necho [time {stm32f4x mass_erase 0}]\n\necho \"\\nwrite_bank 0...\"\necho [time {flash write_bank 0 /root/stm32_bank0.bin}]\n\necho \"\\nprogram...\"\necho [time {program /root/F411E-DISCO.hex}]\n\necho \"\\nverify...\"\necho [time {flash verify_image /root/F411E-DISCO.hex}]\n\nreset\nshutdown\n\n```\n\nBefore change\n```\nroot@rpi-be20e2:~/openocd/tcl# ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0-01016-g8c4570962 (2023-09-19-09:39)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n28365585 microseconds per iteration\n\nunlock...\n302053 microseconds per iteration\n\nmass_erase...\n8113250 microseconds per iteration\n\nwrite_bank 0...\n28217043 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n** Programming Started **\n** Programming Finished **\n1187167 microseconds per iteration\n\nverify...\n69931 microseconds per iteration\nshutdown command invoked\n\n```\n\nAfter change\n```\nroot@rpi-be20e2:~/openocd/tcl# ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0-01019-g7f5822821 (2023-09-11-11:27)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n28377173 microseconds per iteration\n\nunlock...\n409477 microseconds per iteration\n\nmass_erase...\n8222054 microseconds per iteration\n\nwrite_bank 0...\n28241778 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n** Programming Started **\n** Programming Finished **\n1192505 microseconds per iteration\n\nverify...\n69981 microseconds per iteration\nshutdown command invoked\n```\n\nBefore change @ 1MHz\n```\nOpen On-Chip Debugger 0.12.0-01019-g5a2c01150 (2023-09-19-10:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n3597434 microseconds per iteration\n\nunlock...\n405183 microseconds per iteration\n\nmass_erase...\n8340486 microseconds per iteration\n\nwrite_bank 0...\n3336348 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n** Programming Started **\n** Programming Finished **\n1191575 microseconds per iteration\n\nverify...\n70045 microseconds per iteration\nshutdown command invoked\n\n```\n\n\nAfter change @ 1MHz\n```\nroot@rpi-be20e2:~/openocd/tcl# ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0-01019-g5a2c01150 (2023-09-19-10:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n3620353 microseconds per iteration\n\nunlock...\n400019 microseconds per iteration\n\nmass_erase...\n8081135 microseconds per iteration\n\nwrite_bank 0...\n3330923 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n1194223 microseconds per iteration\n\nverify...\n70168 microseconds per iteration\nshutdown command invoked\n```","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"a6d29fe9999bbed58afe155b00ca1f307ac03b80","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"8c315397_74a8a143","in_reply_to":"fe16eda4_aa69696e","updated":"2023-09-13 19:45:58.000000000","message":"Can you elaborate? I\u0027m not aware of any kernel requirements other than to expose /dev/mem or /dev/gpiomem to bit bang the GPIO? These should be appropriately working in any RPi kernel, and a lot of that should be in mainline already.","commit_id":"f6bdb2c0dbc79ce74c832d2cd5f4661bfd801945"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c672de07c02011275cb56bc06000a20c26839909","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"4a1b3b4b_7e91a652","updated":"2024-02-05 19:35:44.000000000","message":"Quick question about Checkpatch-ignore vs the stash-and-store method in the macros","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1abbfa0094ac99657151a84ada65d51490e9ff22","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"fa30ba5a_79e5e8ec","updated":"2024-01-26 23:40:28.000000000","message":"Thanks for taking the time to respond! \n\nI think your comments are reasonable, but I would like some further guidance on suggested approach before submitting further changes.\n\nI\u0027ll work on the other patch (int {gpio_num,chip_num} -\u003e unsigned int {gpio_num,chip_num}) next week. Some of the questions may be moot if that patch gets accepted.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9d75fe74959302e48f54643e4d93c40e7bdb4512","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":6,"id":"182ea29b_84f8d8d0","updated":"2024-01-19 12:47:19.000000000","message":"Vincent,\nsorry I\u0027ve been ignoring this change for long time - I saw the patchset 1 with conditional compilation and thought that nobody would use it. This version is better although the question remains if anybody (other than you) needs the feature.\n\nYou ran some performance test. Unfortunately neither you nor your reviewers grasp the point what performance means in bitbanging adapter. There is little point in measuring transfer rates. The main goal is to deliver the clock at rate with reasonable precision according to the requested adapter speed. Although both JTAG and SWD are synchronous in their principle, the debug clock speed influences lot of timing around and sometimes the debug clock should not exceed some fraction of the system clock.\nSee https://review.openocd.org/c/openocd/+/7264/4/tcl/interface/raspberrypi-native.cfg\nhow the driver timing is tuned. Before #7264 using raspberrypi2-native.cfg on Rpi3+ resulted in debug overclocked 4 or more times - undoubtedly bad.\n\nThere is also work-in-progress on calibrator command https://review.openocd.org/c/openocd/+/7263\n\nAny code change in the time critical part of the driver code requires re-tune the speed factors or at least check the speeds. There is currently 6 RPi versions with different CPU speed. The new branch of \"bulk\" GPIO setting further complicates the tuning/testing.\n\nI\u0027m very unsure if the extended range of GPIOs is worth to all this effort. If the GPIO handling code were improved than okay, but your GPIO_SET/CLR macros seems me as a step back.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e8c5cb2c6ea1ad39d662611a2cb6bde785340d6f","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":6,"id":"1d573db8_8c36ca5d","in_reply_to":"182ea29b_84f8d8d0","updated":"2024-01-19 18:05:50.000000000","message":"Tomas, thanks for taking the time to review this!\n\nMy hope was to make this \"generally usable\" because if there are other vendors using an RPi, like the Compute Module, on a carrier board, it\u0027s not always up to the the consumer how the pins may be routed off-card. It\u0027s not as simple as placing wires on a GPIO header to select which pins to use as the underlying hardware may force you to use something else, and since hardware can\u0027t always conform to the limitations of software, then software can at least make it work, just maybe not at the maximum possible speeds (though, apparently that isn\u0027t the goal here as you discuss maintaining a very specific clock).\n\nI did ask a few times in this review and in IRC for help/direction in reviewing the performance changes, so I appreciate you calling this out. \n\nI discuss the GPIO_SET/CLR macros in your other comment.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"aab3170ae0d391aea011e13df6e790c60a38dc10","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":6,"id":"f9739dc3_48756dba","in_reply_to":"1d573db8_8c36ca5d","updated":"2024-01-26 19:10:18.000000000","message":"\u003e My hope was to make this \"generally usable\" because if there are other vendors using an RPi, like the Compute Module, on a carrier board, it\u0027s not always up to the the consumer how the pins may be routed off-card.\n\nAgreed.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4f0ddacc47038308358b4deb96c93d7b3b1cee33","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"e6621311_ca4042ba","in_reply_to":"f9739dc3_48756dba","updated":"2024-01-27 06:54:46.000000000","message":"Done","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"6341b171_593b2ff5","updated":"2024-02-08 07:22:26.000000000","message":"Looks very good, thanks! And thanks for thorough testing.\n\nI commented a minor issue with the type mess around reading gpio level. Actually it is mostly the old problem and partially induced by types used in bitbang calls. It could go to a separate patch if you prefer..","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"32e1b6d5e79236101d1a753b7d56d24e7b499ed0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"235cf088_7c9495b0","updated":"2024-02-07 23:13:30.000000000","message":"Updated changeset to incorporate feedback.\n\nAll pads changes have been reverted, macros are now static inline functions, paths have been consolidated and now use a `gpio_control` struct to facilitate toggling GPIO.","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c36f964450a927b19be801a671b428930e85dd4c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"1cb8c191_1cb4b5a8","updated":"2024-02-08 15:32:44.000000000","message":"Retyped output_level to bool and updated the inline function and callers.","commit_id":"c79927507af927cb7ec395befddced872400ef7a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"3eaf2cc7c83be77b4e6111d40eea24d78362166d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"453a98e1_c998848c","updated":"2024-02-08 18:34:44.000000000","message":"Thanks, Vincent! Looks good. I will test it soon.\n\nJonathan, could you take a look?","commit_id":"c79927507af927cb7ec395befddced872400ef7a"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"35ee6b3bc932e6e8662b1a74f68eacfef98ec736","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"fc3cbd32_3f2b6042","in_reply_to":"453a98e1_c998848c","updated":"2024-02-08 19:55:18.000000000","message":"Some of the changes here sort of assume some of the changes in https://review.openocd.org/c/openocd/+/8124 will land, like the gpio_pin_num members being unsigned ints.\n\nHopefully that\u0027s ok","commit_id":"c79927507af927cb7ec395befddced872400ef7a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"3bc975b3f7535938e32e62a9c228c0571e552d25","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"84b9e073_ce751786","in_reply_to":"fc3cbd32_3f2b6042","updated":"2024-02-08 21:20:31.000000000","message":"\u003e Some of the changes here sort of assume ...\n\u003e Hopefully that\u0027s ok\n\nUnfortunately it creates a conflict.\nTo make things easier I merged #8124. Please rebase this change onto the current git master.","commit_id":"c79927507af927cb7ec395befddced872400ef7a"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"d2ba3aa60e31bfe0e46c0fef1f8179292417c523","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"2f817cc6_4f474e45","updated":"2024-02-08 21:43:40.000000000","message":"Rebased after the merge of https://review.openocd.org/c/openocd/+/8124 to resolve conflicts.","commit_id":"64052969f46e411b40e23e59f4dc8f0cea7965d7"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"9f09b881646cf0dd4386959e7215cd802565c457","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"8ccfa2b4_b990871a","updated":"2025-08-14 19:20:37.000000000","message":"I realize it\u0027s been over 2 years since the original patch, but I do believe we saw reasonable speed improvements due to reduced instruction count and minimizing math for toggling these pins.\n\nI\u0027m considering rebasing this patch and resubmitting.","commit_id":"915d327e4ccfe394e65f5a7fe9afa9a497d8511e"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"27319562_4dc4889d","updated":"2025-08-15 01:07:48.000000000","message":"Resolving previous discussions as they had been covered by the last push. I have not had a chance to test this build yet, but the merge conflicts were minimal. I can try to schedule time to test this maybe next week.","commit_id":"915d327e4ccfe394e65f5a7fe9afa9a497d8511e"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"abb94bd5768d9d904e1c7822121b123847e45d98","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"c2ba63a9_2c35cecd","updated":"2025-09-23 17:43:21.000000000","message":"I promised some performance numbers after the rebase so have included them below.\n\nThe variance is roughly 1% from mainline. So, while measurable, it seems pretty low considering we get support for all pins on the platform.\n\nI would ask that this changeset be considered for inclusion into main.\n\n### JTAG\n\nBaseline\n```\nroot@rpi-8e5db4:~# /root/openocd-0_12_0-e971d677c/usr/local/bin/openocd --version\nOpen On-Chip Debugger 0.12.0+dev-02164-ge971d677c (2025-08-28-14:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nroot@rpi-8e5db4:~# \nroot@rpi-8e5db4:~# time /root/openocd-0_12_0-e971d677c/usr/local/bin/openocd --log_output svf-openocd-0_12_0-e971d677c.log -f rpi_jtag_svf.cfg ; echo \"Return Code: $?\"\nOpen On-Chip Debugger 0.12.0+dev-02164-ge971d677c (2025-08-28-14:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\n\nreal\t0m26.343s\nuser\t0m24.184s\nsys\t0m2.128s\nReturn Code: 0\nroot@rpi-8e5db4:~# \nroot@rpi-8e5db4:~# grep \u0027microseconds per iteration\u0027 svf-openocd-0_12_0-e971d677c.log \n26313990 microseconds per iteration\nroot@rpi-8e5db4:~# \n```\n\nWith changeset\n```\nroot@rpi-8e5db4:~# /root/openocd-0_12_0-3cd2b39bf/usr/local/bin/openocd --version\nOpen On-Chip Debugger 0.12.0+dev-01120-g3cd2b39bf (2025-08-28-14:57)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nroot@rpi-8e5db4:~# \nroot@rpi-8e5db4:~# time /root/openocd-0_12_0-3cd2b39bf/usr/local/bin/openocd --log_output svf-openocd-0_12_0-3cd2b39bf.log -f rpi_jtag_svf.cfg ; echo \"Return Code: $?\"\nOpen On-Chip Debugger 0.12.0+dev-01120-g3cd2b39bf (2025-08-28-14:57)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\n\nreal\t0m26.668s\nuser\t0m24.485s\nsys\t0m2.119s\nReturn Code: 0\nroot@rpi-8e5db4:~# \nroot@rpi-8e5db4:~# grep \u0027microseconds per iteration\u0027 svf-openocd-0_12_0-3cd2b39bf.log \n26637798 microseconds per iteration\nroot@rpi-8e5db4:~# \n```\n\n**Variance +1.2%**\n\n\n---\n\n### SWDIO\n\nBaseline\n```\nroot@rpi-ced5b3:~# /root/openocd-0_12_0-e971d677c/usr/local/bin/openocd --version\nOpen On-Chip Debugger 0.12.0+dev-02164-ge971d677c (2025-08-29-13:55)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nroot@rpi-ced5b3:~# \nroot@rpi-ced5b3:~# time /root/openocd-0_12_0-e971d677c/usr/local/bin/openocd -f stm32f4_rpi.cfg \nOpen On-Chip Debugger 0.12.0+dev-02164-ge971d677c (2025-08-29-13:55)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : [stm32f4x.cpu] Examination succeed\nInfo : [stm32f4x.cpu] starting gdb server on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n1109046 microseconds per iteration\n\nverify...\n68757 microseconds per iteration\nshutdown command invoked\n\nreal\t0m9.915s\nuser\t0m4.373s\nsys\t0m0.051s\n```\n\nWith Changeset\n\n```\nroot@rpi-ced5b3:~# /root/patch-openocd/usr/local/bin/openocd --version\nOpen On-Chip Debugger 0.12.0+dev-01120-g3cd2b39bf (2025-08-22-16:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nroot@rpi-ced5b3:~# \nroot@rpi-ced5b3:~# time /root/patch-openocd/usr/local/bin/openocd -f stm32f4_rpi.cfg \nOpen On-Chip Debugger 0.12.0+dev-01120-g3cd2b39bf (2025-08-22-16:28)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 100 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : [stm32f4x.cpu] Examination succeed\nInfo : [stm32f4x.cpu] starting gdb server on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc\n** Programming Started **\n** Programming Finished **\n1093364 microseconds per iteration\n\nverify...\n69513 microseconds per iteration\nshutdown command invoked\n\nreal\t0m9.959s\nuser\t0m4.413s\nsys\t0m0.042s\n```\n\n**Variance: +/- ~1.5%**","commit_id":"3cd2b39bf56686e804b10a89d4ad52490fe5214b"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c3829b2ce0b2c9bf6c8050b911681fada29a07cf","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"feb8c3ba_8421811f","in_reply_to":"92c082a2_e11e3b73","updated":"2025-09-24 14:37:38.000000000","message":"I\u0027m sorry to say that I\u0027m not sure I have the expertise to tune the `speed_offset`. I don\u0027t think we set the governor to `performance`, I think our kernels set that to on `ondemand` by default because performance mode led to lockups when there were not heat pads placed on the CPU. \n\nI will ask that we make sure to test with `performance` governors along side the changes to the read functions.\n\nWe are currently testing on a Compute Module 3 and a 3b+, so they are slightly older devices so we are likely affected by not tuning that value correctly.\n\nIs this value overrideable? Do you have suggestions for how to tune this? I\u0027m mostly concerned that I don\u0027t trust the values I would come up with.","commit_id":"3cd2b39bf56686e804b10a89d4ad52490fe5214b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0fbe5c7717572f0fdb337a48fde5b39b8c23b8a6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"92c082a2_e11e3b73","in_reply_to":"c2ba63a9_2c35cecd","updated":"2025-09-24 14:08:15.000000000","message":"Vincent,\nIMO the tests you run actually show more or less just random variations.\nDid you locked cpufreq governors to performance during testing?\nIf you want more relevant performance tests, you should use the highest `adapter speed` possible and avoid a flash algorithm witch waits for the target flash operation quite often.\n\nAnyway I tested your patch on RPi4 with 64-bit Debian 11\nand checked the clock frequency @ `adapter speed` 100, 1000 and maximum with a logic analyser. Clock freq is similarly as without the patch precise @ 100 kHz, not bad precision @ 1 MHz and approximate @ max.\n\nAs I expected, the new code is little bit faster than the original one without this patch. The overall performance of SWD target (STM32H7A3) RAM download/upload increases from 404/327 to 406/329 KiB/s, by ~0.5 %\n\nThe question is if we need to re-tune `speed_offset`s in tcl/interface/raspberrypi-native.cfg The change looks negligible @ RPi4 but will be\nrelatively bigger on older devices with lower `speed_offset`\n\nI didn\u0027t test JTAG operation. I believe it should be similar as SWD.\n\nGood work!","commit_id":"3cd2b39bf56686e804b10a89d4ad52490fe5214b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"92ef48e518de1d386726dabba94aa9aca82d9c66","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"2a2413d6_49041dbf","updated":"2025-09-24 07:45:57.000000000","message":"Apart for a minor fix below, I\u0027m ok with this version. But I cannot test it, so having another comment would be welcome.\n\nI see space for improving the speed, maybe in a next patch.\nWhile this driver used the generic `adapter gpio` command (which is good to keep as is), it\u0027s clearly not efficient to use the content of `struct adapter_gpio_config` directly during the driver operations.\nIn `bcm2835gpio_init()` the content of `struct adapter_gpio_config` can be converted in a local struct (or even more than one) that contains pre-computed values for offsets, pointers, masks, and whatever else is required at run-time.\nThis would avoid re-computing them at run-time for each pin operation, gaining speed.","commit_id":"9267f2583f763e7991fe855251e39e327fcb07e2"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c3829b2ce0b2c9bf6c8050b911681fada29a07cf","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"f449f395_faeceac8","in_reply_to":"21daf04f_eab2cd04","updated":"2025-09-24 14:37:38.000000000","message":"Yes, I agree. I was so focused on optimizing writes that I completely failed to look at the read functions. I\u0027m willing to also update those code paths in this changeset with similar lookup methods.","commit_id":"9267f2583f763e7991fe855251e39e327fcb07e2"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0fbe5c7717572f0fdb337a48fde5b39b8c23b8a6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"21daf04f_eab2cd04","in_reply_to":"2a2413d6_49041dbf","updated":"2025-09-24 14:08:15.000000000","message":"Antonio, did you notice `struct gpio_control` which is used exactly as you propose in `bcm2835gpio_write()` and `bcm2835gpio_swd_write_fast()`?\nBTW The original `bcm2835gpio_swd_write_fast()` aarch64 code has 23 asm instructions from func start to `bcm2835_gpio_synchronize()`, the code in this change has only 10!\nI admit the input operations `bcm2835gpio_read()` and `bcm2835_swdio_read()` could be optimised better although I would not expect substantial speed up as `bcm2835_swdio_read()` body has 10 instructions only.","commit_id":"9267f2583f763e7991fe855251e39e327fcb07e2"},{"author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"change_message_id":"cc795dc80c5da2115714f8fa95058228484d7e4b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"8a31ee9f_94c02bf9","updated":"2025-11-06 09:04:44.000000000","message":"For almost all practical purposes it\u0027s better to undershoot the adapter speed than to overshoot (`adapter speed` in config files is used to set the maximum speed the part can take in the given state), so that should be the default assumption.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"b1ac6cc2f5c214ef547328e026aac8317e5de78b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"c3bd9b34_f6c7f516","updated":"2025-11-16 01:14:21.000000000","message":"Thanks for helping me get this into its current state, I really appreciate it. Is there anything else I need to do to get this considered for merging?","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e96a9344114e4cd30428e703f6caa07600e5174f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"4399c17c_cf01a0e4","updated":"2025-10-03 16:57:37.000000000","message":"This latest version of the patch makes the following changes:\n\n* Addresses Antonio\u0027s comment about the cast\n* Updates the swdio and jtag read functions to use gpio_control per comment from Tomas\n* Updates the swdio_drive function to also use gpio_control\n\nThe read functions only shave off a single instruction so I doubt there\u0027s any real gain other than to keep things looking consistent.\n\nThe drive function gets a rather large reduction in instructions, nearly 40%. Most of what\u0027s left are branches based on if there\u0027s a pin defined for `ADAPTER_GPIO_IDX_SWDIO_DIR` which is probably an unlikely path and could be optimized later.\n\nThe pin direction toggling in `bcm2835_swdio_drive` does not use the new inline functions and instead uses gpio_control to shave off a read and store when setting the mode to output.\n\nThis is probably the most \"controversial\". I\u0027ve tested this about 100 times (so, really, hundreds of thousands of times) and haven\u0027t had a failure yet. I don\u0027t think I\u0027m widening any opportunity for conflicts between clearing the mode bits to signal mode\u003dinput and setting the low bit to set mode\u003doutput. The previous method to set the mode wasn\u0027t guaranteed to be atomic either so it seemed like an opportunity to remove what looked like unnecessary read and store instructions.\n\nI did some performance testing for both SWD and JTAG for this latest version on our RPi CM3 and RPi 3b+.\n\nJTAG still suffers due to that additional memory store that can\u0027t be combined, but due to the other changes it\u0027s mostly negated. I set the CPU governor to `performance` and averaged 10 runs and the penalty is ~.005% (new 26408400ms vs current 26288880ms)\n\nSWD seems to be slightly faster after these changes by ~.005%\n\nSo, I think we\u0027re largely gaining full pin support \"for free\"","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"6d01a79757fef32f5d0364d2ae52b4b4b1820f85","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"43c850b2_6aff2b02","in_reply_to":"0ec7decd_f5993bec","updated":"2025-11-03 21:25:32.000000000","message":"We found a scope and tested on a RPi CM3 at the current values `bcm2835gpio speed_coeffs 300000 34` and found we were undershooting by quite a bit. We ended up having to adjust the offset to 44 for the bcm2837. I double checked that we tested on the latest version of this changeset (revision 13).\n\nhttps://imgur.com/a/PVlgOtO\n\nWe also tested revision 11 with this offset value and it was pretty bang on... revision 13 does slightly overshoot @ 44. We could maybe tweak it to 43 or 42 but this may undershoot the target value. I don\u0027t know what tolerance we\u0027re aiming for however.\n\nI\u0027m holding off on updating this patch until we get some additional numbers and some ideas on what tolerance we\u0027re looking for in these numbers (value undershooting vs overshooting, etc).\n\nWe could also aim to change these values in a subsequent patch. I\u0027m not sure if it\u0027s more important to get something in that works or to ensure it\u0027s perfect. I know this has been open for a while and it would be nice to get it merged in at some point!","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b26415193a796cc1533418eefbe59dbc580ed958","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"9e36f300_908b7cb0","in_reply_to":"4399c17c_cf01a0e4","updated":"2025-10-03 20:16:01.000000000","message":"\u003e JTAG still suffers due to that additional memory store that can\u0027t be combined, but due to the other changes it\u0027s mostly negated. I set the CPU governor to `performance` and averaged 10 runs and the penalty is ~.005% (new 26408400ms vs current 26288880ms)\n\nDid you mean 0.5% ? This is what I get from the elapsed times.\n\n\u003e SWD seems to be slightly faster after these changes by ~.005%\n\nIf this should be also 0.5%, it\u0027s same what I get with the previous patch set.\n\n\u003e So, I think we\u0027re largely gaining full pin support \"for free\"\n\nYes, good work.\nI will re-test timing on RPi4 and some old slow RPi (1 or 2)\nand decide if we can leave the timing coefs as they are.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1bc071528564df487d7bad687f37075fa35cdbde","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"ac0aff05_6bc10fa3","in_reply_to":"43c850b2_6aff2b02","updated":"2025-11-04 15:17:18.000000000","message":"To be clear, I can certainly update the value for the bcm2837 if those captures look good enough, but we do not have the hardware to capture numbers on other platforms, so would need someone to contribute those values or submit a patch subsequently.\n\nWith the current in-tree values, the clocks look like so https://imgur.com/a/FzcmDUD\n\nAlso, the offset value calculated was only for JTAG operations. We did not capture SWD. I\u0027m not sure the delay would necessarily be equivalent between the two transports and it probably wouldn\u0027t be equivalent between the generic path and the fast path for SWD so I think there may need to be tuning for users regardless depending on transport method and pin configuration.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"ad4493a4eab9029f5265035327d7d8573929c6f0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"a4a191a5_b8c6a168","in_reply_to":"5b98ff5f_ac44a44b","updated":"2025-10-13 19:22:39.000000000","message":"Tomas, just want to check if you\u0027ve had a chance to verify these timings.\n\nThanks","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"8aa7f88affb13fe2dd1b2afc8ccfeaf6f5ae69a5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"775f03ec_7e760e03","in_reply_to":"73c67b02_b2bd8999","updated":"2025-11-10 01:31:54.000000000","message":"Thanks for taking the time to measure. We were able to get some SWD captures at the end of last week I believe, i will look at the numbers and see if there was any need to adjust the values significantly.\n\nI imagine the SWD fast path is the transport we should be tuning for since other paths will be slower just due to the number of memory stores and path inefficiencies.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"7dbe2523ced875ee8f8bee251ed4407119e3d829","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"5b98ff5f_ac44a44b","in_reply_to":"9e36f300_908b7cb0","updated":"2025-10-03 20:42:04.000000000","message":"I probably forgot to multiply by 100, so 0.5% is probably accurate, but double checking my measurements would be appreciated.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"bdcc66accf3d700812e720ae4ebf626b604e268d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"0ec7decd_f5993bec","in_reply_to":"a4a191a5_b8c6a168","updated":"2025-10-13 19:52:36.000000000","message":"Not yet, sorry.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ac5e9c20770360e96b7e133051785e7df180f778","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"73c67b02_b2bd8999","in_reply_to":"ac0aff05_6bc10fa3","updated":"2025-11-10 00:57:11.000000000","message":"Vincent,\nI found a significant overshot on RPi2 (fast path SWD) - speed_offset should be adjusted from 36 to 25. I assume RPi1 will overshot similarly. I\u0027ll prepare a separate patch for speed corrections.","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"30b96c8c3e39c4fc2082e495706abe4f096ed532","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"47758387_8c752f85","in_reply_to":"c3bd9b34_f6c7f516","updated":"2025-11-16 11:02:28.000000000","message":"No, just wait a week. Thank you for good contribution!","commit_id":"0163f756dbf8f288bd278fd03b89a6513416f4a6"}],"configure.ac":[{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"927ed017148198cb6076f608a2367d3fb8e7778b","unresolved":true,"context_lines":[{"line_number":308,"context_line":"  ],"},{"line_number":309,"context_line":"  ["},{"line_number":310,"context_line":"    build_bcm2835gpio\u003dno"},{"line_number":311,"context_line":"    bcm2835gpio_all_gpio\u003dno"},{"line_number":312,"context_line":"    build_imx_gpio\u003dno"},{"line_number":313,"context_line":"    build_am335xgpio\u003dno"},{"line_number":314,"context_line":"])"}],"source_content_type":"application/octet-stream","patch_set":4,"id":"fa031e1f_f7dd1112","line":311,"updated":"2023-08-18 13:04:26.000000000","message":"it\u0027s a nit, but I\u0027d use the same naming style as the rest of this list...","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"5d11bc7605f056c58e700d2b7453483708554c71","unresolved":false,"context_lines":[{"line_number":308,"context_line":"  ],"},{"line_number":309,"context_line":"  ["},{"line_number":310,"context_line":"    build_bcm2835gpio\u003dno"},{"line_number":311,"context_line":"    bcm2835gpio_all_gpio\u003dno"},{"line_number":312,"context_line":"    build_imx_gpio\u003dno"},{"line_number":313,"context_line":"    build_am335xgpio\u003dno"},{"line_number":314,"context_line":"])"}],"source_content_type":"application/octet-stream","patch_set":4,"id":"0f0583ff_b926c537","line":311,"in_reply_to":"be7dcc7b_cb8730f2","updated":"2024-01-18 14:27:29.000000000","message":"Ack","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"a6d29fe9999bbed58afe155b00ca1f307ac03b80","unresolved":true,"context_lines":[{"line_number":308,"context_line":"  ],"},{"line_number":309,"context_line":"  ["},{"line_number":310,"context_line":"    build_bcm2835gpio\u003dno"},{"line_number":311,"context_line":"    bcm2835gpio_all_gpio\u003dno"},{"line_number":312,"context_line":"    build_imx_gpio\u003dno"},{"line_number":313,"context_line":"    build_am335xgpio\u003dno"},{"line_number":314,"context_line":"])"}],"source_content_type":"application/octet-stream","patch_set":4,"id":"be7dcc7b_cb8730f2","line":311,"in_reply_to":"fa031e1f_f7dd1112","updated":"2023-09-13 19:45:58.000000000","message":"Should no longer be an issue","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"}],"doc/openocd.texi":[{"author":{"_account_id":1000859,"name":"Karl Palsson","email":"karlp@tweak.au","username":"karlp"},"change_message_id":"927ed017148198cb6076f608a2367d3fb8e7778b","unresolved":true,"context_lines":[{"line_number":3289,"context_line":"peripherals\u0027 kernel drivers. The driver restores the previous"},{"line_number":3290,"context_line":"configuration on exit."},{"line_number":3291,"context_line":""},{"line_number":3292,"context_line":"GPIO configuration is handled by the generic command"},{"line_number":3293,"context_line":"@ref{adapter gpio, @command{adapter gpio}}."},{"line_number":3294,"context_line":""},{"line_number":3295,"context_line":"See @file{interface/raspberrypi-native.cfg} for a sample config and"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"310a986b_d8440a45","line":3292,"updated":"2023-08-18 13:04:26.000000000","message":"You should probably not just _drop_ this, but mention that you need to enable a special configure option to enable them.","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"a6d29fe9999bbed58afe155b00ca1f307ac03b80","unresolved":true,"context_lines":[{"line_number":3289,"context_line":"peripherals\u0027 kernel drivers. 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The driver restores the previous"},{"line_number":3290,"context_line":"configuration on exit."},{"line_number":3291,"context_line":""},{"line_number":3292,"context_line":"GPIO configuration is handled by the generic command"},{"line_number":3293,"context_line":"@ref{adapter gpio, @command{adapter gpio}}."},{"line_number":3294,"context_line":""},{"line_number":3295,"context_line":"See @file{interface/raspberrypi-native.cfg} for a sample config and"}],"source_content_type":"text/x-texinfo","patch_set":4,"id":"9f8e9d9f_e93e928a","line":3292,"in_reply_to":"583ef085_fe547368","updated":"2024-01-18 14:27:29.000000000","message":"Ack","commit_id":"d68783be776d7fa7ba812f0b59d329cbe886110c"}],"src/jtag/drivers/bcm2835gpio.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9d75fe74959302e48f54643e4d93c40e7bdb4512","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"733afd36_b1aaad7a","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"updated":"2024-01-19 12:47:19.000000000","message":"Lot of changes unrelated to the topic","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1abbfa0094ac99657151a84ada65d51490e9ff22","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"304d62f1_d2fbc128","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"203e6933_313223af","updated":"2024-01-26 23:40:28.000000000","message":"Tomas, just to be clear, are you asking that I drop all changes for the pads or should they be kept in? I\u0027m willing to do either, so please let me know your preference.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4f0ddacc47038308358b4deb96c93d7b3b1cee33","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"59b84dd6_106e007a","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"304d62f1_d2fbc128","updated":"2024-01-27 06:54:46.000000000","message":"Please keep pad related code as is in this patch, just add the comment to the code and/or commit message. Let\u0027s address it later, in separate patch","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":false,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4add2260_9bf44ff0","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"39a3959f_40dc0b5c","updated":"2024-02-08 07:22:26.000000000","message":"Done","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"aab3170ae0d391aea011e13df6e790c60a38dc10","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"203e6933_313223af","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"3dfdfae6_18d58d36","updated":"2024-01-26 19:10:18.000000000","message":"Yup, I wrote the comment. I hoped RPi guys would extend raspi-gpio or something similar. AFAIK there is no utility to handle pad settings.\n\nDoing so in OpenOCD imposes two problems:\n- pad setting requires /dev/mem access \u003d big security risk in a scriptable and network connected app - we discussed it in 7350: jtag/drivers/bcm2835gpio: add peripheral_mem_dev config command | https://review.openocd.org/c/openocd/+/7350\n- if the setting bad influences some other function, user blames OpenOCD\n\nI didn\u0027t notice we were little bit short of pads for supported pins - good catch!","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"32e1b6d5e79236101d1a753b7d56d24e7b499ed0","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"39a3959f_40dc0b5c","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"59b84dd6_106e007a","updated":"2024-02-07 23:13:30.000000000","message":"Should be addressed in the latest version","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e8c5cb2c6ea1ad39d662611a2cb6bde785340d6f","unresolved":true,"context_lines":[{"line_number":29,"context_line":"#define BCM2835_PADS_GPIO_28_45_OFFSET  (0x30 / 4)"},{"line_number":30,"context_line":"#define BCM2835_PADS_GPIO_46_53_OFFSET  (0x34 / 4)"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"#define BCM2835_PADS_GPIO_PASSWORD      (0x5a \u003c\u003c 24)"},{"line_number":33,"context_line":"#define BCM2835_PADS_GPIO_HYST_ENABLED  BIT(3)"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"enum bcm2835_pads_gpio_drv {"},{"line_number":36,"context_line":"\tDRIVE_STRENGTH_2MA,"},{"line_number":37,"context_line":"\tDRIVE_STRENGTH_4MA,"},{"line_number":38,"context_line":"\tDRIVE_STRENGTH_6MA,"},{"line_number":39,"context_line":"\tDRIVE_STRENGTH_8MA,"},{"line_number":40,"context_line":"\tDRIVE_STRENGTH_10MA,"},{"line_number":41,"context_line":"\tDRIVE_STRENGTH_12MA,"},{"line_number":42,"context_line":"\tDRIVE_STRENGTH_14MA,"},{"line_number":43,"context_line":"\tDRIVE_STRENGTH_16MA,"},{"line_number":44,"context_line":"};"},{"line_number":45,"context_line":""},{"line_number":46,"context_line":"/* See \"GPIO Function Select Registers (GPFSELn)\" in \"Broadcom BCM2835 ARM Peripherals\" datasheet. */"},{"line_number":47,"context_line":"#define BCM2835_GPIO_MODE_INPUT 0"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"3dfdfae6_18d58d36","line":44,"range":{"start_line":32,"start_character":0,"end_line":44,"end_character":2},"in_reply_to":"733afd36_b1aaad7a","updated":"2024-01-19 18:05:50.000000000","message":"I\u0027m totally willing to drop the pads changes if that is preferred. There\u0027s already a code comment in the driver that the pads configuration needs to be factored out into \"something else\":\n\n```\n/* TODO: move pads config to a separate utility */\n```\n\nIt seemed appropriate, however, that if we were expanding the pins to be used that we would also expand the pad tunings.\n\nIn fact, the original pads code did not account for all the usable pins and only supported the first 28, not the first 32.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9d75fe74959302e48f54643e4d93c40e7bdb4512","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"daedfa2f_24e156b8","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"updated":"2024-01-19 12:47:19.000000000","message":"Not much worse than the original code, but from the performance point of view it looks like an Arduino sketch. Why both address and the GPIO bit is computed at each GPIO change instead of using cached values?","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"32e1b6d5e79236101d1a753b7d56d24e7b499ed0","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"df2d2768_7db01666","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"4a760118_3e630edd","updated":"2024-02-07 23:13:30.000000000","message":"using static inline functions instead of macros","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c672de07c02011275cb56bc06000a20c26839909","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"d0dc25b2_567aa048","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"4b1e843e_2a133d10","updated":"2024-02-05 19:35:44.000000000","message":"I now remember why I couldn\u0027t do this before. Checkpatch complains about gpio_pin_num being used multiple times in the macro\n\n```\nvfazio@vfazio4 /mnt/development/openocd $ ./tools/checkpatch.sh \nCHECK:MACRO_ARG_REUSE: Macro argument reuse \u0027gpio_pin_num\u0027 - possible side-effects?\n#25: FILE: src/jtag/drivers/bcm2835gpio.c:65:\n+#define MODE_GPIO(gpio_pin_num) (BCM2835_GPIO_REG_READ((gpio_pin_num / 10)) \u003e\u003e ((gpio_pin_num % 10) * 3))\n\nCHECK:MACRO_ARG_PRECEDENCE: Macro argument \u0027gpio_pin_num\u0027 may be better as \u0027(gpio_pin_num)\u0027 to avoid precedence issues\n#25: FILE: src/jtag/drivers/bcm2835gpio.c:65:\n+#define MODE_GPIO(gpio_pin_num) (BCM2835_GPIO_REG_READ((gpio_pin_num / 10)) \u003e\u003e ((gpio_pin_num % 10) * 3))\n\n```\n\nIt thinks that the value could be passed in as a `val++` such that multiple expansions in the macro may cause the value to change unexpectedly. When I pushed this ages ago, the Jenkins build failed even though this is not a warning or error despite the message here https://openocd.org/doc-release/doxygen/patchguide.html#checkpatch\n\nSince I needed to store to a temp variable to silence these complaints, I took advantage of it to do the uint32 cast.\n\nI wasn\u0027t sure if it was allowable to add the following without discussion:\nCheckpatch-ignore: MACRO_ARG_REUSE, MACRO_ARG_PRECEDENCE\n\nWould you prefer I add the checkpatch-ignore trailer or continue to do the stash-and-use method that\u0027s currently in place?","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1abbfa0094ac99657151a84ada65d51490e9ff22","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"df1a5bf7_ece40c3b","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"8dbc6365_453e247e","updated":"2024-01-26 23:40:28.000000000","message":"Tomas, I like this idea especially since both paths of SWD are performing two memory writes anyway, the paths can collapse into a single function with the same overhead.\n\nI think I can make this change and also use a similar pattern for the non-bulk JTAG pins, if you\u0027re OK with that:\n\n```\nstatic struct {\n\tuint32_t *swdio_clr_set_addr[2];\n\tuint32_t swdio_mask;\n\tuint32_t *swclk_clr_set_addr[2];\n\tuint32_t swclk_mask;\n\tuint32_t *jtagtdi_clr_set_addr[2];\n\tuint32_t jtagtdi_mask;\n\tuint32_t *jtagtms_clr_set_addr[2];\n\tuint32_t jtagtms_mask;\n\tuint32_t *jtagtck_clr_set_addr[2];\n\tuint32_t jtagtck_mask;\n} gpio_control;\n```\n\n```\nstatic int bcm2835gpio_write(int tck, int tms, int tdi)\n{\n\t*gpio_control.jtagtdi_clr_set_addr[tdi] \u003d gpio_control.jtagtdi_mask;\n\t*gpio_control.jtagtms_clr_set_addr[tms] \u003d gpio_control.jtagtms_mask;\n\t*gpio_control.jtagtck_clr_set_addr[tck] \u003d gpio_control.jtagtck_mask; /* Write clock last */\n\n\tbcm2835_gpio_synchronize();\n\n\tbcm2835_delay();\n\n\treturn ERROR_OK;\n}\n```\n\nOtherwise I can keep this function as-is, just let me know your preference.\n\nI don\u0027t know if there really needs to be a guard for negative numbers in the write functions themselves. We obviously don\u0027t want to incur a performance penalty for every write and, from what I can tell in `src/jtag/drivers/bitbang.c`, we\u0027re pretty strict about the values being fed in as either 0 or 1. Though it may make since to retype this interface to be either an unsigned int or a bool at some point?\n\n\nI\u0027ll be more than happy to submit that int -\u003e unsigned int patch; I\u0027ll try to get to it next week. \n\nHowever, in the interim, I would appreciate your guidance on your preferred format for the macros as there are still places where they are needed, like `set_gpio_value`.\n\nAs I mentioned, the macros are ugly to coerce the gpio number to a uint for division/modulo performance.\n\nIf you want, I can drop the casting song \u0026 dance so the macros look like:\n\n```\n#define GPIO_CLR(gpio_pin_num) BCM2835_GPIO_REG_WRITE((10 + (gpio_pin_num / 32)), (1 \u003c\u003c (gpio_pin_num % 32)))\n```\n\nThis will incur some performance overhead to account for signed ints until I get time to submit the other patch. But once that lands, we get the changes \"for free\" and the macros will not have to be cleaned up.\n\nOnce I get your feedback, I will rework this patch, rebase, and push.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"12b7f5806d0a996712a5c3c9db9ed03d4b5b94cf","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4a760118_3e630edd","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"d0dc25b2_567aa048","updated":"2024-02-05 20:31:47.000000000","message":"You may use a static inline function instead of macros","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e8c5cb2c6ea1ad39d662611a2cb6bde785340d6f","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"e1a574ca_95d9dada","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"daedfa2f_24e156b8","updated":"2024-01-19 18:05:50.000000000","message":"I don\u0027t think using a cached value is going to necessarily be faster.\n\nIn our original v1 patch we did use an array to cache these values (https://github.com/jzarnstorff/openocd/pull/1#discussion_r1157580804) but this incurs memory reads due to array dereferencing which in the best case is a cache hit and in the worst case is a cache miss. Calculating every time sounds expensive, but is actually cheap as it\u0027s just bit shifting register values.\n\nFor the bulk sets/clears\n```\n   617b8:       1ac72021        lsl     w1, w1, w7\n   617bc:       1ac82040        lsl     w0, w2, w8\n   617c0:       2a010000        orr     w0, w0, w1\n   617c4:       b82378c0        str     w0, [x6, x3, lsl #2]\n```\n\nFor the individual sets/clears:\n```\n   616f0:       53057c81        lsr     w1, w4, #5\n   616f4:       1ac42042        lsl     w2, w2, w4\n   616f8:       6b00011f        cmp     w8, w0\n   616fc:       540002c0        b.eq    61754 \u003cbcm2835gpio_swd_write_fast+0xa4\u003e  // b.none\n   61700:       11001c21        add     w1, w1, #0x7\n   61704:       b82178e2        str     w2, [x7, x1, lsl #2]\n\n```\n\nOf course, it\u0027s only this concise because of the uint cast in the macro. The cast informs the compiler that it doesn\u0027t need to be concerned about overflow logic when doing division/modulo operations. This is safe because we\u0027ll never have pins \u003c0 or \u003e53\n\nThis macro could be simplified/made less ugly if I can find the time to submit a patch to change `adapter_gpio_config.gpio_num` to a uint tree-wide. I have it staged locally but work priorities have robbed me of the time to push it for review.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4f0ddacc47038308358b4deb96c93d7b3b1cee33","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4b1e843e_2a133d10","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"df1a5bf7_ece40c3b","updated":"2024-01-27 06:54:46.000000000","message":"\u003e I think I can make this change and also use a similar pattern for the non-bulk JTAG pins, if you\u0027re OK with that:\n\nSure.\nJust please first check the generated assembler code.\nWe might need first put gpio_control to a local variable and then dereference it instead of the direct use of gpio_control to get the best machine code. But I hope the C compiler will do the job.\n\n\u003e Otherwise I can keep this function as-is, just let me know your preference.\n\nThink so.\n\n\u003e I don\u0027t know if there really needs to be a guard for negative numbers in the write functions themselves. We obviously don\u0027t want to incur a performance penalty for every write and, from what I can tell in `src/jtag/drivers/bitbang.c`, we\u0027re pretty strict about the values being fed in as either 0 or 1.\nNo guard, no additional checks\n\n\u003e Though it may make since to retype this interface to be either an unsigned int or a bool at some point?\n\nGreat, in a separate patch please.\nThere is marginal question whether `bool` - the correct type in respect to represented values - but little bit weird to use for indexing the array with (yes I know there no other representation of false/true than 0/1)\nor prefer `unsigned int` for the sake of clean indexing.\n\nI wonder how would the generated asm code differ is we use\n\n```\nif (swdio)\n  *gpio_control.swdio_set_addr \u003d gpio_control.swdio_mask;\nelse\n  *gpio_control.swdio_clr_addr \u003d gpio_control.swdio_mask;\n```\ninstead of indexing. I think the difference will be negligible. Just C code is longer...\n\n\u003e However, in the interim, I would appreciate your guidance on your preferred format for the macros as there are still places where they are needed, like `set_gpio_value`.\n...\n\u003e ```\n\u003e #define GPIO_CLR(gpio_pin_num) BCM2835_GPIO_REG_WRITE((10 + (gpio_pin_num / 32)), (1 \u003c\u003c (gpio_pin_num % 32)))\n\u003e ```\nYes, looks good. Their use in not time critical","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":false,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"3588d543_a1e9e1ba","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"df2d2768_7db01666","updated":"2024-02-08 07:22:26.000000000","message":"Done","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"aab3170ae0d391aea011e13df6e790c60a38dc10","unresolved":true,"context_lines":[{"line_number":89,"context_line":"#define GPIO_SET(gpio_pin_num) \\"},{"line_number":90,"context_line":"\tdo { \\"},{"line_number":91,"context_line":"\t\tuint32_t _tmp \u003d (uint32_t)(gpio_pin_num); \\"},{"line_number":92,"context_line":"\t\tBCM2835_GPIO_REG_WRITE((7 + (_tmp / 32)), (1 \u003c\u003c (_tmp % 32))); \\"},{"line_number":93,"context_line":"\t} while (0)"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":"/* GPCLR[10,11] register clears bits which are 1, ignores bits which are 0 */"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"8dbc6365_453e247e","line":92,"range":{"start_line":92,"start_character":26,"end_line":92,"end_character":62},"in_reply_to":"e1a574ca_95d9dada","updated":"2024-01-26 19:10:18.000000000","message":"\u003e I don\u0027t think using a cached value is going to necessarily be faster.\n\u003e \n\u003e but this incurs memory reads due to array dereferencing which in the best case is a cache hit and in the worst case is a cache miss.\n\nWell even gpio_num and gpio base must be read from some memory.\nI assume that cache miss is possible at the very first bit only.\nIf we prepare all values to a single struct instead of gathering them\nfrom here and there the code must go fast...\n\n\u003e Calculating every time sounds expensive, but is actually cheap as it\u0027s just bit shifting register values.\n\nAgree. Couple of instructions makes negligible difference.\n\nAnyway, I\u0027d like a code like this\n```\nstruct {\n  uint32_t *swdio_clr_set_addr[2];\n  uint32_t swdio_mask;\n  ...\n} gpio_control\n\nstatic int swd_write_fast(int swclk, int swdio)\n{\n  *gpio_control.swdio_clr_set_addr[swdio] \u003d gpio_control.swdio_mask;\n  *gpio_control.swclk_clr_set_addr[swclk] \u003d gpio_control.swclk_mask;\n}\n```\nOf course some care should be taken on _clr_set_addr indexing by signed int.\nAnd we don\u0027t need to distinguish bulk and fast cases.\n\n\u003e This macro could be simplified/made less ugly if I can find the time to submit a patch to change `adapter_gpio_config.gpio_num` to a uint tree-wide.\n\nI afraid gpio_num uses -1 as not set/don\u0027t use special value. However with a macro the same value could be used on unsigned int - looks like a good idea, please submit a patch!","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9d75fe74959302e48f54643e4d93c40e7bdb4512","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"6da9bfd1_2af6ba06","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"updated":"2024-01-19 12:47:19.000000000","message":"Awful hack!","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4f0ddacc47038308358b4deb96c93d7b3b1cee33","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"6bd9db22_a7dfa4e7","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"2f75a726_7314a845","updated":"2024-01-27 06:54:46.000000000","message":"Hmm, I thought we drop the \u0027bulk\u0027 path as the \u0027fast\u0027 path is fast enough. Am I wrong?","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"32e1b6d5e79236101d1a753b7d56d24e7b499ed0","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"849f012d_d942faf2","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"67afbb94_92c6ae82","updated":"2024-02-07 23:13:30.000000000","message":"No timing differences were noticed in SWD, which was largely expected since two stores were happening in this path anyway. I did take this opportunity to remove active low function swapping conditional statement out of the `bcm2835gpio_swd_write_fast` path and now swap the address that\u0027s written to based on this flag as part of setting up the gpio_control struct.\n\nFor JTAG, I added similar support for the active low pin value, just to mirror the SWD path.\n\nThere is a slight performance degradation on the JTAG path, which we expected due to the additional memory store, but it looked to be roughly ~1.6% @ 1MHz so maybe this negligible difference is acceptable considering all pins are now supported.\n\nThe ARM64 assembly for these functions is pretty short compared to their previous versions, which is to be expected as we\u0027re just performing some offset calculations for the struct, dereferencing to get the address and performing a store.\n\n```\n000000000006e8c0 \u003cbcm2835gpio_write\u003e:\n   6e8c0:\tb0001be4 \tadrp\tx4, 3eb000 \u003cusb_in_buffer+0x100\u003e\n   6e8c4:\t913c0084 \tadd\tx4, x4, #0xf00\n   6e8c8:\t91004083 \tadd\tx3, x4, #0x10\n   6e8cc:\t8b22cc62 \tadd\tx2, x3, w2, sxtw #3\n   6e8d0:\t8b21cc61 \tadd\tx1, x3, w1, sxtw #3\n   6e8d4:\t8b20cc60 \tadd\tx0, x3, w0, sxtw #3\n   6e8d8:\tb9405086 \tldr\tw6, [x4, #80]\n   6e8dc:\tf9401845 \tldr\tx5, [x2, #48]\n   6e8e0:\tf9402422 \tldr\tx2, [x1, #72]\n   6e8e4:\tf9403000 \tldr\tx0, [x0, #96]\n   6e8e8:\tb90000a6 \tstr\tw6, [x5]\n   6e8ec:\tb9406885 \tldr\tw5, [x4, #104]\n   6e8f0:\tb9408081 \tldr\tw1, [x4, #128]\n   6e8f4:\tb9000045 \tstr\tw5, [x2]\n   6e8f8:\tb9000001 \tstr\tw1, [x0]\n   6e8fc:\td5033bbf \tdmb\tish\n   6e900:\tb9400881 \tldr\tw1, [x4, #8]\n   6e904:\t340000c1 \tcbz\tw1, 6e91c \u003cbcm2835gpio_write+0x5c\u003e\n   6e908:\t52800000 \tmov\tw0, #0x0                   \t// #0\n   6e90c:\td503201f \tnop\n   6e910:\t11000400 \tadd\tw0, w0, #0x1\n   6e914:\t6b01001f \tcmp\tw0, w1\n   6e918:\t54ffffc1 \tb.ne\t6e910 \u003cbcm2835gpio_write+0x50\u003e  // b.any\n   6e91c:\t52800000 \tmov\tw0, #0x0                   \t// #0\n   6e920:\td65f03c0 \tret\n\n```\n```\n000000000006dc30 \u003cbcm2835gpio_swd_write_fast\u003e:\n   6dc30:\t90001c02 \tadrp\tx2, 3ed000 \u003cusb_in_buffer+0x1d8\u003e\n   6dc34:\t9138a042 \tadd\tx2, x2, #0xe28\n   6dc38:\t91004043 \tadd\tx3, x2, #0x10\n   6dc3c:\t8b20cc60 \tadd\tx0, x3, w0, sxtw #3\n   6dc40:\tb9402044 \tldr\tw4, [x2, #32]\n   6dc44:\tf861d861 \tldr\tx1, [x3, w1, sxtw #3]\n   6dc48:\tf9400c00 \tldr\tx0, [x0, #24]\n   6dc4c:\tb9000024 \tstr\tw4, [x1]\n   6dc50:\tb9403841 \tldr\tw1, [x2, #56]\n   6dc54:\tb9000001 \tstr\tw1, [x0]\n   6dc58:\td5033bbf \tdmb\tish\n   6dc5c:\tb9400841 \tldr\tw1, [x2, #8]\n   6dc60:\t340000a1 \tcbz\tw1, 6dc74 \u003cbcm2835gpio_swd_write_fast+0x44\u003e\n   6dc64:\t52800000 \tmov\tw0, #0x0                   \t// #0\n   6dc68:\t11000400 \tadd\tw0, w0, #0x1\n   6dc6c:\t6b01001f \tcmp\tw0, w1\n   6dc70:\t54ffffc1 \tb.ne\t6dc68 \u003cbcm2835gpio_swd_write_fast+0x38\u003e  // b.any\n   6dc74:\t52800000 \tmov\tw0, #0x0                   \t// #0\n   6dc78:\td65f03c0 \tret\n```\n\nPerformance captures are below and were compared against `4593c75f0` which is the current HEAD of master.\n\n***SWD***\n\n**New**\n```\nroot@rpi-be20e2:~/openocd/tcl# time ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0+dev-01509-g7a0c7ace1-dirty (2024-02-07-16:27)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : [stm32f4x.cpu] Examination succeed\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n3558178 microseconds per iteration\n\nunlock...\n406195 microseconds per iteration\n\nmass_erase...\n8352824 microseconds per iteration\n\nwrite_bank 0...\n3290683 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n** Programming Started **\n** Programming Finished **\n1189681 microseconds per iteration\n\nverify...\n69705 microseconds per iteration\nshutdown command invoked\n\nreal\t0m16.972s\nuser\t0m8.386s\nsys\t0m0.147s\n```\n\n**Previous**\n```\nroot@rpi-be20e2:~/openocd/tcl# time ../src/openocd -f stm32f4_rpi.cfg\nOpen On-Chip Debugger 0.12.0+dev-01509-g4593c75f0-dirty (2024-02-07-16:37)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 997 kHz\nInfo : SWD DPIDR 0x2ba01477\nInfo : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected\nInfo : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints\nInfo : [stm32f4x.cpu] Examination succeed\nInfo : starting gdb server for stm32f4x.cpu on 3333\nInfo : Listening on port 3333 for gdb connections\nInfo : [stm32f4x.cpu] requesting target halt and executing a soft reset\n\nread_bank 0...\nInfo : device id \u003d 0x10006431\nInfo : flash size \u003d 512 KiB\n[stm32f4x.cpu] halted due to breakpoint, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n3607580 microseconds per iteration\n\nunlock...\n405460 microseconds per iteration\n\nmass_erase...\n8237331 microseconds per iteration\n\nwrite_bank 0...\n3353553 microseconds per iteration\n\nprogram...\n[stm32f4x.cpu] halted due to debug-request, current mode: Thread \nxPSR: 0x01000000 pc: 0x080061b8 msp: 0x20000c80\n** Programming Started **\n** Programming Finished **\n1193272 microseconds per iteration\n\nverify...\n69762 microseconds per iteration\nshutdown command invoked\n\nreal\t0m16.971s\nuser\t0m8.495s\nsys\t0m0.156s\n```\n\n***JTAG***\n\n**New**\n```\nroot@rpi-8e5db4:~# ./simpleocd.sh svf Quartus-1.01.a.svf_new \nInitializing GPIO...\nPowering on...\nopenocd_submission\nOpen On-Chip Debugger 0.12.0+dev-01510-g7a0c7ace1 (2024-02-06-15:47)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nBCM2835 GPIO: peripheral_base \u003d 0x3f000000\nBCM2835 GPIO: speed_coeffs \u003d 194938, speed_offset \u003d 48\nadapter speed: 1000 kHz\njtag\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 1000 kHz\nWarn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!\nInfo : JTAG tap: auto0.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : AUTO auto0.tap - use \"jtag newtap auto0 tap -irlen 2 -expected-id 0x031820dd\"\nError: IR capture error at bit 2, saw 0x3ffffffffffffd55 not 0x...3\nWarn : Bypassing JTAG setup events due to errors\nWarn : gdb services need one or more targets defined\nsvf processing file: \"Quartus-1.01.a.svf_new\"\n0%    adapter speed: 1000 kHz\n95%    24220272 microseconds per iteration\nshutdown command invoked\n\nreal\t0m24.249s\nuser\t0m24.102s\nsys\t0m0.100s\nPowering off...\nResetting GPIO...\n```\n\n**Previous**\n```\nroot@rpi-8e5db4:~# ./simpleocd.sh svf Quartus-1.01.a.svf_new \nInitializing GPIO...\nPowering on...\n./openocd/src/openocd\nOpen On-Chip Debugger 0.12.0+dev-01510-g4593c75f0 (2024-02-06-15:57)\nLicensed under GNU GPL v2\nFor bug reports, read\n\thttp://openocd.org/doc/doxygen/bugs.html\nBCM2835 GPIO: peripheral_base \u003d 0x1056964608\nBCM2835 GPIO: speed_coeffs \u003d 194938, speed_offset \u003d 48\nadapter speed: 1000 kHz\njtag\nInfo : BCM2835 GPIO JTAG/SWD bitbang driver\nInfo : clock speed 1000 kHz\nWarn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!\nInfo : JTAG tap: auto0.tap tap/device found: 0x031820dd (mfg: 0x06e (Altera), part: 0x3182, ver: 0x0)\nWarn : AUTO auto0.tap - use \"jtag newtap auto0 tap -irlen 2 -expected-id 0x031820dd\"\nError: IR capture error at bit 2, saw 0x3ffffffffffffd55 not 0x...3\nWarn : Bypassing JTAG setup events due to errors\nWarn : gdb services need one or more targets defined\nsvf processing file: \"Quartus-1.01.a.svf_new\"\n0%    adapter speed: 1000 kHz\n95%    23832662 microseconds per iteration\nshutdown command invoked\n\nreal\t0m23.860s\nuser\t0m23.770s\nsys\t0m0.046s\nPowering off...\nResetting GPIO...\n```","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"a3afabbe90fc4e6bb5632dacccddb73d60af4125","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"67afbb94_92c6ae82","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"6bd9db22_a7dfa4e7","updated":"2024-01-27 12:59:42.000000000","message":"For SWD this is true as the number of memory writes is the same in both paths. \n\nThe only concern will be the JTAG bulk path. There was a 5% speed degradation when using the non-bulk path which can add up when programming large images. \n\nWe will need to get new performance numbers after these changes anyway to see what impact using the \u0027gpio_control\u0027 struct has for both cases. I still have some slight concern about the impact of the array dereferencing, but let\u0027s see what happens. \n\nWe can make a decision once I have the performance data. I\u0027ll try to have one of my engineers work on this next week.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e8c5cb2c6ea1ad39d662611a2cb6bde785340d6f","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"73b03809_bad7f1e9","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"6da9bfd1_2af6ba06","updated":"2024-01-19 18:05:50.000000000","message":"I\u0027m not sure why this is considered a hack. If we\u0027re doing bulk operations, which is the only time this gets called, then all of the pins are either at offset 0 or offset 1, captured here in `bulk_offset` and driven by the user selected pins.\n\nOtherwise I\u0027d have two sets of macros that do essentially the same thing but hardcoded to 8/11 and switch based on `bulk_offset`, which is essentially the same operation but doubles the number of macros and makes the bulk functions less clean.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"aab3170ae0d391aea011e13df6e790c60a38dc10","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"d3d76c52_4dec17b8","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"73b03809_bad7f1e9","updated":"2024-01-26 19:10:18.000000000","message":"The macro hides the use of bulk_offset variable and the code readability sucks.\nOther macros use pio_base but it could be expected from macro name and function. And BTW if you preferred offset computation in GPIO_SET/CLR, why BULK versions differ so much? Just pass either gpio_num too as a parameter...","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":false,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"a9c93855_0fa8dd45","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"849f012d_d942faf2","updated":"2024-02-08 07:22:26.000000000","message":"Done","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"1abbfa0094ac99657151a84ada65d51490e9ff22","unresolved":true,"context_lines":[{"line_number":106,"context_line":"\t\t((BCM2835_GPIO_REG_READ((13 + (_tmp / 32))) \u003e\u003e (_tmp % 32)) \u0026 1); \\"},{"line_number":107,"context_line":"\t})"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":"#define GPIO_BULK_SET(v) BCM2835_GPIO_REG_WRITE(7 + bulk_offset, v)"},{"line_number":110,"context_line":"#define GPIO_BULK_CLR(v) BCM2835_GPIO_REG_WRITE(10 + bulk_offset, v)"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"static int dev_mem_fd;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2f75a726_7314a845","line":109,"range":{"start_line":109,"start_character":52,"end_line":109,"end_character":63},"in_reply_to":"d3d76c52_4dec17b8","updated":"2024-01-26 23:40:28.000000000","message":"Thanks for the clarification! I can rework this to no longer use `bulk_offset` and to take a GPIO pin number as an explicit parameter, no problem.\n\n```\n\t/* pins share the same offset for bulk operations so use TCK for the offset calculation */\n\tGPIO_BULK_SET(adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num, set);\n\tGPIO_BULK_CLR(adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num, clear);\n```\n\nIf you prefer, we could drop this macro altogether maybe...\n\nAs part of initializing `struct gpio_control` we may want something like:\n\n```\n#define GPIO_SET_ADDR(gpio_pin_num) (pio_base + 7 + (gpio_pin_num / 32))\n#define GPIO_CLR_ADDR(gpio_pin_num) (pio_base + 10 + (gpio_pin_num / 32))\n\ngpio_control.swclk_clr_set_addr[0] \u003d GPIO_CLR_ADDR(adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num);\ngpio_control.swclk_clr_set_addr[1] \u003d GPIO_SET_ADDR(adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num);\ngpio_control.swclk_mask \u003d (1 \u003c\u003c adapter_gpio_config[ADAPTER_GPIO_IDX_SWCLK].gpio_num % 32));\n```\n\nin which case the bulk sets could maybe just be:\n\n```\n*GPIO_SET_ADDR(adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num) \u003d set\n*GPIO_CLR_ADDR(adapter_gpio_config[ADAPTER_GPIO_IDX_TCK].gpio_num) \u003d clear\n\n```\n\nI\u0027m open to suggestions.","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9d75fe74959302e48f54643e4d93c40e7bdb4512","unresolved":true,"context_lines":[{"line_number":598,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":599,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_0_27_OFFSET]);"},{"line_number":600,"context_line":""},{"line_number":601,"context_line":"\t\tinitial_drive_strengths[1] \u003d pads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u0026 0x1f;"},{"line_number":602,"context_line":"\t\tLOG_INFO(\"initial gpio [28-45] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":603,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":604,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":605,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":606,"context_line":""},{"line_number":607,"context_line":"\t\tinitial_drive_strengths[2] \u003d pads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u0026 0x1f;"},{"line_number":608,"context_line":"\t\tLOG_INFO(\"initial gpio [46-53] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":609,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":610,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":611,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":612,"context_line":"\t}"},{"line_number":613,"context_line":""},{"line_number":614,"context_line":"\t/* Configure JTAG/SWD signals. Default directions and initial states are handled"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"ee602abe_c7e7714f","line":611,"range":{"start_line":601,"start_character":2,"end_line":611,"end_character":79},"updated":"2024-01-19 12:47:19.000000000","message":"This sets all the pads regardless they are used for JTAG/SWD, for some other custom function or used internally in the RPi board. In the worst case RPi board could totally hang. See the comment on line 578","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4f0ddacc47038308358b4deb96c93d7b3b1cee33","unresolved":false,"context_lines":[{"line_number":598,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":599,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_0_27_OFFSET]);"},{"line_number":600,"context_line":""},{"line_number":601,"context_line":"\t\tinitial_drive_strengths[1] \u003d pads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u0026 0x1f;"},{"line_number":602,"context_line":"\t\tLOG_INFO(\"initial gpio [28-45] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":603,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":604,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":605,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":606,"context_line":""},{"line_number":607,"context_line":"\t\tinitial_drive_strengths[2] \u003d pads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u0026 0x1f;"},{"line_number":608,"context_line":"\t\tLOG_INFO(\"initial gpio [46-53] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":609,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":610,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":611,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":612,"context_line":"\t}"},{"line_number":613,"context_line":""},{"line_number":614,"context_line":"\t/* Configure JTAG/SWD signals. Default directions and initial states are handled"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"fe2abe54_bb3ab0fe","line":611,"range":{"start_line":601,"start_character":2,"end_line":611,"end_character":79},"in_reply_to":"cd61edae_ffba518d","updated":"2024-01-27 06:54:46.000000000","message":"Done","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e8c5cb2c6ea1ad39d662611a2cb6bde785340d6f","unresolved":true,"context_lines":[{"line_number":598,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":599,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_0_27_OFFSET]);"},{"line_number":600,"context_line":""},{"line_number":601,"context_line":"\t\tinitial_drive_strengths[1] \u003d pads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u0026 0x1f;"},{"line_number":602,"context_line":"\t\tLOG_INFO(\"initial gpio [28-45] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":603,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_28_45_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":604,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":605,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_28_45_OFFSET]);"},{"line_number":606,"context_line":""},{"line_number":607,"context_line":"\t\tinitial_drive_strengths[2] \u003d pads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u0026 0x1f;"},{"line_number":608,"context_line":"\t\tLOG_INFO(\"initial gpio [46-53] pads conf %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":609,"context_line":"\t\tpads_base[BCM2835_PADS_GPIO_46_53_OFFSET] \u003d BCM2835_PADS_GPIO_PASSWORD | BCM2835_PADS_GPIO_HYST_ENABLED |"},{"line_number":610,"context_line":"\t\t\t\tDRIVE_STRENGTH_4MA;"},{"line_number":611,"context_line":"\t\tLOG_INFO(\"pads conf set to %08x\", pads_base[BCM2835_PADS_GPIO_46_53_OFFSET]);"},{"line_number":612,"context_line":"\t}"},{"line_number":613,"context_line":""},{"line_number":614,"context_line":"\t/* Configure JTAG/SWD signals. Default directions and initial states are handled"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"cd61edae_ffba518d","line":611,"range":{"start_line":601,"start_character":2,"end_line":611,"end_character":79},"in_reply_to":"ee602abe_c7e7714f","updated":"2024-01-19 18:05:50.000000000","message":"See my previous comment about the pads settings","commit_id":"d19b88a9375d22b419f26259b535e8b808ceae96"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":true,"context_lines":[{"line_number":58,"context_line":"static const struct adapter_gpio_config *adapter_gpio_config;"},{"line_number":59,"context_line":"static struct initial_gpio_state {"},{"line_number":60,"context_line":"\tunsigned int mode;"},{"line_number":61,"context_line":"\tunsigned int output_level;"},{"line_number":62,"context_line":"} initial_gpio_state[ADAPTER_GPIO_IDX_NUM];"},{"line_number":63,"context_line":"static uint32_t initial_drive_strength_etc;"},{"line_number":64,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"830d4bd7_27b435b9","line":61,"range":{"start_line":61,"start_character":1,"end_line":61,"end_character":13},"updated":"2024-02-08 07:22:26.000000000","message":"See comment on line 85 first.\n\nIf you change get_level() result type this will follow it.","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":58,"context_line":"static const struct adapter_gpio_config *adapter_gpio_config;"},{"line_number":59,"context_line":"static struct initial_gpio_state {"},{"line_number":60,"context_line":"\tunsigned int mode;"},{"line_number":61,"context_line":"\tunsigned int output_level;"},{"line_number":62,"context_line":"} initial_gpio_state[ADAPTER_GPIO_IDX_NUM];"},{"line_number":63,"context_line":"static uint32_t initial_drive_strength_etc;"},{"line_number":64,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"a7833d37_e32d9b01","line":61,"range":{"start_line":61,"start_character":1,"end_line":61,"end_character":13},"in_reply_to":"830d4bd7_27b435b9","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":true,"context_lines":[{"line_number":81,"context_line":"\treturn (BCM2835_GPIO_REG_READ((gpio_pin_num / 10)) \u003e\u003e ((gpio_pin_num % 10) * 3) \u0026 7);"},{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"0b67840c_f2630e1e","line":84,"range":{"start_line":84,"start_character":9,"end_line":84,"end_character":14},"updated":"2024-02-08 07:22:26.000000000","message":"A copy\u0026pasta error?","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c36f964450a927b19be801a671b428930e85dd4c","unresolved":true,"context_lines":[{"line_number":81,"context_line":"\treturn (BCM2835_GPIO_REG_READ((gpio_pin_num / 10)) \u003e\u003e ((gpio_pin_num % 10) * 3) \u0026 7);"},{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"64774fcd_2ac6dc6b","line":84,"range":{"start_line":84,"start_character":9,"end_line":84,"end_character":14},"in_reply_to":"0b67840c_f2630e1e","updated":"2024-02-08 15:32:44.000000000","message":"Yep, nice catch. Sorry for the mess. Fixed this reference.","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":81,"context_line":"\treturn (BCM2835_GPIO_REG_READ((gpio_pin_num / 10)) \u003e\u003e ((gpio_pin_num % 10) * 3) \u0026 7);"},{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"fef9ed50_6e22c2fe","line":84,"range":{"start_line":84,"start_character":9,"end_line":84,"end_character":14},"in_reply_to":"64774fcd_2ac6dc6b","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":true,"context_lines":[{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"},{"line_number":88,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"9d1c0fee_1df1e15a","line":85,"range":{"start_line":85,"start_character":14,"end_line":85,"end_character":26},"updated":"2024-02-08 07:22:26.000000000","message":"Did you consider using bool type for get_level?\nI hope it should not complicate the resulting machine code","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"},{"line_number":88,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"a0afe9c2_756e73bf","line":85,"range":{"start_line":85,"start_character":14,"end_line":85,"end_character":26},"in_reply_to":"4814c900_5d6cc186","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"c36f964450a927b19be801a671b428930e85dd4c","unresolved":true,"context_lines":[{"line_number":82,"context_line":"}"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"/* GPLEV[10,11], current level of the pin */"},{"line_number":85,"context_line":"static inline unsigned int bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn ((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"},{"line_number":88,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"4814c900_5d6cc186","line":85,"range":{"start_line":85,"start_character":14,"end_line":85,"end_character":26},"in_reply_to":"9d1c0fee_1df1e15a","updated":"2024-02-08 15:32:44.000000000","message":"I didn\u0027t, but since we\u0027re introducing a typed function, it seems reasonable to type it like we expect so I\u0027ve done that. I don\u0027t think this causes any problems with the generated assembly\n\n\n```\n000000000006dad4 \u003cbcm2835_swdio_read\u003e:\n   6dad4:\td0001c00 \tadrp\tx0, 3ef000 \u003cusb_in_buffer+0x1d8\u003e\n   6dad8:\tf0001b21 \tadrp\tx1, 3d4000 \u003cmemcpy@GLIBC_2.17\u003e\n   6dadc:\tf9471400 \tldr\tx0, [x0, #3624]\n   6dae0:\tf9456824 \tldr\tx4, [x1, #2768]\n   6dae4:\tb9407802 \tldr\tw2, [x0, #120]\n   6dae8:\t39422003 \tldrb\tw3, [x0, #136]\n   6daec:\t53057c41 \tlsr\tw1, w2, #5\n   6daf0:\t11003421 \tadd\tw1, w1, #0xd\n   6daf4:\tb8617880 \tldr\tw0, [x4, x1, lsl #2]\n   6daf8:\t1ac22400 \tlsr\tw0, w0, w2\n   6dafc:\t12000000 \tand\tw0, w0, #0x1\n   6db00:\t4a000060 \teor\tw0, w3, w0\n   6db04:\td65f03c0 \tret\n\n```","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":true,"context_lines":[{"line_number":234,"context_line":""},{"line_number":235,"context_line":"static bb_value_t bcm2835gpio_read(void)"},{"line_number":236,"context_line":"{"},{"line_number":237,"context_line":"\tuint32_t value \u003d (uint32_t)bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].gpio_num);"},{"line_number":238,"context_line":"\treturn value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].active_low ? BB_HIGH : BB_LOW);"},{"line_number":239,"context_line":""},{"line_number":240,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"32b2c15a_a69786e6","line":237,"range":{"start_line":237,"start_character":1,"end_line":237,"end_character":9},"updated":"2024-02-08 07:22:26.000000000","message":"With bool get_level() we can simplify:\n```\nbool level \u003d get_level();\nreturn (level ^ active_low) ? BB_HIGH : BB_LOW;\n```\n\nAlso note that round brackets are misplaced in the old code (fortunately it works anyway)","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":234,"context_line":""},{"line_number":235,"context_line":"static bb_value_t bcm2835gpio_read(void)"},{"line_number":236,"context_line":"{"},{"line_number":237,"context_line":"\tuint32_t value \u003d (uint32_t)bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].gpio_num);"},{"line_number":238,"context_line":"\treturn value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_TDO].active_low ? BB_HIGH : BB_LOW);"},{"line_number":239,"context_line":""},{"line_number":240,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"cac2ea18_0944e987","line":237,"range":{"start_line":237,"start_character":1,"end_line":237,"end_character":9},"in_reply_to":"32b2c15a_a69786e6","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"857df0de176325e8d5e8b20d91c0e91206b2c99b","unresolved":true,"context_lines":[{"line_number":312,"context_line":""},{"line_number":313,"context_line":"static int bcm2835_swdio_read(void)"},{"line_number":314,"context_line":"{"},{"line_number":315,"context_line":"\tuint32_t value \u003d bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);"},{"line_number":316,"context_line":"\treturn value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0);"},{"line_number":317,"context_line":"}"},{"line_number":318,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"9ef10fde_a439b3e2","line":315,"updated":"2024-02-08 07:22:26.000000000","message":"With bool get_level():\n```\nbool level \u003d get_level();\nreturn (int)(level ^ active_low);\n```","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":312,"context_line":""},{"line_number":313,"context_line":"static int bcm2835_swdio_read(void)"},{"line_number":314,"context_line":"{"},{"line_number":315,"context_line":"\tuint32_t value \u003d bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);"},{"line_number":316,"context_line":"\treturn value ^ (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low ? 1 : 0);"},{"line_number":317,"context_line":"}"},{"line_number":318,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"5459fd3b_78356c22","line":315,"in_reply_to":"9ef10fde_a439b3e2","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"7a0c7ace107e9c62af2ede524659c91549f469af"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"07c3479582a73e363b5f6f6184cbf12d7cfa7bb2","unresolved":true,"context_lines":[{"line_number":313,"context_line":"static int bcm2835_swdio_read(void)"},{"line_number":314,"context_line":"{"},{"line_number":315,"context_line":"\tbool value \u003d bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);"},{"line_number":316,"context_line":"\treturn (int)(value ^ adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low);"},{"line_number":317,"context_line":"}"},{"line_number":318,"context_line":""},{"line_number":319,"context_line":"static int bcm2835gpio_khz(int khz, int *jtag_speed)"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"0853a706_8950c997","line":316,"updated":"2024-02-24 23:11:10.000000000","message":"NO CAST to convert a bool to int\nreturn (bolean value) ? 1 : 0;","commit_id":"64052969f46e411b40e23e59f4dc8f0cea7965d7"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"4d28db6d26442b8d37805dafdbb1ff912b34824d","unresolved":true,"context_lines":[{"line_number":313,"context_line":"static int bcm2835_swdio_read(void)"},{"line_number":314,"context_line":"{"},{"line_number":315,"context_line":"\tbool value \u003d bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);"},{"line_number":316,"context_line":"\treturn (int)(value ^ adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low);"},{"line_number":317,"context_line":"}"},{"line_number":318,"context_line":""},{"line_number":319,"context_line":"static int bcm2835gpio_khz(int khz, int *jtag_speed)"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"65a5df30_13a8dedb","line":316,"in_reply_to":"0853a706_8950c997","updated":"2024-02-24 23:44:01.000000000","message":"updated","commit_id":"64052969f46e411b40e23e59f4dc8f0cea7965d7"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"3e2198a94c170714536afaec7df18f27f34c690e","unresolved":false,"context_lines":[{"line_number":313,"context_line":"static int bcm2835_swdio_read(void)"},{"line_number":314,"context_line":"{"},{"line_number":315,"context_line":"\tbool value \u003d bcm2835_get_level(adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num);"},{"line_number":316,"context_line":"\treturn (int)(value ^ adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].active_low);"},{"line_number":317,"context_line":"}"},{"line_number":318,"context_line":""},{"line_number":319,"context_line":"static int bcm2835gpio_khz(int khz, int *jtag_speed)"}],"source_content_type":"text/x-csrc","patch_set":9,"id":"af060e40_dbfedba2","line":316,"in_reply_to":"65a5df30_13a8dedb","updated":"2025-08-15 01:07:48.000000000","message":"Done","commit_id":"64052969f46e411b40e23e59f4dc8f0cea7965d7"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"92ef48e518de1d386726dabba94aa9aca82d9c66","unresolved":true,"context_lines":[{"line_number":84,"context_line":"/* GPLEV[13,14], current level of the pin */"},{"line_number":85,"context_line":"static inline bool bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn (bool)((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"},{"line_number":88,"context_line":"}"},{"line_number":89,"context_line":""},{"line_number":90,"context_line":"/* set GPIO pin as input */"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"63fe88cc_f1d67293","line":87,"updated":"2025-09-24 07:45:57.000000000","message":"No need for the cast, as it\u0027s done by the prototype of the function.","commit_id":"9267f2583f763e7991fe855251e39e327fcb07e2"},{"author":{"_account_id":1002139,"name":"Vincent Fazio","email":"vfazio@gmail.com","username":"vfazio"},"change_message_id":"e96a9344114e4cd30428e703f6caa07600e5174f","unresolved":false,"context_lines":[{"line_number":84,"context_line":"/* GPLEV[13,14], current level of the pin */"},{"line_number":85,"context_line":"static inline bool bcm2835_get_level(unsigned int gpio_pin_num)"},{"line_number":86,"context_line":"{"},{"line_number":87,"context_line":"\treturn (bool)((BCM2835_GPIO_REG_READ((13 + (gpio_pin_num / 32))) \u003e\u003e (gpio_pin_num % 32)) \u0026 1);"},{"line_number":88,"context_line":"}"},{"line_number":89,"context_line":""},{"line_number":90,"context_line":"/* set GPIO pin as input */"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"a77fd66d_c8c9f500","line":87,"in_reply_to":"63fe88cc_f1d67293","updated":"2025-10-03 16:57:37.000000000","message":"Done","commit_id":"9267f2583f763e7991fe855251e39e327fcb07e2"}]}