)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9ea08e4b399c3cffbadad54b8cea98d2c439aba6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"b8831459_ec818696","updated":"2023-08-26 12:55:34.000000000","message":"I think we can merge this as-is.\n\nBut I\u0027m questioning myself:\nDEVARCH[0:15] is the ARCHID that for DTW is 0x1A02 (see: https://review.openocd.org/c/openocd/+/7800/3/src/target/arm_adi_v5.c#917)\nDEVARCH[16:19] is the revision\nDEVARCH[20] must be 1 if DEVARCH is present\nDEVARCH[21-31] is JEP106 ID of architect (0x23b for ARM)\n\nOld Cortex-M have old DTW without DEVARCH register (no CoreSight compatible) so read it is zero.\nNew Cortex-M have CoreSight compatible DTW with, so far, revision 0 and 1.\n\nShould we instead mask away revision and check\n(DEVARCH \u0026 0xfff0ffff) \u003d\u003d 0x47701A02 ?","commit_id":"4b0a65ee749f3e7951b5744c8ea19ddaddce66b9"},{"author":{"_account_id":1000863,"name":"Tarek BOCHKATI","email":"tarek.bouchkati@gmail.com","username":"BouchkatiTarek"},"change_message_id":"16f66b6d848e5efc39746349d6da7bb12627a3c3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"ef887fe9_3f98af48","updated":"2023-08-24 13:11:36.000000000","message":"tested OK.","commit_id":"4b0a65ee749f3e7951b5744c8ea19ddaddce66b9"}]}