)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"ac557c5982de26594c351dcbfbd0570f0928e7e6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"720049e9_048734a7","updated":"2023-09-22 06:42:08.000000000","message":"I have added detections for Lexra and MIPSr1, the code should work on both situations now.","commit_id":"fc6aea67d1d5b135fe11f31b87eeab74eacb688a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4e16df65638a261c24140f1eb1a8838794675acc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":24,"id":"2c3e8310_9244bfad","updated":"2023-12-28 14:15:35.000000000","message":"Again minor nitty-picky comments.\nThanks for your effort with this long series","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"62beba6885c84f4059b9f00d7c6efa6d096b89af","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":24,"id":"e8354e52_7df5f6d1","updated":"2023-12-25 07:17:35.000000000","message":"Hi, I just noticed this patch caused a checkpatch error on mingw build... The error has been addressed now, so the this patch and 3 other patches should be ready for submit, please let me know if there still are codes that need fixing, thanks!","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"95cac684d7dc595affbca03fc1594ba51aff710f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":25,"id":"7f8cd952_49a60095","updated":"2023-12-29 09:22:48.000000000","message":"No problem! Thanks for helping me getting this patch chain through, too! btw happy new year :D","commit_id":"0aa66aea36221bc512ffe47acec8564970657d8d"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"7eba1ad1f2d33129a37450a60eaaea14f4aee639","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":25,"id":"15de3c03_dd446794","in_reply_to":"7f8cd952_49a60095","updated":"2023-12-29 10:18:40.000000000","message":"Thanks to you for your effort in improving OpenOCD support for MIPS. This CPU arch is going to disappear from new devices, but there are still plenty of legacy devices around.\nHappy new year!","commit_id":"0aa66aea36221bc512ffe47acec8564970657d8d"}],"src/target/mips32.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4e16df65638a261c24140f1eb1a8838794675acc","unresolved":true,"context_lines":[{"line_number":796,"context_line":"\treturn \u0026mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];"},{"line_number":797,"context_line":"}"},{"line_number":798,"context_line":""},{"line_number":799,"context_line":"bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)"},{"line_number":800,"context_line":"{"},{"line_number":801,"context_line":"\treturn (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":802,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"ba05f7a4_ddfef15d","line":799,"updated":"2023-12-28 14:15:35.000000000","message":"This function and next mips32_cpu_get_release() are only used in this file.\nThey should be declared as static and removed from the file.h\nOr do you plan to use them in a following patch of this series? (I haven\u0027t check them yet)","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"95cac684d7dc595affbca03fc1594ba51aff710f","unresolved":false,"context_lines":[{"line_number":796,"context_line":"\treturn \u0026mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];"},{"line_number":797,"context_line":"}"},{"line_number":798,"context_line":""},{"line_number":799,"context_line":"bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)"},{"line_number":800,"context_line":"{"},{"line_number":801,"context_line":"\treturn (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":802,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"7b1ca15b_c13e5614","line":799,"in_reply_to":"ba05f7a4_ddfef15d","updated":"2023-12-29 09:22:48.000000000","message":"There was some usage in other files, but not after they are wrapped by `mips32_cpu_support_*` functions. Thanks for pointing out!","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"}],"src/target/mips32.h":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4e16df65638a261c24140f1eb1a8838794675acc","unresolved":true,"context_lines":[{"line_number":454,"context_line":"#define MIPS32_OP_BEQ\t0x04u"},{"line_number":455,"context_line":"#define MIPS32_OP_BGTZ\t0x07u"},{"line_number":456,"context_line":"#define MIPS32_OP_BNE\t0x05u"},{"line_number":457,"context_line":"#define MIPS32_OP_ADD 0x20u"},{"line_number":458,"context_line":"#define MIPS32_OP_ADDI\t0x08u"},{"line_number":459,"context_line":"#define MIPS32_OP_AND\t0x24u"},{"line_number":460,"context_line":"#define MIPS32_OP_CACHE\t0x2Fu"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"81833dc7_47fcea56","line":457,"updated":"2023-12-28 14:15:35.000000000","message":"Please use between macro name and value, so it get aligned with the other macros above and below","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"95cac684d7dc595affbca03fc1594ba51aff710f","unresolved":false,"context_lines":[{"line_number":454,"context_line":"#define MIPS32_OP_BEQ\t0x04u"},{"line_number":455,"context_line":"#define MIPS32_OP_BGTZ\t0x07u"},{"line_number":456,"context_line":"#define MIPS32_OP_BNE\t0x05u"},{"line_number":457,"context_line":"#define MIPS32_OP_ADD 0x20u"},{"line_number":458,"context_line":"#define MIPS32_OP_ADDI\t0x08u"},{"line_number":459,"context_line":"#define MIPS32_OP_AND\t0x24u"},{"line_number":460,"context_line":"#define MIPS32_OP_CACHE\t0x2Fu"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"e3baf737_fb3cbbea","line":457,"in_reply_to":"81833dc7_47fcea56","updated":"2023-12-29 09:22:48.000000000","message":"Done","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"4e16df65638a261c24140f1eb1a8838794675acc","unresolved":true,"context_lines":[{"line_number":573,"context_line":"#define MIPS16_ISA_SDBBP\t\t\t0xE801u"},{"line_number":574,"context_line":""},{"line_number":575,"context_line":"/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */"},{"line_number":576,"context_line":"#define MMIPS32_POOL32A\t\t\t\t\t0X00u"},{"line_number":577,"context_line":"#define MMIPS32_POOL32F\t\t\t\t\t0X15u"},{"line_number":578,"context_line":"#define MMIPS32_POOL32FXF\t\t\t\t0x3Bu"},{"line_number":579,"context_line":"#define MMIPS32_POOL32AXF\t\t\t\t0x3Cu"},{"line_number":580,"context_line":"#define MMIPS32_POOL32B\t\t\t\t\t0x08u"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"b13b42bb_9af9a615","line":577,"range":{"start_line":576,"start_character":8,"end_line":577,"end_character":33},"updated":"2023-12-28 14:15:35.000000000","message":"This whole file (apart the modified line 576) use \u00270x\u0027 with lowercase \u0027x\u0027.\nplease keep consistency and use \u00270x\u0027","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"95cac684d7dc595affbca03fc1594ba51aff710f","unresolved":false,"context_lines":[{"line_number":573,"context_line":"#define MIPS16_ISA_SDBBP\t\t\t0xE801u"},{"line_number":574,"context_line":""},{"line_number":575,"context_line":"/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */"},{"line_number":576,"context_line":"#define MMIPS32_POOL32A\t\t\t\t\t0X00u"},{"line_number":577,"context_line":"#define MMIPS32_POOL32F\t\t\t\t\t0X15u"},{"line_number":578,"context_line":"#define MMIPS32_POOL32FXF\t\t\t\t0x3Bu"},{"line_number":579,"context_line":"#define MMIPS32_POOL32AXF\t\t\t\t0x3Cu"},{"line_number":580,"context_line":"#define MMIPS32_POOL32B\t\t\t\t\t0x08u"}],"source_content_type":"text/x-csrc","patch_set":24,"id":"9ddf19e5_080a7104","line":577,"range":{"start_line":576,"start_character":8,"end_line":577,"end_character":33},"in_reply_to":"b13b42bb_9af9a615","updated":"2023-12-29 09:22:48.000000000","message":"Done","commit_id":"07f49a784125d895965a73fc1d6faa3c6d7c45a8"}],"src/target/mips32_pracc.c":[{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"bd13ad2a55ec0c7d480c479b9f01c4b922c31bf7","unresolved":true,"context_lines":[{"line_number":452,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR));\t/* $15 \u003d MIPS32_PRACC_BASE_ADDR */"},{"line_number":453,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load  $8 with modified upper addr */"},{"line_number":454,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 8));\t\t\t/* lw $8, LOWER16(addr)($8) */"},{"line_number":455,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_SYNC(ctx.isa));"},{"line_number":456,"context_line":"\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT,"},{"line_number":457,"context_line":"\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15));\t/* sw $8,PRACC_OUT_OFFSET($15) */"},{"line_number":458,"context_line":"\tpracc_add_li32(\u0026ctx, 8, ejtag_info-\u003ereg8, 0);\t\t\t\t/* restore $8 */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"8b5a67ba_5f1b6e29","line":455,"updated":"2023-09-15 18:40:07.000000000","message":"SYNC is supported by MIPSr1. Lexra will probably not support it.","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"ac557c5982de26594c351dcbfbd0570f0928e7e6","unresolved":false,"context_lines":[{"line_number":452,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR));\t/* $15 \u003d MIPS32_PRACC_BASE_ADDR */"},{"line_number":453,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load  $8 with modified upper addr */"},{"line_number":454,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 8));\t\t\t/* lw $8, LOWER16(addr)($8) */"},{"line_number":455,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_SYNC(ctx.isa));"},{"line_number":456,"context_line":"\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT,"},{"line_number":457,"context_line":"\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15));\t/* sw $8,PRACC_OUT_OFFSET($15) */"},{"line_number":458,"context_line":"\tpracc_add_li32(\u0026ctx, 8, ejtag_info-\u003ereg8, 0);\t\t\t\t/* restore $8 */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"688c6764_16cfc00e","line":455,"in_reply_to":"8b5a67ba_5f1b6e29","updated":"2023-09-22 06:42:08.000000000","message":"Done","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"bd13ad2a55ec0c7d480c479b9f01c4b922c31bf7","unresolved":true,"context_lines":[{"line_number":552,"context_line":"\tpracc_queue_init(\u0026ctx);"},{"line_number":553,"context_line":""},{"line_number":554,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR));\t/* $15 \u003d MIPS32_PRACC_BASE_ADDR */"},{"line_number":555,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_EHB(ctx.isa));"},{"line_number":556,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MFC0(ctx.isa, 8, cp0_reg, cp0_sel));\t\t/* move cp0 reg / sel to $8 */"},{"line_number":557,"context_line":"\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT,"},{"line_number":558,"context_line":"\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15));\t/* store $8 to pracc_out */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"93639675_36fe305f","line":555,"updated":"2023-09-15 18:40:07.000000000","message":"EHB is not supported by MIPSr1, so it should be executed only on supported CPUs.","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"ac557c5982de26594c351dcbfbd0570f0928e7e6","unresolved":false,"context_lines":[{"line_number":552,"context_line":"\tpracc_queue_init(\u0026ctx);"},{"line_number":553,"context_line":""},{"line_number":554,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR));\t/* $15 \u003d MIPS32_PRACC_BASE_ADDR */"},{"line_number":555,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_EHB(ctx.isa));"},{"line_number":556,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MFC0(ctx.isa, 8, cp0_reg, cp0_sel));\t\t/* move cp0 reg / sel to $8 */"},{"line_number":557,"context_line":"\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT,"},{"line_number":558,"context_line":"\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15));\t/* store $8 to pracc_out */"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"8664cdfb_763436c4","line":555,"in_reply_to":"93639675_36fe305f","updated":"2023-09-22 06:42:08.000000000","message":"Done","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"bd13ad2a55ec0c7d480c479b9f01c4b922c31bf7","unresolved":true,"context_lines":[{"line_number":574,"context_line":"\tpracc_add_li32(\u0026ctx, 15, val, 0);\t\t\t\t/* Load val to $15 */"},{"line_number":575,"context_line":""},{"line_number":576,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MTC0(ctx.isa, 15, cp0_reg, cp0_sel));\t\t/* write $15 to cp0 reg / sel */"},{"line_number":577,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_EHB(ctx.isa));"},{"line_number":578,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) \u003c\u003c ctx.isa)));\t\t/* jump to start */"},{"line_number":579,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0));\t\t\t/* restore $15 from DeSave */"},{"line_number":580,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"9cf1ee9d_936822d1","line":577,"updated":"2023-09-15 18:40:07.000000000","message":"Same here.","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"ac557c5982de26594c351dcbfbd0570f0928e7e6","unresolved":false,"context_lines":[{"line_number":574,"context_line":"\tpracc_add_li32(\u0026ctx, 15, val, 0);\t\t\t\t/* Load val to $15 */"},{"line_number":575,"context_line":""},{"line_number":576,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MTC0(ctx.isa, 15, cp0_reg, cp0_sel));\t\t/* write $15 to cp0 reg / sel */"},{"line_number":577,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_EHB(ctx.isa));"},{"line_number":578,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) \u003c\u003c ctx.isa)));\t\t/* jump to start */"},{"line_number":579,"context_line":"\tpracc_add(\u0026ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0));\t\t\t/* restore $15 from DeSave */"},{"line_number":580,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"b107d187_21bed66c","line":577,"in_reply_to":"9cf1ee9d_936822d1","updated":"2023-09-22 06:42:08.000000000","message":"Done","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"bd13ad2a55ec0c7d480c479b9f01c4b922c31bf7","unresolved":true,"context_lines":[{"line_number":1163,"context_line":""},{"line_number":1164,"context_line":"\t\tMIPS32_LUI(isa, 15, UPPER16(MIPS32_PRACC_TEXT)),"},{"line_number":1165,"context_line":"\t\tMIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_PRACC_TEXT) | isa),\t/* isa bit for JR instr */"},{"line_number":1166,"context_line":"\t\tMIPS32_JRHB(isa, 15),\t\t\t\t\t\t\t\t/* jr start */"},{"line_number":1167,"context_line":"\t\tMIPS32_MFC0(isa, 15, 31, 0),\t\t\t\t\t/* move COP0 DeSave to $15 */"},{"line_number":1168,"context_line":"\t};"},{"line_number":1169,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"04e6507a_3e97774f","line":1166,"updated":"2023-09-15 18:40:07.000000000","message":"jr.hb is not supported on MIPSr1. Should be executed conditionally","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"ac557c5982de26594c351dcbfbd0570f0928e7e6","unresolved":false,"context_lines":[{"line_number":1163,"context_line":""},{"line_number":1164,"context_line":"\t\tMIPS32_LUI(isa, 15, UPPER16(MIPS32_PRACC_TEXT)),"},{"line_number":1165,"context_line":"\t\tMIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_PRACC_TEXT) | isa),\t/* isa bit for JR instr */"},{"line_number":1166,"context_line":"\t\tMIPS32_JRHB(isa, 15),\t\t\t\t\t\t\t\t/* jr start */"},{"line_number":1167,"context_line":"\t\tMIPS32_MFC0(isa, 15, 31, 0),\t\t\t\t\t/* move COP0 DeSave to $15 */"},{"line_number":1168,"context_line":"\t};"},{"line_number":1169,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":4,"id":"198667bf_a13e4214","line":1166,"in_reply_to":"04e6507a_3e97774f","updated":"2023-09-22 06:42:08.000000000","message":"Done","commit_id":"fc5b96d82f0caabf5fb94e2530c798e8fd88ba4c"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"67914576aa9d50b7bf1180981e01cd43adff9dea","unresolved":true,"context_lines":[{"line_number":823,"context_line":"\t * If cacheable we have to synchronize the cache"},{"line_number":824,"context_line":"\t */"},{"line_number":825,"context_line":"\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":826,"context_line":"\tbool is_lexra \u003d (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":827,"context_line":"\tif (cached \u003d\u003d 3 || cached \u003d\u003d 0) {\t\t/* Write back cache or write through cache */"},{"line_number":828,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":829,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"ccb2b080_c1d1e18a","line":826,"updated":"2023-11-17 14:03:46.000000000","message":"please add new functions, something like:\nmips32_cpu_is_lexra()\nmips32_get_release()\nmips32_cpu_support_sync()\nmips32_cpu_support_ehb()","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"d4a1f766c0b5173ab9a3110e41b81d0dae08472b","unresolved":true,"context_lines":[{"line_number":823,"context_line":"\t * If cacheable we have to synchronize the cache"},{"line_number":824,"context_line":"\t */"},{"line_number":825,"context_line":"\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":826,"context_line":"\tbool is_lexra \u003d (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":827,"context_line":"\tif (cached \u003d\u003d 3 || cached \u003d\u003d 0) {\t\t/* Write back cache or write through cache */"},{"line_number":828,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":829,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"f3c1844a_81941693","line":826,"in_reply_to":"5bec9871_71bb3f91","updated":"2023-11-21 07:46:06.000000000","message":"Code Review and Potential Issues: Every line of code, including \"one-liners,\" can be a potential source of problems. These one-liners often translate to multiple CPU instructions, making the argument for simplicity slightly misleading. Ensuring readability and maintainability is as crucial as performance. C offers opportunities to achieve both readable and performant code, and striking the right balance is essential.\n\n    Performance, Code Size, and Cache Utilization: Performance is influenced not just by branching but also by the overall size of the code and its footprint in the CPU cache. Larger blocks of repetitive code can lead to inefficient cache utilization, potentially causing more cache misses and performance degradation. Abstracting repetitive code into functions can reduce the code size and improve cache efficiency.\n\n    Modern Compiler and Processor Capabilities: Modern compilers are adept at optimizing code, particularly for small, frequently used functions. They can inline these functions automatically, eliminating the overhead of a function call. Additionally, modern processors with advanced branch prediction and speculative execution capabilities are less impacted by the additional branches that small functions might introduce.\n\n    Compiler Optimization Techniques: Compilers use various strategies to optimize code at the instruction level, influenced by options like optimizing for size (-Os) or performance (-O2, -O3). Annotating functions with inline hints to the compiler to embed the function\u0027s code at each point of call, reducing overhead and functioning similarly to macros.\n\n    Static Inline Functions for Optimized Performance: Defining functions as static inline in header files allows the compiler to treat them as inlined while maintaining static linkage. This balances the benefits of inlining with the advantages of type safety, debuggability, scope control, and readability offered by functions over macros.\n\n    Advantages of Functions Over Macros: Functions are type-safe and easier to debug than macros. They have defined scope and are less prone to side effects, contributing to better code readability and maintainability.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"fd9ae554d13f25e3a232fa51c8edef4293200136","unresolved":true,"context_lines":[{"line_number":823,"context_line":"\t * If cacheable we have to synchronize the cache"},{"line_number":824,"context_line":"\t */"},{"line_number":825,"context_line":"\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":826,"context_line":"\tbool is_lexra \u003d (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":827,"context_line":"\tif (cached \u003d\u003d 3 || cached \u003d\u003d 0) {\t\t/* Write back cache or write through cache */"},{"line_number":828,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":829,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"5bec9871_71bb3f91","line":826,"in_reply_to":"ccb2b080_c1d1e18a","updated":"2023-11-21 04:16:46.000000000","message":"I don\u0027t think moving some 1liners to separate functions is good for performance, this causes unwanted extra branches and the returned value is not reused if the function is called every time a comparison is needed.\nIn my opinion, `is_lexra` and `rel` could be stored in `mips_ejtag` while others could have more clarifying comments.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"6ccd0bcdd24480e6d62c2dd9480f49c432b5ac22","unresolved":false,"context_lines":[{"line_number":823,"context_line":"\t * If cacheable we have to synchronize the cache"},{"line_number":824,"context_line":"\t */"},{"line_number":825,"context_line":"\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":826,"context_line":"\tbool is_lexra \u003d (ejtag_info-\u003eprid \u0026 PRID_COMP_MASK) \u003d\u003d PRID_COMP_LEXRA;"},{"line_number":827,"context_line":"\tif (cached \u003d\u003d 3 || cached \u003d\u003d 0) {\t\t/* Write back cache or write through cache */"},{"line_number":828,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":829,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"0700262a_8299879f","line":826,"in_reply_to":"f3c1844a_81941693","updated":"2023-11-22 09:50:28.000000000","message":"Thanks for the guidance, I must have mixed up some other language\u0027s performance issue with C.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"67914576aa9d50b7bf1180981e01cd43adff9dea","unresolved":true,"context_lines":[{"line_number":1101,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":1102,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"},{"line_number":1103,"context_line":"\t\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":1104,"context_line":"\t\tif (rel \u003e 1) {"},{"line_number":1105,"context_line":"\t\t\tLOG_DEBUG(\"Unknown release in cache code\");"},{"line_number":1106,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"933d835e_6d7c5c3b","line":1104,"updated":"2023-11-17 14:03:46.000000000","message":"if (rel \u003e MIPS32_RELEASE_2)\n\nCan you please add more comments to describe exact problem here","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"d4a1f766c0b5173ab9a3110e41b81d0dae08472b","unresolved":true,"context_lines":[{"line_number":1101,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":1102,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"},{"line_number":1103,"context_line":"\t\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":1104,"context_line":"\t\tif (rel \u003e 1) {"},{"line_number":1105,"context_line":"\t\t\tLOG_DEBUG(\"Unknown release in cache code\");"},{"line_number":1106,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"9b88bffa_ea1985cf","line":1104,"in_reply_to":"7cabc49f_70690107","updated":"2023-11-21 07:46:06.000000000","message":"No need to solve the problem for now. Just please add comment to explain the problem.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"fd9ae554d13f25e3a232fa51c8edef4293200136","unresolved":true,"context_lines":[{"line_number":1101,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":1102,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"},{"line_number":1103,"context_line":"\t\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":1104,"context_line":"\t\tif (rel \u003e 1) {"},{"line_number":1105,"context_line":"\t\t\tLOG_DEBUG(\"Unknown release in cache code\");"},{"line_number":1106,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"7cabc49f_70690107","line":1104,"in_reply_to":"933d835e_6d7c5c3b","updated":"2023-11-21 04:16:46.000000000","message":"This is not part of the patch chain, but I could try to explain it.\n\nAt the time this code is written, MIPS release 6 was in pre release, and the encoding of `cache` instruction has changed in release 6 (MD00086 rev6.06, page 114 for cache instruction and page 470 for full updates), which does not fit for the instr generation in mips32.h, as it can only handle microMIPS and MIPS32 instrs.\n\nI can try to add support for MIPSr6 in another patch later, but refractoring mips32.h could be challenging as the debugger should switch between micormips and mips32 based on current running ISA.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"6ccd0bcdd24480e6d62c2dd9480f49c432b5ac22","unresolved":false,"context_lines":[{"line_number":1101,"context_line":"\t\tuint32_t start_addr \u003d addr;"},{"line_number":1102,"context_line":"\t\tuint32_t end_addr \u003d addr + count * size;"},{"line_number":1103,"context_line":"\t\tuint32_t rel \u003d (conf \u0026 MIPS32_CONFIG0_AR_MASK) \u003e\u003e MIPS32_CONFIG0_AR_SHIFT;"},{"line_number":1104,"context_line":"\t\tif (rel \u003e 1) {"},{"line_number":1105,"context_line":"\t\t\tLOG_DEBUG(\"Unknown release in cache code\");"},{"line_number":1106,"context_line":"\t\t\treturn ERROR_FAIL;"},{"line_number":1107,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":19,"id":"4c4ef06b_a3308e7c","line":1104,"in_reply_to":"9b88bffa_ea1985cf","updated":"2023-11-22 09:50:28.000000000","message":"Done","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"67914576aa9d50b7bf1180981e01cd43adff9dea","unresolved":true,"context_lines":[{"line_number":1173,"context_line":"\tuint32_t jmp_code[] \u003d {"},{"line_number":1174,"context_line":"\t\tMIPS32_LUI(isa, 15, UPPER16(source-\u003eaddress)),\t\t\t/* load addr of jump in $15 */"},{"line_number":1175,"context_line":"\t\tMIPS32_ORI(isa, 15, 15, LOWER16(source-\u003eaddress) | isa),\t/* isa bit for JR instr */"},{"line_number":1176,"context_line":"\t\trel \u003e MIPS32_RELEASE_1 ? MIPS32_JRHB(isa, 15) : MIPS32_JR(isa, 15),\t/* jump to ram program */"},{"line_number":1177,"context_line":"\t\tisa ? MIPS32_XORI(isa, 15, 15, 1) : MIPS32_NOP,\t/* drop isa bit, needed for LW/SW instructions */"},{"line_number":1178,"context_line":"\t};"},{"line_number":1179,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":19,"id":"08b7161d_449f8d64","line":1176,"updated":"2023-11-17 14:03:46.000000000","message":"maps32_cpu_support_jrhb()","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"fd9ae554d13f25e3a232fa51c8edef4293200136","unresolved":true,"context_lines":[{"line_number":1173,"context_line":"\tuint32_t jmp_code[] \u003d {"},{"line_number":1174,"context_line":"\t\tMIPS32_LUI(isa, 15, UPPER16(source-\u003eaddress)),\t\t\t/* load addr of jump in $15 */"},{"line_number":1175,"context_line":"\t\tMIPS32_ORI(isa, 15, 15, LOWER16(source-\u003eaddress) | isa),\t/* isa bit for JR instr */"},{"line_number":1176,"context_line":"\t\trel \u003e MIPS32_RELEASE_1 ? MIPS32_JRHB(isa, 15) : MIPS32_JR(isa, 15),\t/* jump to ram program */"},{"line_number":1177,"context_line":"\t\tisa ? MIPS32_XORI(isa, 15, 15, 1) : MIPS32_NOP,\t/* drop isa bit, needed for LW/SW instructions */"},{"line_number":1178,"context_line":"\t};"},{"line_number":1179,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":19,"id":"b8f132dd_28fdea04","line":1176,"in_reply_to":"08b7161d_449f8d64","updated":"2023-11-21 04:16:46.000000000","message":"Same as comments on #826, or I can turn them into macros like\n`#define mips32_cpu_support_jrhb(release) (release \u003e MIPS32_RELEASE_1)`\nor make them into inline functions.","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"6ccd0bcdd24480e6d62c2dd9480f49c432b5ac22","unresolved":false,"context_lines":[{"line_number":1173,"context_line":"\tuint32_t jmp_code[] \u003d {"},{"line_number":1174,"context_line":"\t\tMIPS32_LUI(isa, 15, UPPER16(source-\u003eaddress)),\t\t\t/* load addr of jump in $15 */"},{"line_number":1175,"context_line":"\t\tMIPS32_ORI(isa, 15, 15, LOWER16(source-\u003eaddress) | isa),\t/* isa bit for JR instr */"},{"line_number":1176,"context_line":"\t\trel \u003e MIPS32_RELEASE_1 ? MIPS32_JRHB(isa, 15) : MIPS32_JR(isa, 15),\t/* jump to ram program */"},{"line_number":1177,"context_line":"\t\tisa ? MIPS32_XORI(isa, 15, 15, 1) : MIPS32_NOP,\t/* drop isa bit, needed for LW/SW instructions */"},{"line_number":1178,"context_line":"\t};"},{"line_number":1179,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":19,"id":"c44a43f7_ea2c9fa4","line":1176,"in_reply_to":"b8f132dd_28fdea04","updated":"2023-11-22 09:50:28.000000000","message":"Done","commit_id":"35028825143f6e562f5c6ddeb3738fc9331ce653"}]}