)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"415f2c744b0e5648fb570167d66f45a8011bfe18","unresolved":true,"context_lines":[{"line_number":10,"context_line":"the implementation, as the function reads all the registers from"},{"line_number":11,"context_line":"ARMV8_PC and above."},{"line_number":12,"context_line":"The registers currently read are not relevant to answer to the"},{"line_number":13,"context_line":"usual GDB initial request through the \u0027g\u0027 packet. Plus the lack of"},{"line_number":14,"context_line":"differentiation per core state (AArch32 vs AArch64) causes the"},{"line_number":15,"context_line":"read of not existing registers in AArch32 triggering errors, as"},{"line_number":16,"context_line":"tentatively fixed by https://review.openocd.org/5517/"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"0e7da6fd_5b59ff33","line":13,"range":{"start_line":13,"start_character":0,"end_line":13,"end_character":48},"updated":"2023-09-11 08:17:28.000000000","message":"From gdb\u0027s point of view I don\u0027t see any difference between reading R2-SP registers in gdb_get_registers_packet() (used by the original code) or pre-read in armv8_dpm_read_current_registers().\n\nThe main difference is what OpenOCD \u0027reg\u0027 command shows - with the original code user have to issue \u0027reg rxx force\u0027 to force each register read or no value is shown. Also Tcl \u0027get_reg\u0027 works with cached register values (and returns the cached value even if not valid!! - IMO a bug - it doesn\u0027t read a register from hardware until explicitly requested).","commit_id":"2dcdd4888b29c00ce9673f2546c9cda67397b178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"2b271e2c9bece97768c909f6f963b9546974ca48","unresolved":false,"context_lines":[{"line_number":10,"context_line":"the implementation, as the function reads all the registers from"},{"line_number":11,"context_line":"ARMV8_PC and above."},{"line_number":12,"context_line":"The registers currently read are not relevant to answer to the"},{"line_number":13,"context_line":"usual GDB initial request through the \u0027g\u0027 packet. Plus the lack of"},{"line_number":14,"context_line":"differentiation per core state (AArch32 vs AArch64) causes the"},{"line_number":15,"context_line":"read of not existing registers in AArch32 triggering errors, as"},{"line_number":16,"context_line":"tentatively fixed by https://review.openocd.org/5517/"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"004fca1f_dac58706","line":13,"range":{"start_line":13,"start_character":0,"end_line":13,"end_character":48},"in_reply_to":"0e7da6fd_5b59ff33","updated":"2023-09-17 14:15:22.000000000","message":"Agree, from gdb point of view there is no difference.\nAnyway, checking ARM, Cortex-A and Cortex-M code, we pre-read the registers R0-PC to be ready to feed gdb.\nMaybe there is no need and we can speed up the halt by reading only what OpenOCD strictly needs (R0 and PC).\n\nThen, the way aarch64.c handles the registers Aarch64/Aarch32 is really ugly. Should be reworked.\nI haven\u0027t noticed the bug on \u0027get_reg\u0027 ...","commit_id":"2dcdd4888b29c00ce9673f2546c9cda67397b178"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"8cf33cdb3d7ae9972da1d37dfd58b5e9a603ae60","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"99f00ed4_49723eb5","updated":"2023-10-07 14:39:03.000000000","message":"Let\u0027s merge this to fix the read of non-existing registers.\nFurther improvements can get in later on","commit_id":"2dcdd4888b29c00ce9673f2546c9cda67397b178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"415f2c744b0e5648fb570167d66f45a8011bfe18","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"891ce091_aa7a5b7d","updated":"2023-09-11 08:17:28.000000000","message":"Looks reasonable to me.\nI checked if there is any use of a reg \u003e\u003d ARMV8_PC which depends on the cache validity. Seems there is not, but I\u0027m not familiar with aarch64 targets enough to be 100% sure.","commit_id":"2dcdd4888b29c00ce9673f2546c9cda67397b178"}]}