)]}'
{"id":"openocd~master~Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b","project":"openocd","branch":"master","attention_set":{},"removed_from_attention_set":{"1000021":{"account":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"last_update":"2023-10-07 14:46:11.000000000","reason":"removed on reply"},"1001678":{"account":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"last_update":"2023-10-07 14:46:18.000000000","reason":"Change was submitted"}},"hashtags":[],"change_id":"Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b","subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","status":"MERGED","created":"2023-09-14 12:54:23.000000000","updated":"2023-10-07 14:46:18.000000000","submitted":"2023-10-07 14:46:18.000000000","submitter":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"total_comment_count":5,"unresolved_comment_count":0,"has_review_started":true,"submission_id":"7899","meta_rev_id":"ec19ab3d5252dcc3710ae9502af2301e57e4c529","_number":7899,"owner":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"actions":{},"labels":{"Verified":{"approved":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"all":[{"value":0,"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},{"tag":"autogenerated:gerrit:merged","value":1,"date":"2023-10-07 14:46:18.000000000","permitted_voting_range":{"min":1,"max":1},"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}],"values":{"-1":"Fails"," 0":"No score","+1":"Verified"},"description":"","default_value":0},"Code-Review":{"approved":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"all":[{"tag":"autogenerated:gerrit:merged","value":2,"date":"2023-10-07 14:46:18.000000000","permitted_voting_range":{"min":2,"max":2},"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},{"value":0,"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}],"values":{"-2":"This shall not be merged","-1":"I would prefer this is not merged as is"," 0":"No score","+1":"Looks good to me, but someone else must approve","+2":"Looks good to me, approved"},"description":"","default_value":0}},"removable_reviewers":[],"reviewers":{"REVIEWER":[{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"}]},"pending_reviewers":{},"reviewer_updates":[{"updated":"2023-09-14 12:56:21.000000000","updated_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"reviewer":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"state":"REVIEWER"},{"updated":"2023-09-17 14:47:57.000000000","updated_by":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"reviewer":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"state":"CC"},{"updated":"2023-09-18 21:28:37.000000000","updated_by":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"reviewer":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"state":"REVIEWER"}],"messages":[{"id":"a25746ab44a551548fb1280539f0b162aadb45c5","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-14 12:54:23.000000000","message":"Uploaded patch set 1.","accounts_in_message":[],"_revision_number":1},{"id":"7f59c13b8080a13dd8064e291f00ebce36f8313d","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-14 12:56:15.000000000","message":"Uploaded patch set 2: Commit message was updated.","accounts_in_message":[],"_revision_number":2},{"id":"7a85d77336bf77f600df0e0e128d75a68c7730d7","tag":"autogenerated:jenkins-gerrit-trigger","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2023-09-14 12:56:21.000000000","message":"Patch Set 1: Verified-1\n\nBuild Failed \n\nhttps://build.openocd.org/job/openocd-gerrit/18369/ : ABORTED\n\nhttps://build.openocd.org/job/openocd-gerrit-build/17558/ : ABORTED","accounts_in_message":[],"_revision_number":1},{"id":"060628c2a23bc52c244a6fac2894b544d35f6fca","tag":"autogenerated:jenkins-gerrit-trigger","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2023-09-14 13:11:45.000000000","message":"Patch Set 2: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/18370/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/17559/ : SUCCESS","accounts_in_message":[],"_revision_number":2},{"id":"a6edd70481426a207ea148701c24e04b876ae6ad","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-14 13:43:27.000000000","message":"Uploaded patch set 3.\n\nOutdated Votes:\n* Verified+1 (copy condition: \"changekind:NO_CHANGE\")\n","accounts_in_message":[],"_revision_number":3},{"id":"354cbeef0b55e33f1749053f074ab35579800e43","tag":"autogenerated:jenkins-gerrit-trigger","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2023-09-14 13:56:06.000000000","message":"Patch Set 3: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/18371/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/17560/ : SUCCESS","accounts_in_message":[],"_revision_number":3},{"id":"afdac4d0a39572845712895ce7dd18eaec4ef8e1","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2023-09-17 14:47:57.000000000","message":"Patch Set 3:\n\n(1 comment)","accounts_in_message":[],"_revision_number":3},{"id":"32b981acc36d6810f1e988c6d3a48a9e6176b107","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-18 13:08:59.000000000","message":"Patch Set 3:\n\n(2 comments)","accounts_in_message":[],"_revision_number":3},{"id":"8b9adf073961233d83771f7344f83b0465145f0b","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-18 13:25:14.000000000","message":"Uploaded patch set 4.\n\nOutdated Votes:\n* Verified+1 (copy condition: \"changekind:NO_CHANGE\")\n","accounts_in_message":[],"_revision_number":4},{"id":"33e3709d52470ef79f5074ed8c9dea3344832d59","tag":"autogenerated:jenkins-gerrit-trigger","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2023-09-18 14:33:06.000000000","message":"Patch Set 4: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/18397/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/17587/ : SUCCESS","accounts_in_message":[],"_revision_number":4},{"id":"f934e7d8bee9695e931dc32cf5945b50377821fc","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2023-09-18 21:28:37.000000000","message":"Patch Set 4: Code-Review+1\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"25cb016fc45c20484f1c879298a713c1e84ea2ad","tag":"autogenerated:gerrit:newPatchSet","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-25 12:55:17.000000000","message":"Uploaded patch set 5: Patch Set 4 was rebased.\n\nOutdated Votes:\n* Code-Review+1 (copy condition: \"changekind:NO_CHANGE OR is:MIN\")\n* Verified+1 (copy condition: \"changekind:NO_CHANGE\")\n","accounts_in_message":[],"_revision_number":5},{"id":"c809b9396fcf095ff92239d73694caaa970b4508","author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"real_author":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"date":"2023-09-25 12:56:54.000000000","message":"Patch Set 5:\n\n(1 comment)","accounts_in_message":[],"_revision_number":5},{"id":"2d07e134c1e0eb827be4e9ed819e52ba2d058526","tag":"autogenerated:jenkins-gerrit-trigger","author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"real_author":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]},"date":"2023-09-25 13:34:08.000000000","message":"Patch Set 5: Verified+1\n\nBuild Successful \n\nhttps://build.openocd.org/job/openocd-gerrit/18441/ : SUCCESS\n\nhttps://build.openocd.org/job/openocd-gerrit-build/17629/ : SUCCESS","accounts_in_message":[],"_revision_number":5},{"id":"c4cfcb7c8c5323bf513cc6022436e74bac17211e","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2023-10-07 14:46:11.000000000","message":"Patch Set 5: Code-Review+2","accounts_in_message":[],"_revision_number":5},{"id":"ec19ab3d5252dcc3710ae9502af2301e57e4c529","tag":"autogenerated:gerrit:merged","author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"real_author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"date":"2023-10-07 14:46:18.000000000","message":"Change has been successfully cherry-picked as 9c7c5ca4eb04b110f66b4e3c2494a1d55a962b33","accounts_in_message":[],"_revision_number":6}],"current_revision":"9c7c5ca4eb04b110f66b4e3c2494a1d55a962b33","revisions":{"29df9ad922f3be175dbe5525eab302c77c6e3dc4":{"kind":"REWORK","_number":1,"created":"2023-09-14 12:54:23.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/99/7899/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/1 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1ed87e99bf4cacd8dcf273476d83fc64e67bcfc6","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:53:52.000000000","tz":-300},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, All K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is esp\nuseful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"8c9b8b112bf4439ba4da0732af9cca83888aac93":{"kind":"NO_CODE_CHANGE","_number":2,"created":"2023-09-14 12:56:15.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/99/7899/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/2 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1ed87e99bf4cacd8dcf273476d83fc64e67bcfc6","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:55:53.000000000","tz":-300},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, all K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is\nespecially useful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"4dc98ba6030f9c9c050d51db326d5ac2f6d01dc4":{"kind":"REWORK","_number":3,"created":"2023-09-14 13:43:27.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/99/7899/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/3 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1ed87e99bf4cacd8dcf273476d83fc64e67bcfc6","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 13:40:44.000000000","tz":-300},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, all K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is\nespecially useful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nTo prevent a circular-loop scenario for axi-ap accessing debug memory\nwith dmem (direct memory access debug), enable this only when dmem is\ndisabled.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"5e7f7ca7316d3b3039077de644914e9c971b022a":{"kind":"REWORK","_number":4,"created":"2023-09-18 13:25:14.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/99/7899/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/4 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"7351453853dd1cf914e1364fc11feb4f13d62b63","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-18 13:22:31.000000000","tz":-300},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, all K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is\nespecially useful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nTo prevent a circular-loop scenario for axi-ap accessing debug memory\nwith dmem (direct memory access debug), enable this only when dmem is\ndisabled.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"1f8941c7a0e0dbb6e33ca083474df797c2c285c2":{"kind":"TRIVIAL_REBASE","_number":5,"created":"2023-09-25 12:55:17.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/99/7899/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/5 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"57c8ad5ed7566a843117543c0e089c0743e43f62","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-25 12:53:07.000000000","tz":-300},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, all K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is\nespecially useful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nTo prevent a circular-loop scenario for axi-ap accessing debug memory\nwith dmem (direct memory access debug), enable this only when dmem is\ndisabled.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"9c7c5ca4eb04b110f66b4e3c2494a1d55a962b33":{"kind":"REWORK","_number":6,"created":"2023-10-07 14:46:18.000000000","uploader":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"ref":"refs/changes/99/7899/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/99/7899/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/6 \u0026\u0026 git checkout -b change-7899 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/99/7899/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/99/7899/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"d14fef8495e6d0247ea2929053d27b5c561ac1d0","subject":"tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2023-09-14 12:49:02.000000000","tz":-300},"committer":{"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","date":"2023-10-07 14:46:18.000000000","tz":0},"subject":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access","message":"tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access\n\nWhile we can read and write from memory from the view of various\nprocessors, all K3 debug systems have a AXI Access port that allows\nus to directly access memory from debug interface. This port is\nespecially useful in the following scenarios:\n\n1. Debug cache related behavior on processors as this provides a\n   direct bypass path.\n2. Processor has crashed or inaccessible for some reason (low power\n   state etc.)\n3. Scenarios prior to the processor getting active.\n4. Debug MMU or address translation issues (example: TI\u0027s Region\n   Address Table {RAT} translation table used to physically map\n   SoC address space into R5/M4F processor address space)\n\nThe AXI-AP port is the same for all processors in TI\u0027s K3 family.\n\nTo prevent a circular-loop scenario for axi-ap accessing debug memory\nwith dmem (direct memory access debug), enable this only when dmem is\ndisabled.\n\nChange-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b\nReported-by: Dubravko Srsan \u003cdubravko.srsan@dolotron.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\nReviewed-on: https://review.openocd.org/c/openocd/+/7899\nReviewed-by: Antonio Borneo \u003cborneo.antonio@gmail.com\u003e\nTested-by: jenkins\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"CLOSED","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"],"failing_atoms":[]}}]}