)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002192,"name":"frankplow","email":"post@frankplowman.com","username":"frankplow"},"change_message_id":"edeb9c70521974e8299efd826ef7bc578e5c6469","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"ebf4bf9f_f55e5070","updated":"2023-09-17 13:31:03.000000000","message":"I can confirm this patch fixes an issue I experienced whereby ITM stimulus port 0 was not enabled by default on an nRF52832 MCU.","commit_id":"d28e34cedb98400ee0449bfce7d8f40d409b6113"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"38d3ab151c81452d94c8f1300a4d233dc95bec6e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5f4f8451_63402264","updated":"2023-09-17 09:28:49.000000000","message":"I\u0027m afraid this patch could hang complex systems with no ITM.\nFor simple Cortex-M0 (without ITM) this is not a problem because a write at ITM addresses would be silently ignored.\nBut more complex and security enhanced SoC\u0027s could generate exceptions or hang due to writes in armv7m_trace_itm_config().\nWe could detect the ITM by reading its IDs in armv7m_trace_itm_config() before any write. The read \u0027should\u0027 not cause issues.","commit_id":"d28e34cedb98400ee0449bfce7d8f40d409b6113"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"375c89d8687362f086f4ccd846bc050707c8e659","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"64ca6a59_308cddd8","updated":"2024-06-08 21:27:36.000000000","message":"This got lost... I will merge it in 1~2 weeks if nobody complains","commit_id":"d28e34cedb98400ee0449bfce7d8f40d409b6113"}]}