)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9b9576c0e3560bbd193397b7bf4dee410d0ac253","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"3014745a_6651bca2","updated":"2023-11-15 13:32:47.000000000","message":"I cannot test, don\u0027t have any APM32.\nHopefully the similarity with the patch 7110 confirms the solution works.","commit_id":"7e6ec65bfe66b62678718690b442e1bfc5b66540"}],"doc/openocd.texi":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"235b2df150c49e99492d52a7cf44bc823abd3639","unresolved":true,"context_lines":[{"line_number":7676,"context_line":"All members of the STM32F0, STM32F1 and STM32F3 microcontroller families"},{"line_number":7677,"context_line":"from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller"},{"line_number":7678,"context_line":"families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores."},{"line_number":7679,"context_line":"The driver also works with the APM32F0 series from Geehy Semiconductor."},{"line_number":7680,"context_line":"The driver also works with GD32VF103 powered by RISC-V core."},{"line_number":7681,"context_line":"The driver automatically recognizes a number of these chips using"},{"line_number":7682,"context_line":"the chip identification register, and autoconfigures itself."}],"source_content_type":"text/x-texinfo","patch_set":2,"id":"4db47cd3_eba0838e","line":7679,"updated":"2023-11-16 07:24:37.000000000","message":"Sorry Marc, I didn\u0027t noticed at first.\nYou put APM32 in the middle of GD devices.\n\nExpecting more clones are coming here this part of text would need rewrite to an (alphabetically sorted) list like:\n```\nAll members of the STM32F0, STM32F1 and STM32F3 microcontroller families\nfrom STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.\n\nThe driver also works with various devices containing a clone of the STM32 flash controller e.g.:\nGeehy Semiconductor APM32F0 (Cortex-M0+), ...\nGigaDevice GD32F1x0, GD32F3x0, GD32E23x (Cortex-M23) and GD32VF103 (RISC-V)\n```","commit_id":"7e6ec65bfe66b62678718690b442e1bfc5b66540"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"48ddbd2f114c280173775ac80dcf19836058ad95","unresolved":true,"context_lines":[{"line_number":7676,"context_line":"All members of the STM32F0, STM32F1 and STM32F3 microcontroller families"},{"line_number":7677,"context_line":"from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller"},{"line_number":7678,"context_line":"families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores."},{"line_number":7679,"context_line":"The driver also works with the APM32F0 series from Geehy Semiconductor."},{"line_number":7680,"context_line":"The driver also works with GD32VF103 powered by RISC-V core."},{"line_number":7681,"context_line":"The driver automatically recognizes a number of these chips using"},{"line_number":7682,"context_line":"the chip identification register, and autoconfigures itself."}],"source_content_type":"text/x-texinfo","patch_set":2,"id":"c277960e_f9902e15","line":7679,"in_reply_to":"4db47cd3_eba0838e","updated":"2023-11-16 10:34:07.000000000","message":"Good catch, thanks! The description was a total mess in my opinion anyway. I tried to clean it up and removed the \"information\" about the cores which (in my opinion) is not necessary here. I also changed the term \"family\" to \"series\" and the series names as used by the manufacturers.\n\nI will also add another device soon that cannot be distinguished from other devices by the core. For that I will introduce a new configuration parameter like \u0027-chip\u0027 to manually indicate the chip. Any thoughts on that?","commit_id":"7e6ec65bfe66b62678718690b442e1bfc5b66540"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"f35bfd8d9ec0b5cc5626c7d4c8d62e5b4f7a2d81","unresolved":false,"context_lines":[{"line_number":7676,"context_line":"All members of the STM32F0, STM32F1 and STM32F3 microcontroller families"},{"line_number":7677,"context_line":"from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller"},{"line_number":7678,"context_line":"families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores."},{"line_number":7679,"context_line":"The driver also works with the APM32F0 series from Geehy Semiconductor."},{"line_number":7680,"context_line":"The driver also works with GD32VF103 powered by RISC-V core."},{"line_number":7681,"context_line":"The driver automatically recognizes a number of these chips using"},{"line_number":7682,"context_line":"the chip identification register, and autoconfigures itself."}],"source_content_type":"text/x-texinfo","patch_set":2,"id":"0671145c_ec8a5656","line":7679,"in_reply_to":"bf3010fc_1fc64488","updated":"2023-12-05 21:56:16.000000000","message":"\u003e \u003e The description was a total mess in my opinion anyway...\n\u003e \n\u003e Hmm, normal copy-pasta as everywhere... you\u0027re right that core type is not important for a user and a developer can look to target .cfg\n\u003e There is one exception: GD32VF103 - a normally thinking user would say all ST have a Cortex-M and this one has RISC-V - it couldn\u0027t work with the same driver. That\u0027s why I emphasized the core.\n\nI would assume that an user simple uses the driver if documented as suitable. Anyway, fixed.\n\n\u003e BTW GD32VF103 seems to be the only device in series, so we should use the full name.\n\nDone.\n\n\u003e Also I\u0027m very unsure if we can shorten other series names as you did. I hope the name corresponds to devices what were available for testing and author knowledge what is supported.\n\nI don\u0027t think that\u0027s very important. We consider the entire series as supported, if single or few devices don\u0027t work it\u0027s a bug and needs to be reported.\n\n\u003e And GD32E23x resembles its core Cortex-M23 and no other numbers are in the series (however there are some GD32L23x) - not the same numbering scheme as ST uses.\n\nYes, but still the core in the documentation is \"useless\" (additional) information for users.","commit_id":"7e6ec65bfe66b62678718690b442e1bfc5b66540"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4e978b3c9ec61b4081a582b8bbdfcbaeb08d1381","unresolved":true,"context_lines":[{"line_number":7676,"context_line":"All members of the STM32F0, STM32F1 and STM32F3 microcontroller families"},{"line_number":7677,"context_line":"from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller"},{"line_number":7678,"context_line":"families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores."},{"line_number":7679,"context_line":"The driver also works with the APM32F0 series from Geehy Semiconductor."},{"line_number":7680,"context_line":"The driver also works with GD32VF103 powered by RISC-V core."},{"line_number":7681,"context_line":"The driver automatically recognizes a number of these chips using"},{"line_number":7682,"context_line":"the chip identification register, and autoconfigures itself."}],"source_content_type":"text/x-texinfo","patch_set":2,"id":"bf3010fc_1fc64488","line":7679,"in_reply_to":"c277960e_f9902e15","updated":"2023-11-16 22:50:18.000000000","message":"\u003e The description was a total mess in my opinion anyway...\n\nHmm, normal copy-pasta as everywhere... you\u0027re right that core type is not important for a user and a developer can look to target .cfg\nThere is one exception: GD32VF103 - a normally thinking user would say all ST have a Cortex-M and this one has RISC-V - it couldn\u0027t work with the same driver. That\u0027s why I emphasized the core. BTW GD32VF103 seems to be the only device in series, so we should use the full name.\nAlso I\u0027m very unsure if we can shorten other series names as you did. I hope the name corresponds to devices what were available for testing and author knowledge what is supported.\nAnd GD32E23x resembles its core Cortex-M23 and no other numbers are in the series (however there are some GD32L23x) - not the same numbering scheme as ST uses.\n\n\u003e I will also add another device soon that cannot be distinguished from other devices by the core. For that I will introduce a new configuration parameter like \u0027-chip\u0027 to manually indicate the chip. Any thoughts on that?\n\nLot of discussion on this topic is in\n6543: add GigaDevice GD32Exxx flash driver | https://review.openocd.org/c/openocd/+/6543\n6552: move gd32f1x0 and gd32f3x0 to gd32 driver | https://review.openocd.org/c/openocd/+/6552","commit_id":"7e6ec65bfe66b62678718690b442e1bfc5b66540"}],"src/flash/nor/stm32f1x.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"33460ad3d7bba8c5642fdcdbbbba379d6e4a3fb2","unresolved":true,"context_lines":[{"line_number":748,"context_line":"\t\taddr-\u003edevice_id \u003d 0x40015800;"},{"line_number":749,"context_line":"\t\taddr-\u003eflash_size \u003d 0x1FFFF7CC;"},{"line_number":750,"context_line":"\t\treturn ERROR_OK;"},{"line_number":751,"context_line":"\tcase CORTEX_M0P_PARTNO: /* APM32F0x devices */"},{"line_number":752,"context_line":"\t\taddr-\u003edevice_id \u003d 0x40015800;"},{"line_number":753,"context_line":"\t\taddr-\u003eflash_size \u003d 0x1FFFF7CC;"},{"line_number":754,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"7ba7f98a_a38cf266","line":751,"updated":"2023-11-15 08:11:30.000000000","message":"The same code has been waiting for more than year in\n7110: Add support for Geehy Cortex-M0+ controllers proposed by Paul Fertser on the user mailing list | https://review.openocd.org/c/openocd/+/7110\n\nWell the commit message didn\u0027t conform our requirements and it also lacks a documentation. Anyway I would prefer if you can rebase your series on it\nor at least refer the original author in Suggested-by and use common case code for both M0 and M0+ as 7110 does.","commit_id":"99fe3b6ed1044054412d90644b7dae174ac33abd"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"ba0399d1123faaddd1437bc79fc350e4152802d1","unresolved":false,"context_lines":[{"line_number":748,"context_line":"\t\taddr-\u003edevice_id \u003d 0x40015800;"},{"line_number":749,"context_line":"\t\taddr-\u003eflash_size \u003d 0x1FFFF7CC;"},{"line_number":750,"context_line":"\t\treturn ERROR_OK;"},{"line_number":751,"context_line":"\tcase CORTEX_M0P_PARTNO: /* APM32F0x devices */"},{"line_number":752,"context_line":"\t\taddr-\u003edevice_id \u003d 0x40015800;"},{"line_number":753,"context_line":"\t\taddr-\u003eflash_size \u003d 0x1FFFF7CC;"},{"line_number":754,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"f7f0b138_80d13148","line":751,"in_reply_to":"7ba7f98a_a38cf266","updated":"2023-11-15 10:56:28.000000000","message":"Done","commit_id":"99fe3b6ed1044054412d90644b7dae174ac33abd"}]}