)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"b420ed42688d02243cdd5ecb5d24c0b032be29ce","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"8b2fc144_dfa15d28","updated":"2024-01-16 07:11:04.000000000","message":"\u003e Evgeniy: I have only one minor concern about invalidation. I believe not every register should be invalidate-able.\n\nThis would be a nice performance optimization. But I would like to leave this for a separate merge request.\n\nMy priority is to fix the existing bug (by adding the flush). As you can see from the previous discussion, even that is getting a bit complicated already :-) \n\nFor that reason, if you don\u0027t mind, I would like to leave performance optimizations aside, at least for now.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"617d668b8423ed9f4927219d76f8a5dba93ac151","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"989b65af_1291e7e2","updated":"2024-01-15 07:12:56.000000000","message":"\u003e Evgeniy: I\u0027m not sure the approach you are suggesting is optimal.\n\nHi Evgeniy, thank you for looking at our patch, and for your alternate suggestion for the register cache flush. \n\nWe like that approach and believe it would work nicely.\n\nBefore implementing it this way, we\u0027d like to see if other reviewers are also in favor of it.\n\nSo the proposal would be:\n\n1) Extend `struct reg_arch_type` with the flush callback (as Evgeniy suggests):\n\n```c\nstruct reg_arch_type {\n        int (*get)(struct reg *reg);\n        int (*set)(struct reg *reg, uint8_t *buf);\n        int (*flush)(struct reg *reg);  \n};\n```\n\n2) Extend command \"reg\" \n\n```\n# Current \"reg\" write:\nreg \u003creg_name\u003e \u003cnew_value\u003e\n\n# Proposed extension:\nreg \u003creg_name\u003e \u003cnew_value\u003e [force [invalidate]]\n\n# If \"force\" is set, register value is written to the target via flush().\n# If both \"force\" and \"invalidate\" is set, the \"valid\" flag of the register is set to false after the flush().\n```\n\n3) Extend command \"set_reg\" the same way\n\n```\n# Current \"set_reg\":\nset_reg \u003creg_name1\u003e \u003cvalue1\u003e [ \u003creg_name2\u003e \u003cvalue2\u003e [...] ] \n\n# Proposed extension:\nset_reg [-force [-invalidate] ] \u003creg_name1\u003e \u003cvalue1\u003e [ \u003creg_name2\u003e \u003cvalue2\u003e [...] ] \n```\n\n4) Implement command `flush_reg_cache [-invalidate]` that flushes all dirty register values on the given target. That is, flush() is called on all registers of the target that are dirty. \n\nThis is needed e.g. in RISC-V where some of the registers are used temporarily for various operations (e.g. in program buffer) and, therefore, can become dirty even when not explicitly written to by the user.\n\n\n\nPlease let us know if this proposal sounds OK to you. \n\nThank you.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"92371f331bfa50343324cddc1da6cafa4f42e602","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"588c5fcb_4687ccab","updated":"2024-01-16 07:18:08.000000000","message":"\u003eEvgeniy: Consider a read-only register or such register that the change of it\u0027s value is not properly supported by OpenOCD (e.g. misa for RISC-V targets).\n\nAs an aside: The RISC-V `misa` register is not necessarily read-only. It can be writable (WARL) since the [RISC-V Unprivileged Spec](https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view?usp\u003ddrive_link) v1.9.1. \n\nQuoting from the changelog: \n\n```\nMade misa optionally writable to support modifying \nbase and supported ISA extensions. CSR address \nof misa changed.\n```","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"183f47ada88999641655bb35fd00edbb7f91c672","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"0b5beb31_5513b4d5","updated":"2024-01-15 07:13:58.000000000","message":"Adding Antonio and Marc to CC. \n\nPlease, if you have a moment, could you take a look at the proposal.\n\nThank you.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f2c164feb2bb995a8bde94538ece6048ec1b2458","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"20d5d35c_895b4884","updated":"2024-01-17 06:07:02.000000000","message":"Evgeniy, thank you for taking the time to look at this.\n\nI will wait approx. 2 days whether anyone comes with a different opinion. If not, ether Marek or me will implement the flush() + fix for the invalidation as proposed above.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"80f4bfcb311b9d4f65d9bfd730e35cb48e1f79f6","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"f551047f_42d226f1","updated":"2024-01-16 07:05:29.000000000","message":"Hi Evgeniy, thank you for checking the proposal.\n\n\u003e Evgeniy: I would like to disagree that the behavior you are describing is unexpected.\n\nI believe the main rules we should follow here are:\n\n1. Any sequence of reads and writes to registers should produce the same results with or without the use of the cache. (The cache is here only for performance optimization.)\n\n2. If the use of cache leads to different results than without the cache, then we have a bug that needs to be fixed. (Otherwise the users may experience transient, hard-to-debug bugs, depending on the sequence of operations and state of the cache.)\n\n\u003e Evgeniy: If a register is cacheable on write, a sequence of two writes to it would also result in the first value discarded, so, I don\u0027t believe we should flush the cached value before invalidation.\n\nWe have described different scenarios:\n\n- My example was Read-After-Write (RAW), which now leads to different behavior with vs. without the cache. Therefore there is a bug (that needs to be fixed by adding the flush).\n\n- Your example was about Write-After-Write (WAW) on a write-cacheable register.  In this case I agree we can safely forget the the first written value from the cache, and don\u0027t need to flush it.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"944893163e08279db7abbf7c3854df761a18ce28","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"9dc10892_01f79b9e","updated":"2024-01-12 16:00:33.000000000","message":"Thank you for the patch! IMHO the functionality you implemented is much needed. \n\nHowever, I\u0027m not sure the approach you are suggesting is optimal.\nI would suggest to extend `reg_arch_type` by adding `flush` accessor (`target/register.h`):\n```\nstruct reg_arch_type {\n        int (*get)(struct reg *reg);\n        int (*set)(struct reg *reg, uint8_t *buf);\n        int (*flush)(struct reg *reg);\n};\n```\nThis would allow to customize `flush` on per-register level, as well as flush individual registers.\n\nAfter extending register interface, one will be able to add a `-force` flag to register writes by calling `flush` after `set`.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"20e82fd0f5d048c82830c4ff81358366cfd799fc","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"a7ab5d4c_e54521b7","updated":"2024-01-15 13:31:40.000000000","message":"There is one more strong reason for introducing the flush() callback for registers.\n\nConsider the following sequence of commands which leads to unexpected behavior:\n\n```tcl\n# Try write 0xABCD to register x1 (or GDB can do this):\nreg x1 0xabcd  \n  # Let\u0027s suppose the target caches the register value \n  # until resume() or step() isperformed, therefore:\n  # x1.valid \u003d true\n  # x1.dirty \u003d true\n  \nreg x1 force\n  # Current behavior of OpenOCD:\n  \n  # x1.valid \u003d false --\u003e Value 0xABCD, not yet written though,\n  #                      gets lost!\n  # get_reg() \n  # ...\n  \n  # Expected behavior:\n  \n  # if (x1.valid \u0026\u0026 x1.dirty) {\n  #    // Must flush before invalidating \n  #    // the current cached entry!\n  #    flush(x1);\n  # }\n  # x1.valid \u003d false\n  # get_reg()\n  # ...\n \n```","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"ef4f6947_eb156285","in_reply_to":"0fc41b2b_22e50ecd","updated":"2024-02-01 13:11:40.000000000","message":"Ack","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"2d51a616_25a151c3","in_reply_to":"20d5d35c_895b4884","updated":"2024-01-30 15:57:55.000000000","message":"Implemented in the new proposal.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"2c1f1637_98326a8f","in_reply_to":"2d51a616_25a151c3","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"65cc8842_3d430bea","in_reply_to":"65fdd7df_5d60b714","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3960b459f7fd25db53b60ed7f8494ecab77ac2f1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"e4f1c108_4fa1b899","in_reply_to":"8b2fc144_dfa15d28","updated":"2024-01-16 17:25:13.000000000","message":"I agree. It\u0027s better to commit the invalidation as a separate patch.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"28b949a1141aa6bbcef75b176001725372fa03de","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"d2cd3c45_25935ce8","in_reply_to":"989b65af_1291e7e2","updated":"2024-01-15 18:24:49.000000000","message":"The proposal you are describing is great!\nI have only one minor concern about invalidation.\nI believe not every register should be invalidate-able.\nConsider a read-only register or such register that the change of it\u0027s value is not properly supported by OpenOCD (e.g. `misa` for RISC-V targets). If this register can be invalidated, this forces to implement another cache for it\u0027s value (e.g. `misa` value is cached additionally during `examine()`, so it can be accessed anytime: on a running target and so on).\nSo I would suggest the following:\n```\nstruct reg_arch_type {\n        int (*get)(struct reg *reg);\n        int (*set)(struct reg *reg, uint8_t *buf);\n        int (*flush)(struct reg *reg);\n        /* can be set to NULL for most targets */\n        void (*invalidate)(struct reg *reg);\n};\n...\nvoid invalidate(struct reg *reg)\n{\n   if (reg-\u003earch_type-\u003einvalidate)\n       return reg-\u003earch_type-\u003einvalidate(reg);\n   reg-\u003evalid \u003d reg-\u003edirty \u003d false;\n}\n```\nAnd for the `misa` example a custom handler:\n```\nvoid invalidate_misa(struct reg *misa)\n{\n    LOG_DEBUG(\"...\");\n}\n```","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"28b949a1141aa6bbcef75b176001725372fa03de","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"f9d712a1_9c249812","in_reply_to":"a7ab5d4c_e54521b7","updated":"2024-01-15 18:24:49.000000000","message":"I would like to disagree that the behavior you are describing is unexpected.\nIf a register is cacheable on write, a sequence of two writes to it would also result in the first value discarded, so, I don\u0027t believe we should flush the cached value before invalidation. IMHO, this is exactly the point of `force` in the read -- the behavior is different for cacheable register.\nMoreover, what if the `flush` fails? Should the read still be executed? I believe this complicates things.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"6a3d350b_a9a6be37","in_reply_to":"aec08e63_f773e3c1","updated":"2024-02-01 13:11:40.000000000","message":"Ack","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"aec08e63_f773e3c1","in_reply_to":"d2cd3c45_25935ce8","updated":"2024-01-30 15:57:55.000000000","message":"The new version implements most of it. The custom invalidation handler can come in a later patch.","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"2c9c4920_f8a79f2c","in_reply_to":"e4f1c108_4fa1b899","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3960b459f7fd25db53b60ed7f8494ecab77ac2f1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"65fdd7df_5d60b714","in_reply_to":"f551047f_42d226f1","updated":"2024-01-16 17:25:13.000000000","message":"You are right. Thanks for the explanation!","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"0fc41b2b_22e50ecd","in_reply_to":"f9d712a1_9c249812","updated":"2024-01-30 15:57:55.000000000","message":"Can you review the new version if it has the behavior you want?","commit_id":"f207b3dba91b1e9c24317ce0014048181943a847"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"f99f3d1c_ceb1cb55","updated":"2024-01-30 15:57:55.000000000","message":"Should be ready now","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"92b46622_2a50a35c","updated":"2024-01-30 15:33:34.000000000","message":"Thanks, Marek, for the fix and the related improvements.","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"4d453fc5_42012fb5","updated":"2024-01-31 10:50:20.000000000","message":"Thank you for the patch! Overall, I think it is a great improvement. I have a few minor suggestions and concerns.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"85822a04_ea3e030c","updated":"2024-01-30 15:59:14.000000000","message":"Thank you.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"7fdd5071_1a690ce3","updated":"2024-02-01 13:11:40.000000000","message":"Thanks for taking the for the review.","commit_id":"d4ec10c45938043063c21d844fc8e8a7e84ddc5a"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"a67d9712d37f742747b7d99bae864966b73dc7cb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":11,"id":"347298a6_ae11a8de","updated":"2024-02-05 08:29:04.000000000","message":"I have two last details related to usage/help messages, otherwise it looks fine. Thank you.","commit_id":"0513acc7e647797e1267f123162a80996dc1259c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"a367c065_6068a13f","updated":"2024-02-18 10:41:02.000000000","message":"Just some minor comment from my side, for the time being","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"a2d5a3db64de506db8176e090d14d9149d8c9ea4","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"cad064ab_c7a9d345","updated":"2024-02-21 09:32:23.000000000","message":"LGTM for the most part. Only a few minor suggestions.","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"6e2954f95993c6a3320467a0410a63e6251ba670","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":13,"id":"c0c0aaaf_61a03c23","updated":"2024-02-22 12:17:16.000000000","message":"Thanks for the feedback","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"28c4cc75113919d139b6fb2929d301309e065de8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":14,"id":"787bb1ff_61d22e75","updated":"2024-02-22 14:07:56.000000000","message":"Thank you for the quick reply! One more minor concern.","commit_id":"651beb0e40c0f041778537e515a1ca90d9394311"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5901b9f22dc6b0e061193cae7a031e59f04bb5dd","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":15,"id":"8b6d78c4_a15fd4a2","updated":"2024-03-01 06:36:45.000000000","message":"I have two last remaining suggestions for the documentation, the rest of the code otherwise looks fine to me.","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"6bdeba7312076c2fdfa066db88abd37ab726a4ab","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":15,"id":"bbc01907_f84a707c","updated":"2024-02-24 12:50:01.000000000","message":"LGTM","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"bac546dfdaa8775344dca9806f46c4236bb9ab6b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"bdff52e6_4ac7a844","updated":"2024-05-24 13:55:40.000000000","message":"Hello, I have revivied this merge request:\n\n- I have addressed the remaining cosmetic documentation comments.\n- The commit has been rebased.\n- The commit message has been sightly reworded for clarity.\n\nPlease, let us know if you have any further comments or if this can be merged.\n\nThank you!","commit_id":"d2d17e43a289db20e6cc44a0ba640ce11372be4f"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"142e31dffc419e39de561cb05485c10bedec439b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"c2adba99_56be0f52","updated":"2024-12-20 11:47:15.000000000","message":"I\u0027d like to ask you to revive this patch.\nAntonio, Marc, could you please take a look at this one when you have the time?\nMarek, Jan, I believe the patch needs a rebase.","commit_id":"d2d17e43a289db20e6cc44a0ba640ce11372be4f"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"2f3ceb681f840d3ed20107f0094b4c20de0ba18f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"4df95697_76f0c4be","updated":"2024-05-28 06:13:25.000000000","message":"LGTM","commit_id":"d2d17e43a289db20e6cc44a0ba640ce11372be4f"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"46f5b45dea6c80effb6b8528b2ba86d85d145e0a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":17,"id":"10a31d0d_5fc7ec6d","updated":"2025-01-20 12:39:05.000000000","message":"I have just rebased this change.\n\nIn the process, I made cosmetic improvements in the debug prints.\n\nPlease, if you could spare a moment to review this patch that fixes the broken register cache, I\u0027d appreciate that very much. Thank you!","commit_id":"16055c82058f59481dcc02c0cf2299fea26e933e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"577e7f95e22858f25a8bebcc9920828015cb05f2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":18,"id":"e7e5ca34_de8a9180","updated":"2025-01-20 16:18:16.000000000","message":"LGTM. Thanks!","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"83d7542085cb8520b2005c16fe97c5cc39fc2b11","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":20,"id":"8c54e2b2_4d41efee","updated":"2025-02-05 20:44:09.000000000","message":"Hi Jan,\n\nthanks for the changes. In general I have no strong opinion on this patch, only a few thoughts:\n\n - I don\u0027t know what the correct behaviour for dirty registers is. So far I was not confused by the current behaviour that dirty register values are overwritten by a force read. But it seems Antonio is fine with this new behaviour.\n - You patch changes the current behaviour and breaks force-reading of dirty registers for all targets. What about raising a warning and keep the current behaviour until we have a \u0027flush\u0027 implementation?\n - I tested your patch and it works as expected. However, there is no single implementation for register cache flushing, right? I would like the test both together (this patch + target implementation) before we merge this patch. Does this make sense?\n\nBtw, thanks for the work on the merge with the riscv-openocd fork.","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"0395e0ebb502a1d684e396875cb1b46afb4f9db2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":20,"id":"d201ec6b_101ee21e","updated":"2025-01-28 12:56:40.000000000","message":"Hi Marc, when you have a moment, could you please check re-check this review.\n\nMerging this patch will enable [follow-up fixes](https://github.com/riscv-collab/riscv-openocd/pull/1187) in the RISC-V target, which in turn brings us one step closer to being able to contribute the riscv-openocd code back to upstream.\n\nThank you.","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"e52d9fbe0271485753cf9d83ba58d75606147541","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":20,"id":"226af2d2_877ebcb0","in_reply_to":"5dfc286e_062593e7","updated":"2025-02-17 09:13:51.000000000","message":"Hello Marc,\n\nthe fact hat you haven\u0027t observed any cached values could be caused by RISC-V target automatically flushing the cache after a certain period of inactivity, see [3]. If you typed the commands manually, it is likely that the cache got auto-flushed in between the commands.\n\nYou can try e.g. executing the commands quickly one after another to see effects of the cache: `reg a0 0x1234; reg a0 force`.\n\nIf anything else occurs, feel free to let me know.\n\n[3] https://github.com/riscv-collab/riscv-openocd/blob/57b58b783288d358b6412b0600acdc15ec43b297/src/target/riscv/riscv.c#L3891","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"da8c607938a2aec6815f38be9a0f8b18ac50b422","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":20,"id":"ec7fbfec_8656a994","in_reply_to":"8c54e2b2_4d41efee","updated":"2025-02-14 11:23:24.000000000","message":"Hi Marc,\n\n\u003e  - I don\u0027t know what the correct behaviour for dirty registers is. So far I was not confused by the current behaviour that dirty register values are overwritten by a force read. But it seems Antonio is fine with this new behaviour.\n\nMy understanding is that the register cache should only serve for performance improvements (to avoid unnecessary reads/writes of registers in the hardware). Still, any sequence of register reads/writes should IMO produce the same output to the user, regardless of whether the cache is implemented for a given target, and regardless of the \"-force\" argument. Only the number of actual reads/writes from the target would be different.\n\n\u003e  - You patch changes the current behaviour and breaks force-reading of dirty registers for all targets. What about raising a warning and keep the current behaviour until we have a \u0027flush\u0027 implementation?\n\nIn our opinion, the force-reading of dirty registers is already broken now (and may cause issues to users that would be difficult to debug). For that reason, we would prefer to disallow such operation completely until proper register flush is implemented, not just warn.\n\nAnyway, depending on the review consensus, we can rework it to show just a warning. \n\n\u003e  - I tested your patch and it works as expected. However, there is no single implementation for register cache flushing, right? I would like the test both together (this patch + target implementation) before we merge this patch. Does this make sense?\n\nThank you for taking the time to test this patch.\n\nA register flush implementation for RISC-V is available in [1]. Would that be sufficient for your test? If you like, RISC-V ISA simulator Spike [2] can be used as a target for such testing.\n\n[1] https://github.com/riscv-collab/riscv-openocd/pull/1187\n[2] https://github.com/riscv-software-src/riscv-isa-sim?tab\u003dreadme-ov-file#debugging-with-gdb","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"b987b614a942dd7321baa7f6948f59dca6af501f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":20,"id":"5dfc286e_062593e7","in_reply_to":"ec7fbfec_8656a994","updated":"2025-02-16 10:19:01.000000000","message":"Okay, I have no strong opinion on raising a warning vs. error. \n\nThanks for the pointers to [1] and [2]. The spike simulator works as expected. However, I cannot see any register cache behaviour on the `riscv` target *without* your patch. In contrast to other targets, I don\u0027t see a different behaviour for `reg a0` and `reg a0 force` on `riscv`. On Cortex-M targets I can see that caching is done by a \"(cache)\" suffix in `reg`. Any idea?","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"63d204082ffa9f80dc12bec4c3966ecf1585e11c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":21,"id":"7494e70d_e3dc0c22","updated":"2025-03-14 13:22:42.000000000","message":"Polite ping to the reviewers - your approval or review comments would be appreciated.\n\nThank you.","commit_id":"bd7bcfcda5b9600b2131023e237189d86b849608"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"edbba30952c8eb10b774d48b1e0555d7641b535a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":21,"id":"b28080d4_2addbd96","in_reply_to":"7494e70d_e3dc0c22","updated":"2025-03-15 10:19:53.000000000","message":"Hi Jan,\n\nsorry, it\u0027s quite a while since I was working on this topic.\nPlease forgive me if I have lost the thread a bit.\n\n#### OpenOCD master and your patch (riscv target)\n\n`reg a0 0x1234; reg a0 force`\n\u003e a0 (/32): 0x00001234\n\n`reg a0 0xabcd; reg a0`\n\u003e a0 (/32): 0x0000abcd\n\n#### OpenOCD master (cortex_m target)\n\n`reg r0 0x1234; reg r0 force`\n\u003e r0 (/32): 0x00000000\n\n`reg r0 0xabcd; reg r0`\n\u003e r0 (/32): 0x0000abcd\n\nThis is the output for some different setups.\nThe cortex_m target behaves according to the documentation:\n\n\u003e If option \"-force\" is set, the register values are read directly from the\n\u003e target, not from OpenOCD\u0027s internal cache.\n\nIf I apply your patch than the cortex_m target does not work according to the documentation but raises an error.\n\nBtw, the flushing code you referenced [1] is not implemented in master but only in the riscv fork\n\n[1] https://github.com/riscv-collab/riscv-openocd/blob/57b58b783288d358b6412b0600acdc15ec43b297/src/target/riscv/riscv.c#L3891","commit_id":"bd7bcfcda5b9600b2131023e237189d86b849608"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d417c8853a8f5e77f76d51025521d4fb7716dcf2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":21,"id":"51f83ab2_d1b1e6d7","in_reply_to":"8c6af39c_a29176e8","updated":"2025-04-04 07:39:06.000000000","message":"Hi Marc,\nplease, have I managed to explain in a clear way what issue is this merge request trying to address? That is, a silently lost register write operation due to a force-read.\n\nThanks.","commit_id":"bd7bcfcda5b9600b2131023e237189d86b849608"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"4cb627e00884ad999a07820350e006e01c78afd2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":21,"id":"8c6af39c_a29176e8","in_reply_to":"b28080d4_2addbd96","updated":"2025-03-25 17:20:27.000000000","message":"Hi Mark, \n\nthank you for your reply. I probably misunderstood your question initially but now it appears clear to me.\n\nThe case `OpenOCD master (cortex_m target)` from your comment nicely shows the issue that this patch is trying to prevent:\n\nThe second command `reg r0 force` causes the first command `reg r0 0x1234` to get silently lost. In another words, the user asked to write a value 0x1234 into the register but that write will never happen!\n\nThe fix of this issue is a two-stage process: \n\n- Phase 1 - this patch: Rewrite of dirty cache items is prevented and flush is required. The flush callback is introduced for registers. If needed to prevent unwritten values from getting lost, but unimplemented by the given target, an error is raised (as shown in your example).\n\n- Phase 2: Individual targets should implement the flush() callback for registers. For RISC-V, this is prepared in [2].\n\n[2] https://github.com/riscv-collab/riscv-openocd/pull/1187/files#diff-73c080b97f2227b8a21559eee39f1ecebf485c1a8ae44d95fcc5f3e58e2499b9R376\n\nPlease, let me know if I managed to describe it in a clear way.","commit_id":"bd7bcfcda5b9600b2131023e237189d86b849608"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"fa51771809eabbf0826ac2f94213c11ed737e60b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":22,"id":"15de0811_f8769e72","updated":"2025-04-04 07:35:14.000000000","message":"This patch has just been rebased.","commit_id":"a65068981d520e6bf3f5aa8d794f8515dfc7cb26"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"031621fef556799169a68cd0786b3f9e5579a909","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":24,"id":"374cda98_a6de0898","updated":"2025-04-07 07:43:50.000000000","message":"Hi Jan,\n\nsorry for the late response - my time is limited and as you probably know I only do all this on the side and not full-time.\n\nI think the following example makes it very clear (from my perspective).\n\n(1) Read all registers:\n\n```\nreg\n\n\u003e ...\n\u003e (0) r0 (/32): 0x00000000  \n\u003e ...\n```\n\nCurrent value of `r0` is `0x00000000` (no cached value).\n\n(2) Change `r0` to `0xdeabeef`:\n\n```\nreg r0 0xdeadbeef\n```\n\n(3) Read all registers:\n\n```\nreg\n\n\u003e ...\n\u003e (0) r0 (/32): 0xdeadbeef (dirty)\n\u003e ...\n```\n\n`0xdeadbeef` is cached as expected.\n\n(4) Force read register `r0`:\n\n```\nreg r0 force\n\n\u003e r0 (/32): 0x00000000\n```\n\n(5) Read all registers again:\n\n```\nreg\n\n\u003e ...\n\u003e (0) r0 (/32): 0x00000000  \n\u003e ...\n```\n\nThe cached value `0xdeadbeef` is lost. That\u0027s indeed a problem / unexpected.\n\nThe current documentation says: ```If option \"-force\" is set, the register values\nare read directly from the target, bypassing any caching.```\n\nBased on the documentation I would expect that I get the register value directly from the target (**not** cache) without affecting the cached value. That\u0027s obviously not the case.\n\nIn you solution a flush operation is performed and I lose the register value on the target, correct? To be honest, I can hardly imagine any use cases for a *force read*, I never really used it actually. A real-life example would be very interesting. But if you want to make sure that the register value is flushed when you **read** it, wouldn\u0027t is make sense to have something like `reg r0 0xdeadbeef flush`? Personally I would prefer to have a dedicated `register flush` call only.\n\nSo my suggestion, based on my current understanding of the problem, would be:\n\n - Fix `force` behaviour such that cached values are not affected.\n - Add a new parameter `flush` for register read operations.\n\nDoes this make sense? I hope I have understood the problem correctly. I\u0027m not blocking anything here, just giving my personal opinion. I\u0027m probably not the most appropriate reviewer because I\u0027m not familiar with your use cases.","commit_id":"3fc81e312a0842099915f9d0b99c38c29041e652"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"cc029bbdcad547cf7f36b3045acf5dfcdfec49b2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":24,"id":"be8d6e4e_edb92c2f","updated":"2025-04-10 08:22:03.000000000","message":"Hi Marc,\n\nthank you for your response; and I do value your time spent on this, and the insights you have provided.\n\nAs for the use case -\n\nWe use the forced reads and writes for testing. During some advanced tests, \nwe wish to immediately read/write the register values from/to the target, \nbefore continuting with other operations. One example: in RISC-V, many processor\nregisters are specified as WARL (Write Any Read Legal), and forced reads \u0026 writes\nallow to check this behavior.\n\nAs for the provided suggestions -\n\n\u003e Marc: My suggestion [...] would be: Fix `force` behaviour such that cached values are not affected. [...]\n\nThat sounds OK to me. This however means that the register access API (struct reg_arch_type) would need to be extended: a new API call will need to be added, called e.g. `get_nocache()`.\n\n\u003e Marc: Add a new parameter `flush` for register read operations.\n\nI am not in favor of adding a `flush` parameter to the register read commands because it seems quite complicated for the users.\nOn the other hand, I like the idea of having dedicated register flush commands. This would allow the users\nto control the register cache if they need so. Something along these lines:\n\n```\n# Flush (and optionally invalidate) a single register:\nreg_flush [-invalidate] \u003cregister_name\u003e\n\n# Flush (and optionally invalidate) all registers of the given target:\nreg_flush_all [-invalidate]\n```\n\n\nTo summarize, I can see three options how to proceed:\n\n1) As implemented in this patch: Automatically flush dirty registers before force-read. Also add `-force` flag to `set_reg` command. \n\n2) Create a new patch: Implement the `reg_flush` commands for register cache control. Change the `-force` option of `get_reg` and `reg` to not affect the cache. Requires extension of the target API (struct reg_arch_type).\n\n3) Create a new patch: Implement the `reg_flush` commands for register cache control. Deprecate (and later remove) the `-force` option of `get_reg` and `reg`. \nUsers can achieve the same behavior by calling `flush_reg` before `get_reg`: `flush_reg -invalidate reg_name ; get_reg reg_name`.\n\n\nEither of the options is in my opinion fine and addresses the current issues, which are:\n- User has no control of the register cache\n- Register write followed by force-read causes the (dirty) written value to get dropped from cache\n\nI am happy to prepare either of these options, but would like to get opinions from other reviewers before I embark on it :-)\n\nThank you!","commit_id":"3fc81e312a0842099915f9d0b99c38c29041e652"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"bf679679a7db770582ab07abbaff74e339c25ba0","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":24,"id":"44f61273_9cbb596c","updated":"2025-04-17 15:39:48.000000000","message":"Let me start saying that I agree with the purpose of this patch to have a `force` flag to flush and/or invalidate the register cache.\n\nThen, I have spent some time to check the use of `reg_arch_type::get() \u0026 set()` in the different targets. Quite a complicated situation.\n\nEvery target has its own implementation, sometimes even two different implementations in the same target (see on cortex-m `armv7m_reg_type` and `dwt_reg_type`).\nOn riscv both get\u0026set read/write directly in the target; on cortex-m get() reads from target while set() only updates the register cache; on stm8 both get\u0026set work on the register cache only!\nThis probably explains the results from Marc\u0027s tests.\n\nI think that adding the new API `flush` and `invalidate`, without uniforming the targets, risks to make the implementation diverging and/or even more confused.\n\nPlus, I read in Jan\u0027s comment that `The cache is here only for performance optimization`. Not true! On Cortex-A and AArch64 the register R0 is used to read/write either the other registers and the memory. And for wider data (e.g. floating point) both R0 and R1 are used. The register cache keeps the old values of R0 and R1 when they get dirty during the operation above.\nSo the implementation of `target_flush_all_regs_default()` is broken for Cortex-A and AArch64 because it flushes R0 as first, but then flushing the other registers it causes R0 to become dirty! At least these two targets need a dedicated implementation.\n\nI think we need a cleanup in the handling of registers and register\u0027s cache.\nI would like to see more centralized and common code in `target.c` and `register.c`, reducing the target specific code.\n\nClearly, I cannot request you to fix all the targets. I don\u0027t think anyone here (me included) has the knowledge on all the supported targets, nor has the HW to test all the targets.\n\nBut, could we approach this differently?\n\nWhat about starting with a first patch to clearly document the API we plan to introduce and their expected behavior?\nIn `doc/manual/target.txt` we have an empty chapter `targetregister`.\nIn `src/target/register.h` there is not a single doxygen comment.\nOnce we agree on this, we could plan the coding and testing activity.","commit_id":"3fc81e312a0842099915f9d0b99c38c29041e652"}],"doc/openocd.texi":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":9056,"context_line":"by using @command{targets} command with the name of the"},{"line_number":9057,"context_line":"target which should become current."},{"line_number":9058,"context_line":""},{"line_number":9059,"context_line":"@deffn {Command} {reg} [(number|name) [(value [\u0027force\u0027]|\u0027force\u0027)]]"},{"line_number":9060,"context_line":"Access a single register by @var{number} or by its @var{name}."},{"line_number":9061,"context_line":"The target must generally be halted before access to CPU core"},{"line_number":9062,"context_line":"registers is allowed. Depending on the hardware, some other"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"24fe483b_885d156f","line":9059,"updated":"2024-01-30 15:33:34.000000000","message":"Please, consider simplifying the syntax of the command (in both the documentation and in the `.help` string):\n\n`@deffn {Command} {reg} [(number|name) [value] [\u0027force\u0027]`","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":9056,"context_line":"by using @command{targets} command with the name of the"},{"line_number":9057,"context_line":"target which should become current."},{"line_number":9058,"context_line":""},{"line_number":9059,"context_line":"@deffn {Command} {reg} [(number|name) [(value [\u0027force\u0027]|\u0027force\u0027)]]"},{"line_number":9060,"context_line":"Access a single register by @var{number} or by its @var{name}."},{"line_number":9061,"context_line":"The target must generally be halted before access to CPU core"},{"line_number":9062,"context_line":"registers is allowed. Depending on the hardware, some other"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"80224b63_ae75f14d","line":9059,"in_reply_to":"24fe483b_885d156f","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":9056,"context_line":"by using @command{targets} command with the name of the"},{"line_number":9057,"context_line":"target which should become current."},{"line_number":9058,"context_line":""},{"line_number":9059,"context_line":"@deffn {Command} {reg} [(number|name) [(value [\u0027force\u0027]|\u0027force\u0027)]]"},{"line_number":9060,"context_line":"Access a single register by @var{number} or by its @var{name}."},{"line_number":9061,"context_line":"The target must generally be halted before access to CPU core"},{"line_number":9062,"context_line":"registers is allowed. Depending on the hardware, some other"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"55da3054_582df96f","line":9059,"in_reply_to":"80224b63_ae75f14d","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":9080,"context_line":"(including by single stepping) or otherwise activating the"},{"line_number":9081,"context_line":"relevant module will flush such values. Use @var{force}"},{"line_number":9082,"context_line":"to also flush the register immediately if the target caches"},{"line_number":9083,"context_line":"the register."},{"line_number":9084,"context_line":""},{"line_number":9085,"context_line":"Cores may have surprisingly many registers in their"},{"line_number":9086,"context_line":"Debug and trace infrastructure:"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"48492c78_f6f3f454","line":9083,"updated":"2024-01-30 15:33:34.000000000","message":"If you like:\n\nThe use of @var{force} also causes a cached register value (if it is dirty - unwritten) to be written back to the target prior to the read.","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":9080,"context_line":"(including by single stepping) or otherwise activating the"},{"line_number":9081,"context_line":"relevant module will flush such values. Use @var{force}"},{"line_number":9082,"context_line":"to also flush the register immediately if the target caches"},{"line_number":9083,"context_line":"the register."},{"line_number":9084,"context_line":""},{"line_number":9085,"context_line":"Cores may have surprisingly many registers in their"},{"line_number":9086,"context_line":"Debug and trace infrastructure:"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"5b5688f7_985396d1","line":9083,"in_reply_to":"3699cff2_dfa097f2","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":9080,"context_line":"(including by single stepping) or otherwise activating the"},{"line_number":9081,"context_line":"relevant module will flush such values. Use @var{force}"},{"line_number":9082,"context_line":"to also flush the register immediately if the target caches"},{"line_number":9083,"context_line":"the register."},{"line_number":9084,"context_line":""},{"line_number":9085,"context_line":"Cores may have surprisingly many registers in their"},{"line_number":9086,"context_line":"Debug and trace infrastructure:"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"3699cff2_dfa097f2","line":9083,"in_reply_to":"48492c78_f6f3f454","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":9097,"context_line":"@end example"},{"line_number":9098,"context_line":"@end deffn"},{"line_number":9099,"context_line":""},{"line_number":9100,"context_line":"@deffn {Command} {set_reg} [\u0027-force\u0027 [\u0027-invalidate\u0027]] dict"},{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"1c9e54cb_73d66484","line":9100,"updated":"2024-01-30 15:33:34.000000000","message":"I believe the invalidation is not implemented in set_reg, just the `-force`. Please, remove it from the doc.","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":9097,"context_line":"@end example"},{"line_number":9098,"context_line":"@end deffn"},{"line_number":9099,"context_line":""},{"line_number":9100,"context_line":"@deffn {Command} {set_reg} [\u0027-force\u0027 [\u0027-invalidate\u0027]] dict"},{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"c56defa3_3d02087f","line":9100,"in_reply_to":"1c9e54cb_73d66484","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":9097,"context_line":"@end example"},{"line_number":9098,"context_line":"@end deffn"},{"line_number":9099,"context_line":""},{"line_number":9100,"context_line":"@deffn {Command} {set_reg} [\u0027-force\u0027 [\u0027-invalidate\u0027]] dict"},{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"}],"source_content_type":"text/x-texinfo","patch_set":6,"id":"859c4ffa_615ae5e3","line":9100,"in_reply_to":"c56defa3_3d02087f","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"},{"line_number":9104,"context_line":"@item @var{\u0027-force\u0027} ... Flush all set registers"},{"line_number":9105,"context_line":"@item @var{dict} ... Tcl dictionary with pairs of register names and values."},{"line_number":9106,"context_line":"@end itemize"},{"line_number":9107,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":12,"id":"a808718b_1abd3f44","line":9104,"updated":"2024-02-18 10:41:02.000000000","message":"you should use\n```\n@item @option{-force) ...\n```\nwe need to find a way to automatically check and fix the syntax of this file, but at first we need to clearly state the desired syntax.\nSorry for bothering on this","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"},{"line_number":9104,"context_line":"@item @var{\u0027-force\u0027} ... Flush all set registers"},{"line_number":9105,"context_line":"@item @var{dict} ... Tcl dictionary with pairs of register names and values."},{"line_number":9106,"context_line":"@end itemize"},{"line_number":9107,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":12,"id":"aeb6c31d_a7e797b0","line":9104,"in_reply_to":"a808718b_1abd3f44","updated":"2024-02-20 14:47:15.000000000","message":"It\u0027s fine. Thanks for telling me the correct syntax.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":9133,"context_line":""},{"line_number":9134,"context_line":"@deffn {Command} {flush_reg_cache} [-invalidate]"},{"line_number":9135,"context_line":"Flush the internal OpenOCD\u0027s register cache - write back the dirty register values to the target."},{"line_number":9136,"context_line":"If -invalidate is set, also invalidate (forget) the OpenOCD\u0027s cached register values; therefore the next"},{"line_number":9137,"context_line":"call to get_reg is guaranteed to read the fresh register value directly from the target."},{"line_number":9138,"context_line":"@end deffn"},{"line_number":9139,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":12,"id":"0454e922_23ccdcf1","line":9136,"updated":"2024-02-18 10:41:02.000000000","message":"please use\n```\nIf @option{-invalidate} is set, ...\n```","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":9133,"context_line":""},{"line_number":9134,"context_line":"@deffn {Command} {flush_reg_cache} [-invalidate]"},{"line_number":9135,"context_line":"Flush the internal OpenOCD\u0027s register cache - write back the dirty register values to the target."},{"line_number":9136,"context_line":"If -invalidate is set, also invalidate (forget) the OpenOCD\u0027s cached register values; therefore the next"},{"line_number":9137,"context_line":"call to get_reg is guaranteed to read the fresh register value directly from the target."},{"line_number":9138,"context_line":"@end deffn"},{"line_number":9139,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":12,"id":"c2a5d4ed_27e19c9b","line":9136,"in_reply_to":"0454e922_23ccdcf1","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5901b9f22dc6b0e061193cae7a031e59f04bb5dd","unresolved":true,"context_lines":[{"line_number":9080,"context_line":"(including by single stepping) or otherwise activating the"},{"line_number":9081,"context_line":"relevant module will flush such values. The use of @var{force}"},{"line_number":9082,"context_line":"also causes a cached register value (if it is dirty - unwritten)"},{"line_number":9083,"context_line":"to be written back to the target prior to the read."},{"line_number":9084,"context_line":""},{"line_number":9085,"context_line":"Cores may have surprisingly many registers in their"},{"line_number":9086,"context_line":"Debug and trace infrastructure:"}],"source_content_type":"text/x-texinfo","patch_set":15,"id":"5885782c_03551d9f","line":9083,"updated":"2024-03-01 06:36:45.000000000","message":"Just a detail in the doc: I believe it is important for clarity to say that the \"force\" argument causes immediate flush.\n\n```\nThe use of @var{force} causes the register value to be \nwritten to the target (flushed) immediately.\n```","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"0db29e78269339ff1d927d1a25e7360ea7020e14","unresolved":false,"context_lines":[{"line_number":9080,"context_line":"(including by single stepping) or otherwise activating the"},{"line_number":9081,"context_line":"relevant module will flush such values. The use of @var{force}"},{"line_number":9082,"context_line":"also causes a cached register value (if it is dirty - unwritten)"},{"line_number":9083,"context_line":"to be written back to the target prior to the read."},{"line_number":9084,"context_line":""},{"line_number":9085,"context_line":"Cores may have surprisingly many registers in their"},{"line_number":9086,"context_line":"Debug and trace infrastructure:"}],"source_content_type":"text/x-texinfo","patch_set":15,"id":"6edbd22e_9a70f3ad","line":9083,"in_reply_to":"5885782c_03551d9f","updated":"2024-05-24 13:46:15.000000000","message":"(resolved myself)","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5901b9f22dc6b0e061193cae7a031e59f04bb5dd","unresolved":true,"context_lines":[{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"},{"line_number":9104,"context_line":"@item @option{-force} ... Flush all set registers"},{"line_number":9105,"context_line":"@item @var{dict} ... Tcl dictionary with pairs of register names and values."},{"line_number":9106,"context_line":"@end itemize"},{"line_number":9107,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":15,"id":"06c77654_b242bd93","line":9104,"updated":"2024-03-01 06:36:45.000000000","message":"Proposed wording for improved clarity:\n\n```\n@item @option{-force} ... Write (flush) the register values to the target immediately\n\n```","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"0db29e78269339ff1d927d1a25e7360ea7020e14","unresolved":false,"context_lines":[{"line_number":9101,"context_line":"Set register values of the target."},{"line_number":9102,"context_line":""},{"line_number":9103,"context_line":"@itemize"},{"line_number":9104,"context_line":"@item @option{-force} ... Flush all set registers"},{"line_number":9105,"context_line":"@item @var{dict} ... Tcl dictionary with pairs of register names and values."},{"line_number":9106,"context_line":"@end itemize"},{"line_number":9107,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":15,"id":"cd36c835_dc1c2a10","line":9104,"in_reply_to":"06c77654_b242bd93","updated":"2024-05-24 13:46:15.000000000","message":"(resolved myself)","commit_id":"b44d1647e6ac6f66f586afe532c35a62cab004dc"}],"src/target/register.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":141,"context_line":"\t}"},{"line_number":142,"context_line":""},{"line_number":143,"context_line":"\tif (!reg-\u003eexist) {"},{"line_number":144,"context_line":"\t\tLOG_ERROR(\"BUG: %s caled with non-existent register!\", __func__);"},{"line_number":145,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":146,"context_line":"\t}"},{"line_number":147,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":12,"id":"6958c28a_73696c41","line":144,"updated":"2024-02-18 10:41:02.000000000","message":"typo s/caled/called/","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":141,"context_line":"\t}"},{"line_number":142,"context_line":""},{"line_number":143,"context_line":"\tif (!reg-\u003eexist) {"},{"line_number":144,"context_line":"\t\tLOG_ERROR(\"BUG: %s caled with non-existent register!\", __func__);"},{"line_number":145,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":146,"context_line":"\t}"},{"line_number":147,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":12,"id":"f25d1d54_6f7fd36a","line":144,"in_reply_to":"6958c28a_73696c41","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":158,"context_line":"\t\tLOG_ERROR(\"Unable to flush dirty register \u0027%s\u0027, operation is not supported\", reg-\u003ename);"},{"line_number":159,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":160,"context_line":"\t}"},{"line_number":161,"context_line":""},{"line_number":162,"context_line":"\tif (!reg-\u003evalid) {"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"7130bf29_c5148bcd","line":159,"updated":"2024-02-18 10:41:02.000000000","message":"ERROR_NOT_IMPLEMENTED ?","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":156,"context_line":""},{"line_number":157,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":158,"context_line":"\t\tLOG_ERROR(\"Unable to flush dirty register \u0027%s\u0027, operation is not supported\", reg-\u003ename);"},{"line_number":159,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":160,"context_line":"\t}"},{"line_number":161,"context_line":""},{"line_number":162,"context_line":"\tif (!reg-\u003evalid) {"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"1fd456b1_57114d70","line":159,"in_reply_to":"7130bf29_c5148bcd","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"83d7542085cb8520b2005c16fe97c5cc39fc2b11","unresolved":true,"context_lines":[{"line_number":157,"context_line":"\t}"},{"line_number":158,"context_line":""},{"line_number":159,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":160,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush dirty register \u0027%s\u0027. OpenOCD does not implement \""},{"line_number":161,"context_line":"\t\t\t\"this operation on %s architecture yet.\", reg-\u003ename, target-\u003etype-\u003ename);"},{"line_number":162,"context_line":"\t\treturn ERROR_NOT_IMPLEMENTED;"},{"line_number":163,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":20,"id":"a08f7bfc_63c8d211","line":160,"updated":"2025-02-05 20:44:09.000000000","message":"Please make this message consistent with the one in target.c:1467 used for the same check. No need for two sentences.","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"da8c607938a2aec6815f38be9a0f8b18ac50b422","unresolved":false,"context_lines":[{"line_number":157,"context_line":"\t}"},{"line_number":158,"context_line":""},{"line_number":159,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":160,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush dirty register \u0027%s\u0027. OpenOCD does not implement \""},{"line_number":161,"context_line":"\t\t\t\"this operation on %s architecture yet.\", reg-\u003ename, target-\u003etype-\u003ename);"},{"line_number":162,"context_line":"\t\treturn ERROR_NOT_IMPLEMENTED;"},{"line_number":163,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":20,"id":"a941f78d_a0f1a24d","line":160,"in_reply_to":"a08f7bfc_63c8d211","updated":"2025-02-14 11:23:24.000000000","message":"Done - I have just updated the message.","commit_id":"f5dd4a3cdebd5ff0d5e3fb07b53a6f7689f10383"}],"src/target/target.c":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":1503,"context_line":""},{"line_number":1504,"context_line":"\tLOG_TARGET_DEBUG(target, \"Found %u dirty registers out of %u all registers.\", dirty_count, total_count);"},{"line_number":1505,"context_line":"\tif (failed_count \u003e 0)"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_WARNING(target, \"Failed to flush %u registers out of %u dirty registers.\","},{"line_number":1507,"context_line":"\t\t\tfailed_count, dirty_count);"},{"line_number":1508,"context_line":"\telse"},{"line_number":1509,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"All dirty registers flushed.\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4c71611a_e155ae71","line":1506,"updated":"2024-01-30 15:33:34.000000000","message":"If you like, the sentence can be simplified:\n`\"Failed to flush %u out of %u dirty registers.\"`","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":1503,"context_line":""},{"line_number":1504,"context_line":"\tLOG_TARGET_DEBUG(target, \"Found %u dirty registers out of %u all registers.\", dirty_count, total_count);"},{"line_number":1505,"context_line":"\tif (failed_count \u003e 0)"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_WARNING(target, \"Failed to flush %u registers out of %u dirty registers.\","},{"line_number":1507,"context_line":"\t\t\tfailed_count, dirty_count);"},{"line_number":1508,"context_line":"\telse"},{"line_number":1509,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"All dirty registers flushed.\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"e919dd03_288f7035","line":1506,"in_reply_to":"2eaed36c_92a6e631","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":1503,"context_line":""},{"line_number":1504,"context_line":"\tLOG_TARGET_DEBUG(target, \"Found %u dirty registers out of %u all registers.\", dirty_count, total_count);"},{"line_number":1505,"context_line":"\tif (failed_count \u003e 0)"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_WARNING(target, \"Failed to flush %u registers out of %u dirty registers.\","},{"line_number":1507,"context_line":"\t\t\tfailed_count, dirty_count);"},{"line_number":1508,"context_line":"\telse"},{"line_number":1509,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"All dirty registers flushed.\");"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"2eaed36c_92a6e631","line":1506,"in_reply_to":"4c71611a_e155ae71","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"},{"line_number":1543,"context_line":"\t\tLOG_TARGET_ERROR(target, \"BUG: Register \u0027%s\u0027 dirty after flushing!\", reg-\u003ename);"},{"line_number":1544,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1545,"context_line":"\t}"},{"line_number":1546,"context_line":"\tif (reg-\u003evalid \u0026\u0026 invalidate) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"06b02646_cec171f5","line":1543,"updated":"2024-01-30 15:33:34.000000000","message":"If you like:\n\n`BUG: Register \u0027%s\u0027 remained dirty after flushing!`","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"},{"line_number":1543,"context_line":"\t\tLOG_TARGET_ERROR(target, \"BUG: Register \u0027%s\u0027 dirty after flushing!\", reg-\u003ename);"},{"line_number":1544,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1545,"context_line":"\t}"},{"line_number":1546,"context_line":"\tif (reg-\u003evalid \u0026\u0026 invalidate) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"996ce33e_8346739a","line":1543,"in_reply_to":"06b02646_cec171f5","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"},{"line_number":1543,"context_line":"\t\tLOG_TARGET_ERROR(target, \"BUG: Register \u0027%s\u0027 dirty after flushing!\", reg-\u003ename);"},{"line_number":1544,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1545,"context_line":"\t}"},{"line_number":1546,"context_line":"\tif (reg-\u003evalid \u0026\u0026 invalidate) {"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"3c5cfed2_6fe07d5a","line":1543,"in_reply_to":"996ce33e_8346739a","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"16ae10ad085365773e2ac879ae5e6285916141ef","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3201,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3202,"context_line":"\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"},{"line_number":3203,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"11130301_57914c13","line":3200,"updated":"2024-01-30 15:33:34.000000000","message":"The flush should only be called under this condition: `if (reg-\u003evalid \u0026\u0026 reg-\u003edirty)`. Please, wrap the block by this additional \"if\". \n\nIn set_reg below, this case is already handled correctly.","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"abbae336f9ebf5a81b76d804d48c735a4dff7fed","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3201,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3202,"context_line":"\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"},{"line_number":3203,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4e1238c8_562b1231","line":3200,"in_reply_to":"11130301_57914c13","updated":"2024-01-30 15:57:55.000000000","message":"Done","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f9738d272c23960429f551e7654eeb4c3c11bc59","unresolved":false,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3201,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3202,"context_line":"\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"},{"line_number":3203,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"a73518c8_3a9c8250","line":3200,"in_reply_to":"4e1238c8_562b1231","updated":"2024-01-30 15:59:14.000000000","message":"Ack","commit_id":"1c901976df0c6fac55b5b800c7df37bfca4968bd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1464,"context_line":"\treturn 32;"},{"line_number":1465,"context_line":"}"},{"line_number":1466,"context_line":""},{"line_number":1467,"context_line":"static int target_flush_all_regs(struct target *target, bool invalidate)"},{"line_number":1468,"context_line":"{"},{"line_number":1469,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1470,"context_line":"\tunsigned int total_count \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"1b47c980_4ded9fd1","line":1467,"updated":"2024-01-31 10:50:20.000000000","message":"`struct target *` can be `const` here.\n\nThere is also a minor concern about the order in which the registers are flushed:\nWriting some registers can clobber other registers (e.g. for RISC-V targets writing FPRs/CSRs via program buffer will result in a clobbered `S0`/`S1`, so, for all registers to be clean after flush these GPRs should be flushed last). Therefore it may be beneficial to leave the implementation here as a default, but provide an option for a target to specify target-specific `flush_all_regs()`.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":1464,"context_line":"\treturn 32;"},{"line_number":1465,"context_line":"}"},{"line_number":1466,"context_line":""},{"line_number":1467,"context_line":"static int target_flush_all_regs(struct target *target, bool invalidate)"},{"line_number":1468,"context_line":"{"},{"line_number":1469,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1470,"context_line":"\tunsigned int total_count \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"6289e140_9aa48860","line":1467,"in_reply_to":"1b47c980_4ded9fd1","updated":"2024-02-01 12:00:30.000000000","message":"Added flush_all_regs function with a default to target_type.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1504,"context_line":"\tLOG_TARGET_DEBUG(target, \"Found %u dirty registers out of %u all registers.\", dirty_count, total_count);"},{"line_number":1505,"context_line":"\tif (failed_count \u003e 0)"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_WARNING(target, \"Failed to flush %u out of %u dirty registers.\","},{"line_number":1507,"context_line":"\t\t\tfailed_count, dirty_count);"},{"line_number":1508,"context_line":"\telse"},{"line_number":1509,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"All dirty registers flushed.\");"},{"line_number":1510,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"2ef2196c_02d31842","line":1507,"updated":"2024-01-31 10:50:20.000000000","message":"Shouldn\u0027t an `ERROR_FAIL` be returned here?","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":1504,"context_line":"\tLOG_TARGET_DEBUG(target, \"Found %u dirty registers out of %u all registers.\", dirty_count, total_count);"},{"line_number":1505,"context_line":"\tif (failed_count \u003e 0)"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_WARNING(target, \"Failed to flush %u out of %u dirty registers.\","},{"line_number":1507,"context_line":"\t\t\tfailed_count, dirty_count);"},{"line_number":1508,"context_line":"\telse"},{"line_number":1509,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"All dirty registers flushed.\");"},{"line_number":1510,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"e686dec5_2d85dcf3","line":1507,"in_reply_to":"2ef2196c_02d31842","updated":"2024-02-01 12:00:30.000000000","message":"Thanks for the suggestion. Putting ERROR_FAIL there and LOG_TARGET_ERROR here.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1511,"context_line":"\treturn ERROR_OK;"},{"line_number":1512,"context_line":"}"},{"line_number":1513,"context_line":""},{"line_number":1514,"context_line":"static int target_flush_reg(const struct target *target, const char *reg_name, bool invalidate)"},{"line_number":1515,"context_line":"{"},{"line_number":1516,"context_line":"\tstruct reg *reg \u003d register_get_by_name(target-\u003ereg_cache, reg_name, true);"},{"line_number":1517,"context_line":"\tif (!reg) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"c03c2f52_2603b625","line":1514,"updated":"2024-01-31 10:50:20.000000000","message":"As far as I understand, the function is only used like so:\n```\nint result \u003d target_flush_reg(target, reg-\u003ename, ...)\n```\nI would suggest accepting `struct reg` directly as a parameter instead of `target` and `name` pair and moving the function to `register.c`\n```\nstatic int register_flush(struct reg *reg, bool invalidate)\n```\nThis would allow to replace the check `if (!reg)` with an assertion and eliminate the need to search for the register twice.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":1511,"context_line":"\treturn ERROR_OK;"},{"line_number":1512,"context_line":"}"},{"line_number":1513,"context_line":""},{"line_number":1514,"context_line":"static int target_flush_reg(const struct target *target, const char *reg_name, bool invalidate)"},{"line_number":1515,"context_line":"{"},{"line_number":1516,"context_line":"\tstruct reg *reg \u003d register_get_by_name(target-\u003ereg_cache, reg_name, true);"},{"line_number":1517,"context_line":"\tif (!reg) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"d0f14657_f91715d2","line":1514,"in_reply_to":"c03c2f52_2603b625","updated":"2024-02-01 12:00:30.000000000","message":"Done","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c8b51c6f07a2c1d7ca5327c0fad08a9d3e821a25","unresolved":true,"context_lines":[{"line_number":1511,"context_line":"\treturn ERROR_OK;"},{"line_number":1512,"context_line":"}"},{"line_number":1513,"context_line":""},{"line_number":1514,"context_line":"static int target_flush_reg(const struct target *target, const char *reg_name, bool invalidate)"},{"line_number":1515,"context_line":"{"},{"line_number":1516,"context_line":"\tstruct reg *reg \u003d register_get_by_name(target-\u003ereg_cache, reg_name, true);"},{"line_number":1517,"context_line":"\tif (!reg) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"d8da120b_1ec36df1","line":1514,"in_reply_to":"d0f14657_f91715d2","updated":"2024-02-01 12:49:35.000000000","message":"I think it would be better to move the function to `register.c`","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[{"line_number":1511,"context_line":"\treturn ERROR_OK;"},{"line_number":1512,"context_line":"}"},{"line_number":1513,"context_line":""},{"line_number":1514,"context_line":"static int target_flush_reg(const struct target *target, const char *reg_name, bool invalidate)"},{"line_number":1515,"context_line":"{"},{"line_number":1516,"context_line":"\tstruct reg *reg \u003d register_get_by_name(target-\u003ereg_cache, reg_name, true);"},{"line_number":1517,"context_line":"\tif (!reg) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"c46e700a_9ace3d01","line":1514,"in_reply_to":"d8da120b_1ec36df1","updated":"2024-02-01 13:11:40.000000000","message":"Moved it","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1523,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Flushing of register \u0027%s\u0027 is not supported\", reg-\u003ename);"},{"line_number":1524,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1525,"context_line":"\t}"},{"line_number":1526,"context_line":""},{"line_number":1527,"context_line":"\tif (!reg-\u003evalid) {"},{"line_number":1528,"context_line":"\t\tLOG_TARGET_ERROR(target, \"BUG: Register \u0027%s\u0027 is not valid, but flush attempted.\", reg-\u003ename);"},{"line_number":1529,"context_line":"\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"1de6940a_80ede7ed","line":1526,"updated":"2024-01-31 10:50:20.000000000","message":"`reg-\u003eexist` should be checked/asserted here.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":1523,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Flushing of register \u0027%s\u0027 is not supported\", reg-\u003ename);"},{"line_number":1524,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1525,"context_line":"\t}"},{"line_number":1526,"context_line":""},{"line_number":1527,"context_line":"\tif (!reg-\u003evalid) {"},{"line_number":1528,"context_line":"\t\tLOG_TARGET_ERROR(target, \"BUG: Register \u0027%s\u0027 is not valid, but flush attempted.\", reg-\u003ename);"},{"line_number":1529,"context_line":"\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"9e4ebcac_f5d9c25f","line":1526,"in_reply_to":"1de6940a_80ede7ed","updated":"2024-02-01 12:00:30.000000000","message":"Done","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1529,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1530,"context_line":"\t}"},{"line_number":1531,"context_line":"\tif (!reg-\u003edirty) {"},{"line_number":1532,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"Register \u0027%s\u0027 is not dirty, nothing to flush.\", reg-\u003ename);"},{"line_number":1533,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1534,"context_line":"\t}"},{"line_number":1535,"context_line":"\tLOG_TARGET_DEBUG(target, \"Flushing register \u0027%s\u0027.\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"280cc8ad_1b1203fa","line":1532,"updated":"2024-01-31 10:50:20.000000000","message":"The register still needs to be invalidated here if `invalidate` is set.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":1529,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1530,"context_line":"\t}"},{"line_number":1531,"context_line":"\tif (!reg-\u003edirty) {"},{"line_number":1532,"context_line":"\t\tLOG_TARGET_DEBUG(target, \"Register \u0027%s\u0027 is not dirty, nothing to flush.\", reg-\u003ename);"},{"line_number":1533,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1534,"context_line":"\t}"},{"line_number":1535,"context_line":"\tLOG_TARGET_DEBUG(target, \"Flushing register \u0027%s\u0027.\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"6bde143d_eed52431","line":1532,"in_reply_to":"280cc8ad_1b1203fa","updated":"2024-02-01 12:00:30.000000000","message":"Done","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":1536,"context_line":""},{"line_number":1537,"context_line":"\tint result \u003d reg-\u003etype-\u003eflush(reg);"},{"line_number":1538,"context_line":"\tif (result !\u003d ERROR_OK) {"},{"line_number":1539,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027\", reg-\u003ename);"},{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"1ddd115e_c659658c","line":1539,"updated":"2024-01-31 10:50:20.000000000","message":"I think it is beneficial to require from `reg-\u003etype-\u003eflush()` to invalidate a register if it fails. Therefore, I would suggest to add an assertion here:\n```\nassert(!reg-\u003evalid \u0026\u0026 !reg-\u003edirty);\n```","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":true,"context_lines":[{"line_number":1536,"context_line":""},{"line_number":1537,"context_line":"\tint result \u003d reg-\u003etype-\u003eflush(reg);"},{"line_number":1538,"context_line":"\tif (result !\u003d ERROR_OK) {"},{"line_number":1539,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027\", reg-\u003ename);"},{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"c70db1d4_20da7c83","line":1539,"in_reply_to":"1ddd115e_c659658c","updated":"2024-02-01 12:00:30.000000000","message":"I would prefer not to do it for the following reason:\n\nDirty means write is pending (postponed write). If the write (flush) fails, I believe we shouldn\u0027t forget about the pending write. And should retry later (keep the register dirty).\n\nI would leave this up to the target to decide what to do in those cases. But preferably the target should not invalidate it for the reason already explained.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c8b51c6f07a2c1d7ca5327c0fad08a9d3e821a25","unresolved":false,"context_lines":[{"line_number":1536,"context_line":""},{"line_number":1537,"context_line":"\tint result \u003d reg-\u003etype-\u003eflush(reg);"},{"line_number":1538,"context_line":"\tif (result !\u003d ERROR_OK) {"},{"line_number":1539,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027\", reg-\u003ename);"},{"line_number":1540,"context_line":"\t\treturn result;"},{"line_number":1541,"context_line":"\t}"},{"line_number":1542,"context_line":"\tif (reg-\u003edirty) {"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"fe0fa90f_68826303","line":1539,"in_reply_to":"c70db1d4_20da7c83","updated":"2024-02-01 12:49:35.000000000","message":"Thank you for the explanation. You are right.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":3201,"context_line":"\t\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3202,"context_line":"\t\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3203,"context_line":"\t\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"d67e3023_9f89f797","line":3200,"updated":"2024-01-31 10:50:20.000000000","message":"I would suggest to move the\n```\nif (!reg-\u003edirty)\n   return ERROR_OK;\n```\nin front of the\n```\nif (!reg-\u003etype-\u003eflush(...))\n```\nin `target_flush_reg()`.\nThis would allow to eliminate the if/else here.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"2f7876ee9dc79512848f337559dde786d7fbecd7","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":3201,"context_line":"\t\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3202,"context_line":"\t\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3203,"context_line":"\t\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"b95fc58a_e45a49d1","line":3200,"in_reply_to":"538193e7_57cc2743","updated":"2024-02-01 12:51:26.000000000","message":"Please, see the [comment with the clarification](https://review.openocd.org/c/openocd/+/8070/comment/c177b4b1_4262e94a/)","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c8b51c6f07a2c1d7ca5327c0fad08a9d3e821a25","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":3201,"context_line":"\t\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3202,"context_line":"\t\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3203,"context_line":"\t\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"538193e7_57cc2743","line":3200,"in_reply_to":"883154be_4993f05a","updated":"2024-02-01 12:49:35.000000000","message":"Not exactly, the `if` can be eliminated, though it requires adjusting `register_flush()` a bit.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":3201,"context_line":"\t\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3202,"context_line":"\t\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3203,"context_line":"\t\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"62805bc2_4ccaf57a","line":3200,"in_reply_to":"b95fc58a_e45a49d1","updated":"2024-02-01 13:11:40.000000000","message":"Yes, thanks for noticing.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":true,"context_lines":[{"line_number":3197,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3198,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3199,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0)) {"},{"line_number":3200,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":3201,"context_line":"\t\t\t\tint retval \u003d target_flush_reg(target, reg-\u003ename, true);"},{"line_number":3202,"context_line":"\t\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3203,"context_line":"\t\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"883154be_4993f05a","line":3200,"in_reply_to":"d67e3023_9f89f797","updated":"2024-02-01 12:00:30.000000000","message":"I assume you mean a different part of the code? I cannot return ERROR_OK right in here as the function continues.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":3228,"context_line":"\t\tif (CMD_ARGC \u003e\u003d 3 \u0026\u0026 !strcmp(CMD_ARGV[2], \"force\")) {"},{"line_number":3229,"context_line":"\t\t\tflush \u003d true;"},{"line_number":3230,"context_line":"\t\t} else if (CMD_ARGC \u003e\u003d 3) {"},{"line_number":3231,"context_line":"\t\t\tLOG_TARGET_ERROR(target, \"Invalid argument: \u0027%s\u0027\", CMD_ARGV[2]);"},{"line_number":3232,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":3233,"context_line":"\t\t}"},{"line_number":3234,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"b2dbaa1e_a0d3e9b9","line":3231,"updated":"2024-01-31 10:50:20.000000000","message":"There is no need for `LOG_TARGET_ERROR(...)` if `ERROR_COMMAND_SYNTAX_ERROR` is returned. Usage is reported automatically.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":3228,"context_line":"\t\tif (CMD_ARGC \u003e\u003d 3 \u0026\u0026 !strcmp(CMD_ARGV[2], \"force\")) {"},{"line_number":3229,"context_line":"\t\t\tflush \u003d true;"},{"line_number":3230,"context_line":"\t\t} else if (CMD_ARGC \u003e\u003d 3) {"},{"line_number":3231,"context_line":"\t\t\tLOG_TARGET_ERROR(target, \"Invalid argument: \u0027%s\u0027\", CMD_ARGV[2]);"},{"line_number":3232,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":3233,"context_line":"\t\t}"},{"line_number":3234,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"29a9157a_4165b951","line":3231,"in_reply_to":"b2dbaa1e_a0d3e9b9","updated":"2024-02-01 12:00:30.000000000","message":"Removed.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":3248,"context_line":"\t\t\tfree(value);"},{"line_number":3249,"context_line":"\t\t}"},{"line_number":3250,"context_line":""},{"line_number":3251,"context_line":"\t\t// If target has no cache, dirty should never be set to true"},{"line_number":3252,"context_line":"\t\tif (reg-\u003edirty \u0026\u0026 flush)"},{"line_number":3253,"context_line":"\t\t\treturn target_flush_reg(target, reg-\u003ename, false);"},{"line_number":3254,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"f8026d4a_9372df58","line":3251,"updated":"2024-01-31 10:50:20.000000000","message":"I don\u0027t quite understand the meaning of the comment. If a target has no cache, how did we obtain the `struct reg *reg` from it?","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":3248,"context_line":"\t\t\tfree(value);"},{"line_number":3249,"context_line":"\t\t}"},{"line_number":3250,"context_line":""},{"line_number":3251,"context_line":"\t\t// If target has no cache, dirty should never be set to true"},{"line_number":3252,"context_line":"\t\tif (reg-\u003edirty \u0026\u0026 flush)"},{"line_number":3253,"context_line":"\t\t\treturn target_flush_reg(target, reg-\u003ename, false);"},{"line_number":3254,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":7,"id":"87d36858_b2899867","line":3251,"in_reply_to":"f8026d4a_9372df58","updated":"2024-02-01 12:00:30.000000000","message":"Reworded it as \"If target decides not to cache this register, dirty should never be set to true\"","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":4918,"context_line":"\tconst char *third_argv \u003d NULL;"},{"line_number":4919,"context_line":""},{"line_number":4920,"context_line":"\tif (argc \u003d\u003d 3)"},{"line_number":4921,"context_line":"\t\tthird_argv \u003d Jim_GetString(argv[1], NULL);"},{"line_number":4922,"context_line":""},{"line_number":4923,"context_line":"\tif (third_argv \u0026\u0026 !strcmp(third_argv, \"-force\")) {"},{"line_number":4924,"context_line":"\t\tflush \u003d true;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"42714a44_17bd0b08","line":4921,"updated":"2024-01-31 10:50:20.000000000","message":"The name seems misleading. Isn\u0027t it the first argument?","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":4918,"context_line":"\tconst char *third_argv \u003d NULL;"},{"line_number":4919,"context_line":""},{"line_number":4920,"context_line":"\tif (argc \u003d\u003d 3)"},{"line_number":4921,"context_line":"\t\tthird_argv \u003d Jim_GetString(argv[1], NULL);"},{"line_number":4922,"context_line":""},{"line_number":4923,"context_line":"\tif (third_argv \u0026\u0026 !strcmp(third_argv, \"-force\")) {"},{"line_number":4924,"context_line":"\t\tflush \u003d true;"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"ab8271e7_4f3dbdbd","line":4921,"in_reply_to":"42714a44_17bd0b08","updated":"2024-02-01 12:00:30.000000000","message":"Renamed it to \"force_arg\"","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":4973,"context_line":"\t\t\t\treg_value, reg_name);"},{"line_number":4974,"context_line":"\t\t\treturn JIM_ERR;"},{"line_number":4975,"context_line":"\t\t}"},{"line_number":4976,"context_line":""},{"line_number":4977,"context_line":"\t\tif (flush \u0026\u0026 reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":4978,"context_line":"\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":4979,"context_line":"\t\t\t\tJim_SetResultFormatted(interp, \"Flushing for register \u0027%s\u0027 not implemented\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"bb3f0402_460f1b2e","line":4976,"updated":"2024-01-31 10:50:20.000000000","message":"Can\u0027t `target_flush_reg()` be reused here?","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":4973,"context_line":"\t\t\t\treg_value, reg_name);"},{"line_number":4974,"context_line":"\t\t\treturn JIM_ERR;"},{"line_number":4975,"context_line":"\t\t}"},{"line_number":4976,"context_line":""},{"line_number":4977,"context_line":"\t\tif (flush \u0026\u0026 reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":4978,"context_line":"\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":4979,"context_line":"\t\t\t\tJim_SetResultFormatted(interp, \"Flushing for register \u0027%s\u0027 not implemented\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"fd95ffeb_f8c92782","line":4976,"in_reply_to":"bb3f0402_460f1b2e","updated":"2024-02-01 12:00:30.000000000","message":"Done and used","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c2742df08441c52c8a7f023fc56b05511a46648f","unresolved":true,"context_lines":[{"line_number":6660,"context_line":"\t\tif (!strcmp(CMD_ARGV[0], \"-invalidate\")) {"},{"line_number":6661,"context_line":"\t\t\tinvalidate \u003d true;"},{"line_number":6662,"context_line":"\t\t} else {"},{"line_number":6663,"context_line":"\t\t\tLOG_TARGET_ERROR(target, \"Invalid flush_reg_cache option: %s\", CMD_ARGV[0]);"},{"line_number":6664,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":6665,"context_line":"\t\t}"},{"line_number":6666,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"08c76b73_15a290ab","line":6663,"updated":"2024-01-31 10:50:20.000000000","message":"Same as above, the usage is reported if `ERROR_COMMAND_SYNTAX_ERROR` is returned, so there is no need for the message.","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"626a559110a9e66a91a667cb6079889ec3f66084","unresolved":false,"context_lines":[{"line_number":6660,"context_line":"\t\tif (!strcmp(CMD_ARGV[0], \"-invalidate\")) {"},{"line_number":6661,"context_line":"\t\t\tinvalidate \u003d true;"},{"line_number":6662,"context_line":"\t\t} else {"},{"line_number":6663,"context_line":"\t\t\tLOG_TARGET_ERROR(target, \"Invalid flush_reg_cache option: %s\", CMD_ARGV[0]);"},{"line_number":6664,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"},{"line_number":6665,"context_line":"\t\t}"},{"line_number":6666,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"6baebde8_2d9996e7","line":6663,"in_reply_to":"08c76b73_15a290ab","updated":"2024-02-01 12:00:30.000000000","message":"Removed","commit_id":"023486dee50f794d9bdaabaa5793c679fdfaad5e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c8b51c6f07a2c1d7ca5327c0fad08a9d3e821a25","unresolved":true,"context_lines":[{"line_number":1561,"context_line":"\t}"},{"line_number":1562,"context_line":""},{"line_number":1563,"context_line":"\tif (!reg-\u003eexist) {"},{"line_number":1564,"context_line":"\t\tLOG_ERROR(\"BUG: register_flush() caled with non-existent register!\");"},{"line_number":1565,"context_line":"\t}"},{"line_number":1566,"context_line":""},{"line_number":1567,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"c598aba6_96a67a1d","line":1564,"updated":"2024-02-01 12:49:35.000000000","message":"`ERROR_FAIL` should be returned here.","commit_id":"173e342d8eef7cd7aa9688b022298bec1474dddc"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[{"line_number":1561,"context_line":"\t}"},{"line_number":1562,"context_line":""},{"line_number":1563,"context_line":"\tif (!reg-\u003eexist) {"},{"line_number":1564,"context_line":"\t\tLOG_ERROR(\"BUG: register_flush() caled with non-existent register!\");"},{"line_number":1565,"context_line":"\t}"},{"line_number":1566,"context_line":""},{"line_number":1567,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"124cd16b_4a6cf78b","line":1564,"in_reply_to":"c598aba6_96a67a1d","updated":"2024-02-01 13:11:40.000000000","message":"Done in new patchset","commit_id":"173e342d8eef7cd7aa9688b022298bec1474dddc"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c8b51c6f07a2c1d7ca5327c0fad08a9d3e821a25","unresolved":true,"context_lines":[{"line_number":1564,"context_line":"\t\tLOG_ERROR(\"BUG: register_flush() caled with non-existent register!\");"},{"line_number":1565,"context_line":"\t}"},{"line_number":1566,"context_line":""},{"line_number":1567,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1568,"context_line":"\t\tLOG_ERROR(\"Flushing of register \u0027%s\u0027 is not supported\", reg-\u003ename);"},{"line_number":1569,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1570,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"c177b4b1_4262e94a","line":1567,"updated":"2024-02-01 12:49:35.000000000","message":"This comment is to clarify [another comment](https://review.openocd.org/c/openocd/+/8070/comment/d67e3023_9f89f797/).\nI\u0027m referring to moving this check to after `if (!reg-\u003edirty)` on the line 1576.","commit_id":"173e342d8eef7cd7aa9688b022298bec1474dddc"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"c4f96b2f86c44dad705aff64304234742935428a","unresolved":false,"context_lines":[{"line_number":1564,"context_line":"\t\tLOG_ERROR(\"BUG: register_flush() caled with non-existent register!\");"},{"line_number":1565,"context_line":"\t}"},{"line_number":1566,"context_line":""},{"line_number":1567,"context_line":"\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1568,"context_line":"\t\tLOG_ERROR(\"Flushing of register \u0027%s\u0027 is not supported\", reg-\u003ename);"},{"line_number":1569,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1570,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"9046c8ea_057e8ab1","line":1567,"in_reply_to":"c177b4b1_4262e94a","updated":"2024-02-01 13:11:40.000000000","message":"Ack","commit_id":"173e342d8eef7cd7aa9688b022298bec1474dddc"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"3d7916c37b39acc00209d44b7e4815b9e2ee2c06","unresolved":true,"context_lines":[{"line_number":1503,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1504,"context_line":"\t}"},{"line_number":1505,"context_line":"\tif (!target_implements_reg_flush(cache) \u0026\u0026 any_regs_dirty) {"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush dirty registers.\");"},{"line_number":1507,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1508,"context_line":"\t}"},{"line_number":1509,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":10,"id":"6dd21195_3740fcf3","line":1506,"updated":"2024-02-02 07:25:16.000000000","message":"If you\u0027d like:\n\n`Unable to flush dirty registers - operation not supported by the target.`","commit_id":"b78571f1ac0e65a5c11da99b9bab48becbbb4b4d"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"d292cfc246451dcc470db7847204b629c736a848","unresolved":false,"context_lines":[{"line_number":1503,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1504,"context_line":"\t}"},{"line_number":1505,"context_line":"\tif (!target_implements_reg_flush(cache) \u0026\u0026 any_regs_dirty) {"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush dirty registers.\");"},{"line_number":1507,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1508,"context_line":"\t}"},{"line_number":1509,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":10,"id":"ac954e9b_623f4d6a","line":1506,"in_reply_to":"12cf305b_327c14bc","updated":"2024-02-05 07:39:53.000000000","message":"Done","commit_id":"b78571f1ac0e65a5c11da99b9bab48becbbb4b4d"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"911a47a084ad871d3cf1c074affd9738eb0692c0","unresolved":true,"context_lines":[{"line_number":1503,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1504,"context_line":"\t}"},{"line_number":1505,"context_line":"\tif (!target_implements_reg_flush(cache) \u0026\u0026 any_regs_dirty) {"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush dirty registers.\");"},{"line_number":1507,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1508,"context_line":"\t}"},{"line_number":1509,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":10,"id":"12cf305b_327c14bc","line":1506,"in_reply_to":"6dd21195_3740fcf3","updated":"2024-02-02 07:26:34.000000000","message":"I\u0027d also recommend to swap the order of the checks: \n\n- First, check if the target can do the flush at all.\n- Second, check if there is anything to flush.","commit_id":"b78571f1ac0e65a5c11da99b9bab48becbbb4b4d"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"a67d9712d37f742747b7d99bae864966b73dc7cb","unresolved":true,"context_lines":[{"line_number":6697,"context_line":"\t\t.handler \u003d handle_reg_command,"},{"line_number":6698,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":6699,"context_line":"\t\t.help \u003d \"display (reread from target with \\\"force\\\") or set a register \""},{"line_number":6700,"context_line":"\t\t    \"(force bypass register cache with \\\"force\\\"); \""},{"line_number":6701,"context_line":"\t\t\t\"with no arguments, displays all registers and their values\","},{"line_number":6702,"context_line":"\t\t.usage \u003d \"[(register_number|register_name) [(value [\u0027force\u0027]|\u0027force\u0027)]\","},{"line_number":6703,"context_line":"\t},"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"72ee82ea_a4ee5ce7","line":6700,"updated":"2024-02-05 08:29:04.000000000","message":"I\u0027d recommend to slightly update the help:\n\n```\n.help \u003d \"display (reread from target with \\\"force\\\") or set a register \"\n        \"(write to the target immediately with \\\"force\\\"); \"\n```","commit_id":"0513acc7e647797e1267f123162a80996dc1259c"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"708ef3565740d89ba7dd2d95a87214d7158814c8","unresolved":false,"context_lines":[{"line_number":6697,"context_line":"\t\t.handler \u003d handle_reg_command,"},{"line_number":6698,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":6699,"context_line":"\t\t.help \u003d \"display (reread from target with \\\"force\\\") or set a register \""},{"line_number":6700,"context_line":"\t\t    \"(force bypass register cache with \\\"force\\\"); \""},{"line_number":6701,"context_line":"\t\t\t\"with no arguments, displays all registers and their values\","},{"line_number":6702,"context_line":"\t\t.usage \u003d \"[(register_number|register_name) [(value [\u0027force\u0027]|\u0027force\u0027)]\","},{"line_number":6703,"context_line":"\t},"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"f40e563b_306d4288","line":6700,"in_reply_to":"72ee82ea_a4ee5ce7","updated":"2024-02-05 11:41:42.000000000","message":"Done","commit_id":"0513acc7e647797e1267f123162a80996dc1259c"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"a67d9712d37f742747b7d99bae864966b73dc7cb","unresolved":true,"context_lines":[{"line_number":6699,"context_line":"\t\t.help \u003d \"display (reread from target with \\\"force\\\") or set a register \""},{"line_number":6700,"context_line":"\t\t    \"(force bypass register cache with \\\"force\\\"); \""},{"line_number":6701,"context_line":"\t\t\t\"with no arguments, displays all registers and their values\","},{"line_number":6702,"context_line":"\t\t.usage \u003d \"[(register_number|register_name) [(value [\u0027force\u0027]|\u0027force\u0027)]\","},{"line_number":6703,"context_line":"\t},"},{"line_number":6704,"context_line":"\t{"},{"line_number":6705,"context_line":"\t\t.name \u003d \"poll\","}],"source_content_type":"text/x-csrc","patch_set":11,"id":"3f5ae9cf_b4b8a707","line":6702,"updated":"2024-02-05 08:29:04.000000000","message":"I\u0027d recommend to simplify the usage:\n\n```\n.usage \u003d \"[(register_number|register_name) [value] [\u0027force\u0027]]\"\n```","commit_id":"0513acc7e647797e1267f123162a80996dc1259c"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"708ef3565740d89ba7dd2d95a87214d7158814c8","unresolved":false,"context_lines":[{"line_number":6699,"context_line":"\t\t.help \u003d \"display (reread from target with \\\"force\\\") or set a register \""},{"line_number":6700,"context_line":"\t\t    \"(force bypass register cache with \\\"force\\\"); \""},{"line_number":6701,"context_line":"\t\t\t\"with no arguments, displays all registers and their values\","},{"line_number":6702,"context_line":"\t\t.usage \u003d \"[(register_number|register_name) [(value [\u0027force\u0027]|\u0027force\u0027)]\","},{"line_number":6703,"context_line":"\t},"},{"line_number":6704,"context_line":"\t{"},{"line_number":6705,"context_line":"\t\t.name \u003d \"poll\","}],"source_content_type":"text/x-csrc","patch_set":11,"id":"249ef7a7_a539785c","line":6702,"in_reply_to":"3f5ae9cf_b4b8a707","updated":"2024-02-05 11:41:42.000000000","message":"Done","commit_id":"0513acc7e647797e1267f123162a80996dc1259c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":1469,"context_line":"\twhile (cache) {"},{"line_number":1470,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1471,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1472,"context_line":"\t\t\tif (reg-\u003etype-\u003eflush)"},{"line_number":1473,"context_line":"\t\t\t\treturn true;"},{"line_number":1474,"context_line":"\t\t}"},{"line_number":1475,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"b9334e77_1012407a","line":1472,"updated":"2024-02-18 10:41:02.000000000","message":"skip registers with reg-\u003eexist\u003dfalse ?","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":1469,"context_line":"\twhile (cache) {"},{"line_number":1470,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1471,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1472,"context_line":"\t\t\tif (reg-\u003etype-\u003eflush)"},{"line_number":1473,"context_line":"\t\t\t\treturn true;"},{"line_number":1474,"context_line":"\t\t}"},{"line_number":1475,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"d52dc823_e30f5bb7","line":1472,"in_reply_to":"b9334e77_1012407a","updated":"2024-02-20 14:47:15.000000000","message":"This checks if any register implements flushing, if yes, we expect the target takes into account registers which do not have flushing implemented.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":1477,"context_line":"\treturn false;"},{"line_number":1478,"context_line":"}"},{"line_number":1479,"context_line":""},{"line_number":1480,"context_line":"static bool target_any_register_dirty(const struct reg_cache *cache)"},{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\twhile (cache) {"},{"line_number":1483,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"aaf9c705_bca13ae4","line":1480,"updated":"2024-02-18 10:41:02.000000000","message":"rename as ```target_has_any_register_dirty()``` ?","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":1477,"context_line":"\treturn false;"},{"line_number":1478,"context_line":"}"},{"line_number":1479,"context_line":""},{"line_number":1480,"context_line":"static bool target_any_register_dirty(const struct reg_cache *cache)"},{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\twhile (cache) {"},{"line_number":1483,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"b3654925_d7452820","line":1480,"in_reply_to":"aaf9c705_bca13ae4","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":1482,"context_line":"\twhile (cache) {"},{"line_number":1483,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1484,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1485,"context_line":"\t\t\tif (reg-\u003edirty)"},{"line_number":1486,"context_line":"\t\t\t\treturn true;"},{"line_number":1487,"context_line":"\t\t}"},{"line_number":1488,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"5e8df882_2cab4c45","line":1485,"updated":"2024-02-18 10:41:02.000000000","message":"maybe not really needed, but the test should be only on registers with reg-\u003eexist\u003dtrue","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":1482,"context_line":"\twhile (cache) {"},{"line_number":1483,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1484,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1485,"context_line":"\t\t\tif (reg-\u003edirty)"},{"line_number":1486,"context_line":"\t\t\t\treturn true;"},{"line_number":1487,"context_line":"\t\t}"},{"line_number":1488,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"59283f77_7264ade4","line":1485,"in_reply_to":"5e8df882_2cab4c45","updated":"2024-02-20 14:47:15.000000000","message":"I agree, changed.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c1128a02baabdad642912f2e6babed628414ec84","unresolved":true,"context_lines":[{"line_number":1516,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1517,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":1518,"context_line":"\t\t\t\tdirty_count++;"},{"line_number":1519,"context_line":"\t\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1520,"context_line":"\t\t\t\t\tLOG_TARGET_WARNING(target, \"Flushing register \u0027%s\u0027 is not implemented\", reg-\u003ename);"},{"line_number":1521,"context_line":"\t\t\t\t\tfailed_count++;"},{"line_number":1522,"context_line":"\t\t\t\t\tcontinue;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"39670094_58c06512","line":1519,"updated":"2024-02-12 13:48:25.000000000","message":"Can\u0027t `register_flush()` be reused here? The only issue I see is `failed_count` being not incremented in case the register remained dirty after a flush, but this is already considered a bug, so I don\u0027t see a problem here.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":1516,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1517,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":1518,"context_line":"\t\t\t\tdirty_count++;"},{"line_number":1519,"context_line":"\t\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1520,"context_line":"\t\t\t\t\tLOG_TARGET_WARNING(target, \"Flushing register \u0027%s\u0027 is not implemented\", reg-\u003ename);"},{"line_number":1521,"context_line":"\t\t\t\t\tfailed_count++;"},{"line_number":1522,"context_line":"\t\t\t\t\tcontinue;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"093e8902_21f70943","line":1519,"in_reply_to":"39670094_58c06512","updated":"2024-02-20 14:47:15.000000000","message":"I would prefer to keep it this way, it will be easier for us to spot bugs this way and we would lose the failed_count.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c1128a02baabdad642912f2e6babed628414ec84","unresolved":true,"context_lines":[{"line_number":1535,"context_line":"\t\t\t\tif (reg-\u003evalid \u0026\u0026 invalidate) {"},{"line_number":1536,"context_line":"\t\t\t\t\tLOG_TARGET_DEBUG(target, \"Invalidating register \u0027%s\u0027 after flush\", reg-\u003ename);"},{"line_number":1537,"context_line":"\t\t\t\t\treg-\u003evalid \u003d false;"},{"line_number":1538,"context_line":"\t\t\t\t}"},{"line_number":1539,"context_line":"\t\t\t}"},{"line_number":1540,"context_line":"\t\t}"},{"line_number":1541,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"8641a0ce_66a2f136","line":1538,"updated":"2024-02-12 13:48:25.000000000","message":"A clean register is not invalidated even if `invalidate` is passed. Is this intentional? If not, this may be fixed by reusing `register_flush()`.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":1535,"context_line":"\t\t\t\tif (reg-\u003evalid \u0026\u0026 invalidate) {"},{"line_number":1536,"context_line":"\t\t\t\t\tLOG_TARGET_DEBUG(target, \"Invalidating register \u0027%s\u0027 after flush\", reg-\u003ename);"},{"line_number":1537,"context_line":"\t\t\t\t\treg-\u003evalid \u003d false;"},{"line_number":1538,"context_line":"\t\t\t\t}"},{"line_number":1539,"context_line":"\t\t\t}"},{"line_number":1540,"context_line":"\t\t}"},{"line_number":1541,"context_line":"\t\tcache \u003d cache-\u003enext;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"334cb2e5_628c588d","line":1538,"in_reply_to":"8641a0ce_66a2f136","updated":"2024-02-20 14:47:15.000000000","message":"Changed it to invalidate. It does make sense to invalidate in this case, even if the register is not dirty.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c1128a02baabdad642912f2e6babed628414ec84","unresolved":true,"context_lines":[{"line_number":3201,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3202,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3203,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0) \u0026\u0026 reg-\u003evalid) {"},{"line_number":3204,"context_line":"\t\t\tint retval \u003d register_flush(reg, true);"},{"line_number":3205,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3206,"context_line":"\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"},{"line_number":3207,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"9299dce1_e6d8306a","line":3204,"updated":"2024-02-12 13:48:25.000000000","message":"With the current order of checks in `register_flush()`, this will not work. Reading a clean register with `force` flag set on a target not implementing `reg-\u003earch_type-\u003eflush` will result in an error. For this to work, early exit for non-dirty registers in `register_flush()` should be before the check whether the `reg-\u003earch_type-\u003eflush` is not `NULL`.\nMoreover, I would suggest checking whether `target_implements_reg_flush()` is true here, since otherwise the change will break scripts of users. (Maybe also a `TODO` that the check can be removed once all the target implement the flush.)","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":3201,"context_line":"\tif ((CMD_ARGC \u003d\u003d 1) || ((CMD_ARGC \u003d\u003d 2) \u0026\u0026 !((CMD_ARGV[1][0] \u003e\u003d \u00270\u0027)"},{"line_number":3202,"context_line":"\t\t\t\u0026\u0026 (CMD_ARGV[1][0] \u003c\u003d \u00279\u0027)))) {"},{"line_number":3203,"context_line":"\t\tif (CMD_ARGC \u003d\u003d 2 \u0026\u0026 (strcmp(CMD_ARGV[1], \"force\") \u003d\u003d 0) \u0026\u0026 reg-\u003evalid) {"},{"line_number":3204,"context_line":"\t\t\tint retval \u003d register_flush(reg, true);"},{"line_number":3205,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":3206,"context_line":"\t\t\t\tLOG_TARGET_ERROR(target, \"Failed to flush register \u0027%s\u0027 before force-reading\", reg-\u003ename);"},{"line_number":3207,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"5e39c4b2_426dd48f","line":3204,"in_reply_to":"9299dce1_e6d8306a","updated":"2024-02-20 14:47:15.000000000","message":"Are you sure about that? The order of checks in register_flush() is:\n\n- !reg (ERROR)\n- !reg-\u003eexists (ERROR)\n- !reg-\u003edirty (OK)\n...\n\nThere is an early exit for the case when the register isn\u0027t dirty.\n\nAdded the extra check that the target implements flushing.","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c1128a02baabdad642912f2e6babed628414ec84","unresolved":true,"context_lines":[{"line_number":4973,"context_line":"\t\t}"},{"line_number":4974,"context_line":""},{"line_number":4975,"context_line":"\t\tif (flush \u0026\u0026 reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":4976,"context_line":"\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":4977,"context_line":"\t\t\t\tJim_SetResultFormatted(interp, \"Flushing for register \u0027%s\u0027 not implemented\", reg-\u003ename);"},{"line_number":4978,"context_line":"\t\t\t\treturn JIM_ERR;"},{"line_number":4979,"context_line":"\t\t\t}"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"9599d406_aaa69da0","line":4976,"updated":"2024-02-12 13:48:25.000000000","message":"I think this is already reported in `register_flush()`","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":4973,"context_line":"\t\t}"},{"line_number":4974,"context_line":""},{"line_number":4975,"context_line":"\t\tif (flush \u0026\u0026 reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":4976,"context_line":"\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":4977,"context_line":"\t\t\t\tJim_SetResultFormatted(interp, \"Flushing for register \u0027%s\u0027 not implemented\", reg-\u003ename);"},{"line_number":4978,"context_line":"\t\t\t\treturn JIM_ERR;"},{"line_number":4979,"context_line":"\t\t\t}"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"6ef18049_3fdfe757","line":4976,"in_reply_to":"9599d406_aaa69da0","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":6650,"context_line":"\tbool invalidate \u003d false;"},{"line_number":6651,"context_line":""},{"line_number":6652,"context_line":"\tif (CMD_ARGC \u003d\u003d 1) {"},{"line_number":6653,"context_line":"\t\tif (!strcmp(CMD_ARGV[0], \"-invalidate\"))"},{"line_number":6654,"context_line":"\t\t\tinvalidate \u003d true;"},{"line_number":6655,"context_line":"\t\telse"},{"line_number":6656,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"169a43ee_f20169b0","line":6653,"updated":"2024-02-18 10:41:02.000000000","message":"invert the test, so we can avoid the \"else\" block:\n```\nif (strcmp(CMD_ARGV[0], \"-invalidate\"))\n  return ERROR_COMMAND_SYNTAX_ERROR;\ninvalidate \u003d true;\n```","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":6650,"context_line":"\tbool invalidate \u003d false;"},{"line_number":6651,"context_line":""},{"line_number":6652,"context_line":"\tif (CMD_ARGC \u003d\u003d 1) {"},{"line_number":6653,"context_line":"\t\tif (!strcmp(CMD_ARGV[0], \"-invalidate\"))"},{"line_number":6654,"context_line":"\t\t\tinvalidate \u003d true;"},{"line_number":6655,"context_line":"\t\telse"},{"line_number":6656,"context_line":"\t\t\treturn ERROR_COMMAND_SYNTAX_ERROR;"}],"source_content_type":"text/x-csrc","patch_set":12,"id":"a9d16c0b_9f797015","line":6653,"in_reply_to":"169a43ee_f20169b0","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f28326f467ec4d5df156b82bc4cf7323721f17b5","unresolved":true,"context_lines":[{"line_number":6918,"context_line":"\t\t.usage \u003d \"size\","},{"line_number":6919,"context_line":"\t},"},{"line_number":6920,"context_line":"\t{"},{"line_number":6921,"context_line":"\t\t.name \u003d \"flush_reg_cache\","},{"line_number":6922,"context_line":"\t\t.handler \u003d handle_flush_reg_cache_command,"},{"line_number":6923,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":6924,"context_line":"\t\t.help \u003d \"Flush register cache\","}],"source_content_type":"text/x-csrc","patch_set":12,"id":"fe87c8c5_d5b9d52d","line":6921,"updated":"2024-02-18 10:41:02.000000000","message":"could be moved above and placed together with the commands \"get_reg\" and \"set_reg\"","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"e88016f20c4c100573652cf710b3448c6d5605e1","unresolved":false,"context_lines":[{"line_number":6918,"context_line":"\t\t.usage \u003d \"size\","},{"line_number":6919,"context_line":"\t},"},{"line_number":6920,"context_line":"\t{"},{"line_number":6921,"context_line":"\t\t.name \u003d \"flush_reg_cache\","},{"line_number":6922,"context_line":"\t\t.handler \u003d handle_flush_reg_cache_command,"},{"line_number":6923,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":6924,"context_line":"\t\t.help \u003d \"Flush register cache\","}],"source_content_type":"text/x-csrc","patch_set":12,"id":"d1bfa819_56f1f53d","line":6921,"in_reply_to":"fe87c8c5_d5b9d52d","updated":"2024-02-20 14:47:15.000000000","message":"Done","commit_id":"e3a0817eddd55b79cee7a0fd11f2526aa9a387b9"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"a2d5a3db64de506db8176e090d14d9149d8c9ea4","unresolved":true,"context_lines":[{"line_number":1502,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1503,"context_line":"\t}"},{"line_number":1504,"context_line":""},{"line_number":1505,"context_line":"\tif (!target_has_any_register_dirty(cache)) {"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_INFO(target, \"No registers dirty, nothing to flush.\");"},{"line_number":1507,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1508,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"a471ca49_0204ab4a","line":1505,"updated":"2024-02-21 09:32:23.000000000","message":"If `invalidate` is passed, register cache is not invalidated in this case.\nI would suggest to remove this call and append the following to the end of the function:\n```\nif (!dirty_count)\n   LOG_TARGET_INFO(target, \"No registers dirty, nothing to flush.\");\n```\n`target_has_any_register_dirty()` can be removed after this.","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"6e2954f95993c6a3320467a0410a63e6251ba670","unresolved":false,"context_lines":[{"line_number":1502,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1503,"context_line":"\t}"},{"line_number":1504,"context_line":""},{"line_number":1505,"context_line":"\tif (!target_has_any_register_dirty(cache)) {"},{"line_number":1506,"context_line":"\t\tLOG_TARGET_INFO(target, \"No registers dirty, nothing to flush.\");"},{"line_number":1507,"context_line":"\t\treturn ERROR_OK;"},{"line_number":1508,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"622ee92c_26f7d040","line":1505,"in_reply_to":"a471ca49_0204ab4a","updated":"2024-02-22 12:17:16.000000000","message":"Thanks for the idea, did so.","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"a2d5a3db64de506db8176e090d14d9149d8c9ea4","unresolved":true,"context_lines":[{"line_number":1514,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1515,"context_line":"\t\t\ttotal_count++;"},{"line_number":1516,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1517,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":1518,"context_line":"\t\t\t\tdirty_count++;"},{"line_number":1519,"context_line":"\t\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1520,"context_line":"\t\t\t\t\tLOG_TARGET_WARNING(target, \"Flushing register \u0027%s\u0027 is not implemented\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"b17a7a16_b0f90af5","line":1517,"updated":"2024-02-21 09:32:23.000000000","message":"`reg-\u003eexist` should be checked here before `reg-\u003e[valid|dirty]`.\nI would suggest to add an early continue:\n```\nif (!(reg-\u003eexist \u0026\u0026 reg-\u003evalid))\n    continue;\n```","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"6e2954f95993c6a3320467a0410a63e6251ba670","unresolved":false,"context_lines":[{"line_number":1514,"context_line":"\t\tfor (unsigned int i \u003d 0; i \u003c cache-\u003enum_regs; i++) {"},{"line_number":1515,"context_line":"\t\t\ttotal_count++;"},{"line_number":1516,"context_line":"\t\t\tstruct reg *reg \u003d \u0026cache-\u003ereg_list[i];"},{"line_number":1517,"context_line":"\t\t\tif (reg-\u003evalid \u0026\u0026 reg-\u003edirty) {"},{"line_number":1518,"context_line":"\t\t\t\tdirty_count++;"},{"line_number":1519,"context_line":"\t\t\t\tif (!reg-\u003etype-\u003eflush) {"},{"line_number":1520,"context_line":"\t\t\t\t\tLOG_TARGET_WARNING(target, \"Flushing register \u0027%s\u0027 is not implemented\", reg-\u003ename);"}],"source_content_type":"text/x-csrc","patch_set":13,"id":"7f53db3d_b535adf4","line":1517,"in_reply_to":"b17a7a16_b0f90af5","updated":"2024-02-22 12:17:16.000000000","message":"Done, I did use if (!reg-\u003eexists || !reg-\u003evalid) instead, feels more readable to me.","commit_id":"05a500343029c8dcc6b7d58ffcc787cadfb634cd"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"28c4cc75113919d139b6fb2929d301309e065de8","unresolved":true,"context_lines":[{"line_number":1489,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1490,"context_line":"\t}"},{"line_number":1491,"context_line":""},{"line_number":1492,"context_line":""},{"line_number":1493,"context_line":""},{"line_number":1494,"context_line":"\tunsigned int total_count \u003d 0;"},{"line_number":1495,"context_line":"\tunsigned int dirty_count \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":14,"id":"5ec0e732_2b1cf0de","line":1492,"updated":"2024-02-22 14:07:56.000000000","message":"Seems like there are a few extra empty lines here","commit_id":"651beb0e40c0f041778537e515a1ca90d9394311"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"0fecc83b47c8ee1319e1dcd5d6459a0d6f71c89e","unresolved":false,"context_lines":[{"line_number":1489,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1490,"context_line":"\t}"},{"line_number":1491,"context_line":""},{"line_number":1492,"context_line":""},{"line_number":1493,"context_line":""},{"line_number":1494,"context_line":"\tunsigned int total_count \u003d 0;"},{"line_number":1495,"context_line":"\tunsigned int dirty_count \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":14,"id":"05278cec_f832dd6f","line":1492,"in_reply_to":"5ec0e732_2b1cf0de","updated":"2024-02-23 06:43:19.000000000","message":"Done","commit_id":"651beb0e40c0f041778537e515a1ca90d9394311"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"28c4cc75113919d139b6fb2929d301309e065de8","unresolved":true,"context_lines":[{"line_number":3243,"context_line":"\t\t\tfree(value);"},{"line_number":3244,"context_line":"\t\t}"},{"line_number":3245,"context_line":""},{"line_number":3246,"context_line":"\t\t// If target decides not to cache this register, dirty should never be set to true"},{"line_number":3247,"context_line":"\t\tif (reg-\u003edirty \u0026\u0026 flush)"},{"line_number":3248,"context_line":"\t\t\treturn register_flush(reg, false);"},{"line_number":3249,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"f40d5f9b_2800a33f","line":3246,"updated":"2024-02-22 14:07:56.000000000","message":"I don\u0027t understand the comment. Why is the flush needed here?","commit_id":"651beb0e40c0f041778537e515a1ca90d9394311"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"0fecc83b47c8ee1319e1dcd5d6459a0d6f71c89e","unresolved":false,"context_lines":[{"line_number":3243,"context_line":"\t\t\tfree(value);"},{"line_number":3244,"context_line":"\t\t}"},{"line_number":3245,"context_line":""},{"line_number":3246,"context_line":"\t\t// If target decides not to cache this register, dirty should never be set to true"},{"line_number":3247,"context_line":"\t\tif (reg-\u003edirty \u0026\u0026 flush)"},{"line_number":3248,"context_line":"\t\t\treturn register_flush(reg, false);"},{"line_number":3249,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":14,"id":"58b71e45_c4856568","line":3246,"in_reply_to":"f40d5f9b_2800a33f","updated":"2024-02-23 06:43:19.000000000","message":"The flush here is done if the user specified the \"force\" argument, hence force writing the register.\n\nDeleted the comment, I agree it probably isn\u0027t needed.","commit_id":"651beb0e40c0f041778537e515a1ca90d9394311"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"7bd2bd3559cc9685dc49156f54f4056c224bf1d3","unresolved":true,"context_lines":[{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet"},{"line_number":1485,"context_line":"\t// this function will result in many warnings, these two if branches"},{"line_number":1486,"context_line":"\t// are here to prevent them"},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not supported by the target.\");"}],"source_content_type":"text/x-csrc","patch_set":17,"id":"d2175f4d_26990588","line":1485,"updated":"2025-01-20 13:11:26.000000000","message":"I believe the comment is outdated (at least the part about `two if branches`) and can be removed.","commit_id":"16055c82058f59481dcc02c0cf2299fea26e933e"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"b92095f0ec6123bae4556ca29f3a8ff55fd7f006","unresolved":true,"context_lines":[{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet"},{"line_number":1485,"context_line":"\t// this function will result in many warnings, these two if branches"},{"line_number":1486,"context_line":"\t// are here to prevent them"},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not supported by the target.\");"}],"source_content_type":"text/x-csrc","patch_set":17,"id":"e7822b42_3bf97a93","line":1485,"in_reply_to":"d2175f4d_26990588","updated":"2025-01-20 13:29:29.000000000","message":"Addressed, thanks for the catch.","commit_id":"16055c82058f59481dcc02c0cf2299fea26e933e"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"577e7f95e22858f25a8bebcc9920828015cb05f2","unresolved":false,"context_lines":[{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet"},{"line_number":1485,"context_line":"\t// this function will result in many warnings, these two if branches"},{"line_number":1486,"context_line":"\t// are here to prevent them"},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not supported by the target.\");"}],"source_content_type":"text/x-csrc","patch_set":17,"id":"2f8298c6_2d2659b6","line":1485,"in_reply_to":"e7822b42_3bf97a93","updated":"2025-01-20 16:18:16.000000000","message":"Done","commit_id":"16055c82058f59481dcc02c0cf2299fea26e933e"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"28924cfb238f816b0ca358a55ab507907d9e6686","unresolved":true,"context_lines":[{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet, this function"},{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"eb1ac123_32d415bf","line":1484,"updated":"2025-01-20 21:15:03.000000000","message":"Wrong comment style.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"da8c607938a2aec6815f38be9a0f8b18ac50b422","unresolved":false,"context_lines":[{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet, this function"},{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"6a170f00_8fe382cf","line":1484,"in_reply_to":"8f860044_d7b8dd20","updated":"2025-02-14 11:23:24.000000000","message":"Ack","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5bebb10437ffd39cc30964574af78b34dbb08b96","unresolved":true,"context_lines":[{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet, this function"},{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"fd610ccd_6369598a","line":1484,"in_reply_to":"eb1ac123_32d415bf","updated":"2025-01-21 14:29:08.000000000","message":"Addressed - I have replaced it by a block comment.\n\nSide question: Is this the current coding style for comments?\n- Block comments for multi-line text \n- Either comment style (line or block) for single-line text\n\nIf so, then the [C style guide](https://openocd.org/doc/doxygen/html/stylec.html) should be updated to state that.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"83d7542085cb8520b2005c16fe97c5cc39fc2b11","unresolved":true,"context_lines":[{"line_number":1481,"context_line":"{"},{"line_number":1482,"context_line":"\tstruct reg_cache *cache \u003d target-\u003ereg_cache;"},{"line_number":1483,"context_line":""},{"line_number":1484,"context_line":"\t// In targets where per-register flushing isn\u0027t implemented yet, this function"},{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"8f860044_d7b8dd20","line":1484,"in_reply_to":"fd610ccd_6369598a","updated":"2025-02-05 20:44:09.000000000","message":"Yes, that\u0027s the current coding style. The part about block comments is missing it seems.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"28924cfb238f816b0ca358a55ab507907d9e6686","unresolved":true,"context_lines":[{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not yet supported \""},{"line_number":1489,"context_line":"\t\t\t\"by %s implementation in OpenOCD.\", target-\u003etype-\u003ename);"},{"line_number":1490,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1491,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"90f8d361_1d29614d","line":1488,"updated":"2025-01-20 21:15:03.000000000","message":"Do not use a point at the end of the log message, see coding style.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"da8c607938a2aec6815f38be9a0f8b18ac50b422","unresolved":false,"context_lines":[{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not yet supported \""},{"line_number":1489,"context_line":"\t\t\t\"by %s implementation in OpenOCD.\", target-\u003etype-\u003ename);"},{"line_number":1490,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1491,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"94b0ee1a_da4a9232","line":1488,"in_reply_to":"7e973ca7_5bf1dd93","updated":"2025-02-14 11:23:24.000000000","message":"Done","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5bebb10437ffd39cc30964574af78b34dbb08b96","unresolved":true,"context_lines":[{"line_number":1485,"context_line":"\t// would result in many errors (one for each dirty register). The check below is"},{"line_number":1486,"context_line":"\t// to prevent that and print just a single clear error message."},{"line_number":1487,"context_line":"\tif (!target_implements_reg_flush(cache)) {"},{"line_number":1488,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Unable to flush register cache - operation not yet supported \""},{"line_number":1489,"context_line":"\t\t\t\"by %s implementation in OpenOCD.\", target-\u003etype-\u003ename);"},{"line_number":1490,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":1491,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"7e973ca7_5bf1dd93","line":1488,"in_reply_to":"90f8d361_1d29614d","updated":"2025-01-21 14:29:08.000000000","message":"Addressed - I have removed trailing periods or exclamation marks from all log messages, except for those that consist of multiple sentences.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"28924cfb238f816b0ca358a55ab507907d9e6686","unresolved":true,"context_lines":[{"line_number":4914,"context_line":""},{"line_number":4915,"context_line":"\t/* Check for the \"-force\" argument */"},{"line_number":4916,"context_line":"\tif (CMD_ARGC \u003d\u003d 2) {"},{"line_number":4917,"context_line":"\t\tif (strcmp(CMD_ARGV[0], \"-force\")) {"},{"line_number":4918,"context_line":"\t\t\tflush \u003d true;"},{"line_number":4919,"context_line":"\t\t} else {"},{"line_number":4920,"context_line":"\t\t\tcommand_print(CMD, \"unknown argument \u0027%s\u0027\", CMD_ARGV[0]);"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"65bdfc65_412bf3ed","line":4917,"updated":"2025-01-20 21:15:03.000000000","message":"Should be `!strcmp(..)`, no?","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"da8c607938a2aec6815f38be9a0f8b18ac50b422","unresolved":false,"context_lines":[{"line_number":4914,"context_line":""},{"line_number":4915,"context_line":"\t/* Check for the \"-force\" argument */"},{"line_number":4916,"context_line":"\tif (CMD_ARGC \u003d\u003d 2) {"},{"line_number":4917,"context_line":"\t\tif (strcmp(CMD_ARGV[0], \"-force\")) {"},{"line_number":4918,"context_line":"\t\t\tflush \u003d true;"},{"line_number":4919,"context_line":"\t\t} else {"},{"line_number":4920,"context_line":"\t\t\tcommand_print(CMD, \"unknown argument \u0027%s\u0027\", CMD_ARGV[0]);"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"f90db691_c67a21a1","line":4917,"in_reply_to":"19b7a763_adba7e90","updated":"2025-02-14 11:23:24.000000000","message":"Done","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"5bebb10437ffd39cc30964574af78b34dbb08b96","unresolved":true,"context_lines":[{"line_number":4914,"context_line":""},{"line_number":4915,"context_line":"\t/* Check for the \"-force\" argument */"},{"line_number":4916,"context_line":"\tif (CMD_ARGC \u003d\u003d 2) {"},{"line_number":4917,"context_line":"\t\tif (strcmp(CMD_ARGV[0], \"-force\")) {"},{"line_number":4918,"context_line":"\t\t\tflush \u003d true;"},{"line_number":4919,"context_line":"\t\t} else {"},{"line_number":4920,"context_line":"\t\t\tcommand_print(CMD, \"unknown argument \u0027%s\u0027\", CMD_ARGV[0]);"}],"source_content_type":"text/x-csrc","patch_set":18,"id":"19b7a763_adba7e90","line":4917,"in_reply_to":"65bdfc65_412bf3ed","updated":"2025-01-21 14:29:08.000000000","message":"Addressed - thank you for the catch.","commit_id":"be7ab0b63088238af18b188e907299f5eb2e090b"}]}