)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"e6893e413117d6b0a2919dddec140f6d8b8208be","unresolved":true,"context_lines":[{"line_number":13,"context_line":"This flag has no effects on Cortex-M; ARM specifies that only one"},{"line_number":14,"context_line":"CPU Cortex-M can occupy the AP, using hardcoded addresses."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"The flash driver \u0027psoc6\u0027 abuses the flag \u0027-coreid\u0027 to detect if"},{"line_number":17,"context_line":"the current target is the Cortex-M0 or the Cortex-M4."},{"line_number":18,"context_line":"There are other ways to run such detection, without abusing an"},{"line_number":19,"context_line":"unrelated flag. E.g. the AP number or the arch type."},{"line_number":20,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"1cc0104e_d3dcb7ee","line":17,"range":{"start_line":16,"start_character":25,"end_line":17,"end_character":53},"updated":"2024-02-03 16:33:07.000000000","message":"Strongly disagree.\n1) The flash driver primarily needs to know which core is running on - not the type of architecture or CPU. In PSoC6 documentation the cores are referenced as CM0 and CM4. The name of is_cm4 variable is derived from this.\n2) -coreid option name suggests that it was introduced to serve as a general core identification/numbering in a multicore SoC (regardless the SoC is SMP or asymmetric). If the option were named -coresight-rom-table-cpu-index, then yes, this use could be called as an abuse. However with the current name I assume that any use of this option which is not in any contradiction with other existing uses is **correct**\n3) The option should be documented first and all limiting rules listed","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"e8e3a8ed64f5bf06c2935796c303101d71a3d01c","unresolved":true,"context_lines":[{"line_number":13,"context_line":"This flag has no effects on Cortex-M; ARM specifies that only one"},{"line_number":14,"context_line":"CPU Cortex-M can occupy the AP, using hardcoded addresses."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"The flash driver \u0027psoc6\u0027 abuses the flag \u0027-coreid\u0027 to detect if"},{"line_number":17,"context_line":"the current target is the Cortex-M0 or the Cortex-M4."},{"line_number":18,"context_line":"There are other ways to run such detection, without abusing an"},{"line_number":19,"context_line":"unrelated flag. E.g. the AP number or the arch type."},{"line_number":20,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"137fabbc_99b27e49","line":17,"range":{"start_line":16,"start_character":25,"end_line":17,"end_character":53},"in_reply_to":"0bbfe0c8_dce1b672","updated":"2024-02-03 19:49:46.000000000","message":"\u003e \u003e 1) The flash driver primarily needs to know which core is running on - not the type of architecture or CPU. In PSoC6 documentation the cores are referenced as CM0 and CM4. The name of is_cm4 variable is derived from this.\n\u003e \n\u003e You mean that there is no guarantee that in psoc6 they are real CM0 and CM4 cores, so detecting them from CPU arch could fail?\n\nNo, certainly not in this chip 😊\n\n\u003e Do you think checking the AP-NUM is more reliable?\n\u003e Or you prefer (read below) to keep coreid as generic ID that can be used in these cases?\n\nAs I wrote I have no objection against the new code in this patch.\n\n\u003e \n\u003e \u003e 2) -coreid option name suggests that it was introduced to serve as a general core identification/numbering in a multicore SoC (regardless the SoC is SMP or asymmetric). If the option were named -coresight-rom-table-cpu-index, then yes, this use could be called as an abuse. However with the current name I assume that any use of this option which is not in any contradiction with other existing uses is **correct**\n\u003e \n\u003e I agree, the commit message is incorrect.\n\u003e From the discussion in 7957 I thought you agree on\n\u003e - changing the SMP index using the position in command \u0027target smp\u0027, which is the wider use of coreid;\n\u003e - keep coreid for ROM table parsing;\n\nSure I agree.\n\n\u003e \n\u003e \u003e 3) The option should be documented first and all limiting rules listed\n\u003e \n\u003e Tentative in 8129\n\nGreat! Let\u0027s continue the discussion there.","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7a73ee80527d0be594488ece132f16fe8631c4bd","unresolved":false,"context_lines":[{"line_number":13,"context_line":"This flag has no effects on Cortex-M; ARM specifies that only one"},{"line_number":14,"context_line":"CPU Cortex-M can occupy the AP, using hardcoded addresses."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"The flash driver \u0027psoc6\u0027 abuses the flag \u0027-coreid\u0027 to detect if"},{"line_number":17,"context_line":"the current target is the Cortex-M0 or the Cortex-M4."},{"line_number":18,"context_line":"There are other ways to run such detection, without abusing an"},{"line_number":19,"context_line":"unrelated flag. E.g. the AP number or the arch type."},{"line_number":20,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"58849700_117dbad7","line":17,"range":{"start_line":16,"start_character":25,"end_line":17,"end_character":53},"in_reply_to":"137fabbc_99b27e49","updated":"2024-06-25 07:22:02.000000000","message":"Ack","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"453b3a6886f7dce355e4271761ab36634149bb70","unresolved":true,"context_lines":[{"line_number":13,"context_line":"This flag has no effects on Cortex-M; ARM specifies that only one"},{"line_number":14,"context_line":"CPU Cortex-M can occupy the AP, using hardcoded addresses."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"The flash driver \u0027psoc6\u0027 abuses the flag \u0027-coreid\u0027 to detect if"},{"line_number":17,"context_line":"the current target is the Cortex-M0 or the Cortex-M4."},{"line_number":18,"context_line":"There are other ways to run such detection, without abusing an"},{"line_number":19,"context_line":"unrelated flag. E.g. the AP number or the arch type."},{"line_number":20,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"0bbfe0c8_dce1b672","line":17,"range":{"start_line":16,"start_character":25,"end_line":17,"end_character":53},"in_reply_to":"1cc0104e_d3dcb7ee","updated":"2024-02-03 18:57:40.000000000","message":"\u003e 1) The flash driver primarily needs to know which core is running on - not the type of architecture or CPU. In PSoC6 documentation the cores are referenced as CM0 and CM4. The name of is_cm4 variable is derived from this.\n\nYou mean that there is no guarantee that in psoc6 they are real CM0 and CM4 cores, so detecting them from CPU arch could fail?\nDo you think checking the AP-NUM is more reliable?\nOr you prefer (read below) to keep coreid as generic ID that can be used in these cases?\n\n\u003e 2) -coreid option name suggests that it was introduced to serve as a general core identification/numbering in a multicore SoC (regardless the SoC is SMP or asymmetric). If the option were named -coresight-rom-table-cpu-index, then yes, this use could be called as an abuse. However with the current name I assume that any use of this option which is not in any contradiction with other existing uses is **correct**\n\nI agree, the commit message is incorrect.\nFrom the discussion in 7957 I thought you agree on\n- changing the SMP index using the position in command \u0027target smp\u0027, which is the wider use of coreid;\n- keep coreid for ROM table parsing;\n- find a replacement for the other use cases (like psoc8 and esp32).\n\nBut I probably misunderstood.\nDo you prefer to keep coreid as generic ID and rename the flag used for ROM table idx?\n\n\u003e 3) The option should be documented first and all limiting rules listed\n\nTentative in 8129","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"79e81c7e6463efecf20646e6cdc9c6d53bd68884","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"300772f9_29dfbf97","updated":"2024-02-03 14:11:45.000000000","message":"Not tested, I don\u0027t have the target device.\nThis follows the discussion in\nhttps://review.openocd.org/c/openocd/+/7957\nHint to Rolf about his proposal in\nhttps://review.openocd.org/c/openocd/+/7983","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"e6893e413117d6b0a2919dddec140f6d8b8208be","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2dead190_7a9f9728","updated":"2024-02-03 16:33:07.000000000","message":"The code is probably fine but the commit msg...","commit_id":"55f41b7d8e1d37e74b831a0fbb2e8894fedc0bdc"},{"author":{"_account_id":1001422,"name":"Bohdan Tymkiv","email":"bohdan200@gmail.com","username":"bhdt"},"change_message_id":"8503a219ae0a46585dce88824a11482d4675559e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"537610a4_7ff7c765","updated":"2024-06-25 19:56:00.000000000","message":"Hello gentlemen,\n\nThe multicore MCUs are becoming more and more common these days. Some Cypress/Infineon Traveo-II MCUs have 1xCM0 + 4xCM7, five ARM cores in total + SysAP - six APs in total. I hoped to upstream support for these MCUs someday but I no longer work for Infineon so the chances are close to zero.\n\nNevertheless, the flash driver has to have a way to differentiate between these APs to work properly. \n\nThe one way which comes into my mind is to differentiate the cores using target_to_cortex_m_safe()-\u003edebug_ap-\u003eap_num but PSoC6 and Traveo-II MCUs also have so-called \u0027SysAP\u0027 - AP with no CPU behind it, basically mem_ap. It is possible to program the Flash via SysAP e.g. if all other APs are disabled because of the chip security configuration. Implementing something like `target_to_mem_ap_safe` should allow to differentiate between SysAP and Cortex cores. I\u0027m not sure if this is the proper way, I\u0027ve never tested it before. \n\nAt the time of development PSoC6 flash driver, the most straightforward way to do this was to (ab)use the `-coreid` parameter, it is not used in cortex_m infrastructure anyway.\n\nSincerely,\nBohdan","commit_id":"ebcf46a3460710e436f023a8845b33f644793c8f"}]}